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Draft standard
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IEEE P1012
IEEE Draft Standard for System, Software, and Hardware Verification and Validation
Summary
Revision Standard - Active - Draft.
Verification and validation 1 (V&V) processes are used to determine whether the development products of a given activity conform to the requirements of that activity and whether the product satisfies its intended use and user needs. V&V life cycle process requirements are specified for different integrity levels. The scope of V&V processes encompasses systems, software, and hardware, and it includes their interfaces. This standard applies to systems, software, and hardware being developed, maintained, or reused [legacy, commercial off-the-shelf (COTS), non-developmental items]. The term software also includes firmware and microcode, and each of the terms system, software, and hardware includes related information or documentation. V&V processes include the analysis, evaluation, review, inspection, assessment, and testing of product
This verification and validation (V&V) standard is a process standard that addresses all system, software, and hardware life cycle processes including the Agreement, Organizational Project-Enabling, Project, Technical, Software Implementation, Software Support, and Software Reuse process groups. This standard is compatible with all life cycle models (e.g., system, software, and hardware); however, not all life cycle models use all of the processes listed in this standard. V&V processes determine whether the development products of a given activity conform to the requirements of that activity and whether the product satisfies its intended use and user needs. This determination may include the analysis, evaluation, review, inspection, assessment, and testing of products and processes.
The purpose of this standard is to: - Establish a common framework of the V&V processes, activities, and tasks in support of all system, software, and hardware life cycle processes. - Define the V&V tasks, required inputs, and required outputs in each life cycle process. - Identify the minimum V&V tasks corresponding to a four-level integrity schema. - Define the content of the Verification and Validation Plan.
Verification and validation 1 (V&V) processes are used to determine whether the development products of a given activity conform to the requirements of that activity and whether the product satisfies its intended use and user needs. V&V life cycle process requirements are specified for different integrity levels. The scope of V&V processes encompasses systems, software, and hardware, and it includes their interfaces. This standard applies to systems, software, and hardware being developed, maintained, or reused [legacy, commercial off-the-shelf (COTS), non-developmental items]. The term software also includes firmware and microcode, and each of the terms system, software, and hardware includes related information or documentation. V&V processes include the analysis, evaluation, review, inspection, assessment, and testing of product
This verification and validation (V&V) standard is a process standard that addresses all system, software, and hardware life cycle processes including the Agreement, Organizational Project-Enabling, Project, Technical, Software Implementation, Software Support, and Software Reuse process groups. This standard is compatible with all life cycle models (e.g., system, software, and hardware); however, not all life cycle models use all of the processes listed in this standard. V&V processes determine whether the development products of a given activity conform to the requirements of that activity and whether the product satisfies its intended use and user needs. This determination may include the analysis, evaluation, review, inspection, assessment, and testing of products and processes.
The purpose of this standard is to: - Establish a common framework of the V&V processes, activities, and tasks in support of all system, software, and hardware life cycle processes. - Define the V&V tasks, required inputs, and required outputs in each life cycle process. - Identify the minimum V&V tasks corresponding to a four-level integrity schema. - Define the content of the Verification and Validation Plan.
Notes
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Technical characteristics
| Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| Publication Date | 04/30/2025 |
| Release Date | 04/30/2025 |
| Edition | D21 |
| Page Count | 324 |
| EAN | --- |
| ISBN | --- |
| Weight (in grams) | --- |
| Brochures |
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Amendments replaces
29/09/2017
Superseded
Historical
Previous versions
30/04/2025
Active
Most Recent
29/09/2017
Superseded
Historical
25/05/2012
Superseded
Historical
08/06/2005
Superseded
Historical
IEEE 1012a:1998
IEEE Standard for Software Verification and Validation - Content Map to IEEE 12207.1
21/12/1998
Superseded
Historical
20/07/1998
Superseded
Historical
14/11/1986
Superseded
, Confirmed
Historical