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IEEE/IEC 62526:2007
IEC 62526 Ed. 1 (IEEE Std 1450.1(TM)-2005): Standard for Extensions to Standard Test Interface Language (STIL) for Semiconductor Design Environments
Summary
New IEEE Standard - Active.
Standard Test Interface Language (STIL) provides an interface between digital test
generation tools and test equipment. Extensions to the test interface language (contained in this
standard) are defined that (1) facilitate the use of the language in the design environment and
(2) facilitate the use of the language for large designs encompassing subdesigns with reusable
patterns.
Structures are defined in STIL to support usage as semiconductor simulation stimulus, including
(1) mapping signal names to equivalent design references, (2) interface between scan and built-in self test
(BIST) and the logic simulation, (3) data types to represent unresolved states in a pattern, (4) parallel or
asynchronous pattern execution on different design blocks, and (5) expression-based conditional execution
of pattern constructs.
Structures are defined in STIL to support the definition of test patterns for sub-blocks of a design4
(i.e., embedded cores) such that these tests can be incorporated into a complete higher level device test.
Structures are defined in STIL to relate fail information from device testing environments back to original
stimulus and design data elements.
4 Syntax in this document that is used in the definition of patterns for sub-blocks is summarized in Annex O.
The STIL language definition is enhanced to support the usage of STIL in the design environment, which
includes extending the execution concept to support STIL as a stimulus language, to allow STIL to be used
as an intermediate form of data, and to allow STIL to capture design information needed to port simulation
data to device test environments.
In addition, define extensions to support the definition of subelement tests and to define the mechanisms to
integrate those tests into a complete device test. This effort is to be performed in conjunction with
IEEE Std 1500TM-2005 [B6] and IEEE P1450.6 [B5], which are defining standards for the definition and
integration of embedded cores.
Finally, define the constructs necessary to correlate test failure information back to the design environment,
to allow debug and diagnosis operations to be performed based on failure information in STIL format.
Standard Test Interface Language (STIL) provides an interface between digital test
generation tools and test equipment. Extensions to the test interface language (contained in this
standard) are defined that (1) facilitate the use of the language in the design environment and
(2) facilitate the use of the language for large designs encompassing subdesigns with reusable
patterns.
Structures are defined in STIL to support usage as semiconductor simulation stimulus, including
(1) mapping signal names to equivalent design references, (2) interface between scan and built-in self test
(BIST) and the logic simulation, (3) data types to represent unresolved states in a pattern, (4) parallel or
asynchronous pattern execution on different design blocks, and (5) expression-based conditional execution
of pattern constructs.
Structures are defined in STIL to support the definition of test patterns for sub-blocks of a design4
(i.e., embedded cores) such that these tests can be incorporated into a complete higher level device test.
Structures are defined in STIL to relate fail information from device testing environments back to original
stimulus and design data elements.
4 Syntax in this document that is used in the definition of patterns for sub-blocks is summarized in Annex O.
The STIL language definition is enhanced to support the usage of STIL in the design environment, which
includes extending the execution concept to support STIL as a stimulus language, to allow STIL to be used
as an intermediate form of data, and to allow STIL to capture design information needed to port simulation
data to device test environments.
In addition, define extensions to support the definition of subelement tests and to define the mechanisms to
integrate those tests into a complete device test. This effort is to be performed in conjunction with
IEEE Std 1500TM-2005 [B6] and IEEE P1450.6 [B5], which are defining standards for the definition and
integration of embedded cores.
Finally, define the constructs necessary to correlate test failure information back to the design environment,
to allow debug and diagnosis operations to be performed based on failure information in STIL format.
Notes
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Technical characteristics
| Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| Publication Date | 12/09/2007 |
| Edition | |
| Page Count | 128 |
| EAN | --- |
| ISBN | --- |
| Weight (in grams) | --- |
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