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Standard
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IEEE/IEC 62142:2005
IEC/IEEE International Standard - Verilog(R) Register Transfer Level Synthesis
Summary
- Inactive-Withdrawn.
Replaces IEEE Std 1364.1-2002. To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standard IEEE 1364.
Replaces IEEE Std 1364.1-2002. To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standard IEEE 1364.
Notes
Inactive-Withdrawn
Technical characteristics
| Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| Publication Date | 12/18/2002 |
| Edition | |
| Page Count | 116 |
| EAN | --- |
| ISBN | --- |
| Weight (in grams) | --- |
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Previous versions
18/12/2002
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