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Standard
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IEEE/IEC 61691-4:2004
IEC/IEEE International Standard - Behavioural Languages - Part 4: Verilog(C) Hardware Description Language
Summary
- Inactive-Withdrawn.
The Verilog(R) Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.
The Verilog(R) Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.
Notes
Inactive-Withdrawn
Technical characteristics
| Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| Publication Date | 11/15/2004 |
| Edition | |
| Page Count | 879 |
| EAN | --- |
| ISBN | --- |
| Weight (in grams) | --- |
| Brochures |
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Previous versions
15/11/2004
Withdrawn
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