Symfony Profiler

[
  "product" => App\Entity\Product\Product {#7310
    #id: 10882
    #code: "IEEE00005233"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751039343 {#7274
      date: 2025-06-27 17:49:03.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969918 {#7322
      date: 2025-07-31 15:51:58.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 38537
        #name: "IEEE/IEC 62530:2011"
        #slug: "ieee-iec-62530-2011-ieee00005233-242534"
        #description: """
           - Active.<br />\n
          This standard represents a merger of two previous standards: IEEE Std 1364™-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document.<br />\n
          \t\t\t\t
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "SystemVerilog -- Unified Hardware Design, Specification, and Verification Language"
        -notes: "Active"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1743289200 {#7317
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1305756000 {#7318
      date: 2011-05-19 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "62530"
    -bookCollection: ""
    -pageCount: 1294
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  "showFullLabel" => "true"
]

[
  "showFullLabel" => "true"
]

App\Twig\Components\ProductState {#93066
  +product: App\Entity\Product\Product {#7310
    #id: 10882
    #code: "IEEE00005233"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751039343 {#7274
      date: 2025-06-27 17:49:03.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969918 {#7322
      date: 2025-07-31 15:51:58.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 38537
        #name: "IEEE/IEC 62530:2011"
        #slug: "ieee-iec-62530-2011-ieee00005233-242534"
        #description: """
           - Active.<br />\n
          This standard represents a merger of two previous standards: IEEE Std 1364™-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document.<br />\n
          \t\t\t\t
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "SystemVerilog -- Unified Hardware Design, Specification, and Verification Language"
        -notes: "Active"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1743289200 {#7317
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1305756000 {#7318
      date: 2011-05-19 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "62530"
    -bookCollection: ""
    -pageCount: 1294
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +appearance: "state-active"
  +labels: [
    "Active"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

[
  "product" => App\Entity\Product\Product {#7310
    #id: 10882
    #code: "IEEE00005233"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751039343 {#7274
      date: 2025-06-27 17:49:03.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969918 {#7322
      date: 2025-07-31 15:51:58.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 38537
        #name: "IEEE/IEC 62530:2011"
        #slug: "ieee-iec-62530-2011-ieee00005233-242534"
        #description: """
           - Active.<br />\n
          This standard represents a merger of two previous standards: IEEE Std 1364™-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document.<br />\n
          \t\t\t\t
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "SystemVerilog -- Unified Hardware Design, Specification, and Verification Language"
        -notes: "Active"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1743289200 {#7317
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1305756000 {#7318
      date: 2011-05-19 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "62530"
    -bookCollection: ""
    -pageCount: 1294
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
]

App\Twig\Components\ProductType {#93246
  +product: App\Entity\Product\Product {#7310
    #id: 10882
    #code: "IEEE00005233"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751039343 {#7274
      date: 2025-06-27 17:49:03.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969918 {#7322
      date: 2025-07-31 15:51:58.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 38537
        #name: "IEEE/IEC 62530:2011"
        #slug: "ieee-iec-62530-2011-ieee00005233-242534"
        #description: """
           - Active.<br />\n
          This standard represents a merger of two previous standards: IEEE Std 1364™-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document.<br />\n
          \t\t\t\t
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "SystemVerilog -- Unified Hardware Design, Specification, and Verification Language"
        -notes: "Active"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1743289200 {#7317
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1305756000 {#7318
      date: 2011-05-19 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "62530"
    -bookCollection: ""
    -pageCount: 1294
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +label: "Standard"
  -typeAttributeCode: "type"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

[
  "product" => App\Entity\Product\Product {#7310
    #id: 10882
    #code: "IEEE00005233"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751039343 {#7274
      date: 2025-06-27 17:49:03.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969918 {#7322
      date: 2025-07-31 15:51:58.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 38537
        #name: "IEEE/IEC 62530:2011"
        #slug: "ieee-iec-62530-2011-ieee00005233-242534"
        #description: """
           - Active.<br />\n
          This standard represents a merger of two previous standards: IEEE Std 1364™-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document.<br />\n
          \t\t\t\t
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "SystemVerilog -- Unified Hardware Design, Specification, and Verification Language"
        -notes: "Active"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1743289200 {#7317
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1305756000 {#7318
      date: 2011-05-19 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "62530"
    -bookCollection: ""
    -pageCount: 1294
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
]

App\Twig\Components\ProductMostRecent {#93321
  +product: App\Entity\Product\Product {#7310
    #id: 10882
    #code: "IEEE00005233"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751039343 {#7274
      date: 2025-06-27 17:49:03.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969918 {#7322
      date: 2025-07-31 15:51:58.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 38537
        #name: "IEEE/IEC 62530:2011"
        #slug: "ieee-iec-62530-2011-ieee00005233-242534"
        #description: """
           - Active.<br />\n
          This standard represents a merger of two previous standards: IEEE Std 1364™-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document.<br />\n
          \t\t\t\t
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "SystemVerilog -- Unified Hardware Design, Specification, and Verification Language"
        -notes: "Active"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1743289200 {#7317
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1305756000 {#7318
      date: 2011-05-19 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "62530"
    -bookCollection: ""
    -pageCount: 1294
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +label: "Most Recent"
  +icon: "check-xs"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

[
  "product" => App\Entity\Product\Product {#7310
    #id: 10882
    #code: "IEEE00005233"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751039343 {#7274
      date: 2025-06-27 17:49:03.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969918 {#7322
      date: 2025-07-31 15:51:58.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 38537
        #name: "IEEE/IEC 62530:2011"
        #slug: "ieee-iec-62530-2011-ieee00005233-242534"
        #description: """
           - Active.<br />\n
          This standard represents a merger of two previous standards: IEEE Std 1364™-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document.<br />\n
          \t\t\t\t
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "SystemVerilog -- Unified Hardware Design, Specification, and Verification Language"
        -notes: "Active"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1743289200 {#7317
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1305756000 {#7318
      date: 2011-05-19 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "62530"
    -bookCollection: ""
    -pageCount: 1294
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  "showFullLabel" => "true"
]

[
  "showFullLabel" => "true"
]

App\Twig\Components\ProductState {#100332
  +product: App\Entity\Product\Product {#7310
    #id: 10882
    #code: "IEEE00005233"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751039343 {#7274
      date: 2025-06-27 17:49:03.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969918 {#7322
      date: 2025-07-31 15:51:58.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 38537
        #name: "IEEE/IEC 62530:2011"
        #slug: "ieee-iec-62530-2011-ieee00005233-242534"
        #description: """
           - Active.<br />\n
          This standard represents a merger of two previous standards: IEEE Std 1364™-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document.<br />\n
          \t\t\t\t
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "SystemVerilog -- Unified Hardware Design, Specification, and Verification Language"
        -notes: "Active"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1743289200 {#7317
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1305756000 {#7318
      date: 2011-05-19 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "62530"
    -bookCollection: ""
    -pageCount: 1294
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +appearance: "state-active"
  +labels: [
    "Active"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

[
  "product" => App\Entity\Product\Product {#7310
    #id: 10882
    #code: "IEEE00005233"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751039343 {#7274
      date: 2025-06-27 17:49:03.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969918 {#7322
      date: 2025-07-31 15:51:58.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 38537
        #name: "IEEE/IEC 62530:2011"
        #slug: "ieee-iec-62530-2011-ieee00005233-242534"
        #description: """
           - Active.<br />\n
          This standard represents a merger of two previous standards: IEEE Std 1364™-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document.<br />\n
          \t\t\t\t
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "SystemVerilog -- Unified Hardware Design, Specification, and Verification Language"
        -notes: "Active"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1743289200 {#7317
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1305756000 {#7318
      date: 2011-05-19 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "62530"
    -bookCollection: ""
    -pageCount: 1294
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
]

App\Twig\Components\ProductMostRecent {#100393
  +product: App\Entity\Product\Product {#7310
    #id: 10882
    #code: "IEEE00005233"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751039343 {#7274
      date: 2025-06-27 17:49:03.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969918 {#7322
      date: 2025-07-31 15:51:58.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 38537
        #name: "IEEE/IEC 62530:2011"
        #slug: "ieee-iec-62530-2011-ieee00005233-242534"
        #description: """
           - Active.<br />\n
          This standard represents a merger of two previous standards: IEEE Std 1364™-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document.<br />\n
          \t\t\t\t
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "SystemVerilog -- Unified Hardware Design, Specification, and Verification Language"
        -notes: "Active"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1743289200 {#7317
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1305756000 {#7318
      date: 2011-05-19 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "62530"
    -bookCollection: ""
    -pageCount: 1294
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +label: "Most Recent"
  +icon: "check-xs"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

[
  "product" => App\Entity\Product\Product {#100308
    #id: 10370
    #code: "IEEE00004256"
    #attributes: Doctrine\ORM\PersistentCollection {#100291 …}
    #variants: Doctrine\ORM\PersistentCollection {#100288 …}
    #options: Doctrine\ORM\PersistentCollection {#100284 …}
    #associations: Doctrine\ORM\PersistentCollection {#100286 …}
    #createdAt: DateTime @1751039020 {#100276
      date: 2025-06-27 17:43:40.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#100289
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#100302 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#100467
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#100308}
        #id: 36489
        #name: "IEEE/IEC 62530:2007"
        #slug: "ieee-iec-62530-2007-ieee00004256-242022"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          This standard provides a set of extensions to the IEEE 1364™ Verilog® hardware<br />\n
          description language (HDL) to aid in the creation and verification of abstract architectural level<br />\n
          models. It also includes design specification methods, embedded assertions language, testbench<br />\n
          language including coverage and an assertions application programming interface (API), and a<br />\n
          direct programming interface (DPI). This standard enables a productivity boost in design and<br />\n
          validation and covers design, simulation, validation, and formal assertion-based verification flows.<br />\n
          \t\t\t\t<br />\n
          This standard specifies extensions for a higher level of abstraction for modeling and verification with the<br />\n
          Verilog® hardware description language (HDL). These additions extend Verilog into the systems space and<br />\n
          the verification space. SystemVerilog is built on top of IEEE Std 1364™1 for the Verilog HDL. This<br />\n
          standard includes design specification methods, embedded assertions language, testbench language<br />\n
          including coverage and assertions application programming interface (API), and a direct programming<br />\n
          interface (DPI).<br />\n
          Throughout this standard, the following terms apply:<br />\n
          — Verilog refers to IEEE Std 1364 for the Verilog HDL.<br />\n
          — Verilog-2001 refers to IEEE Std 1364-2001 [B4]2 for the Verilog HDL.<br />\n
          — Verilog-1995 refers to IEEE Std 1364-1995 [B3] for the Verilog HDL.<br />\n
          — SystemVerilog refers to the extensions to the Verilog standard (IEEE Std 1364) as defined in this<br />\n
          standard.<br />\n
          SystemVerilog adds extended and new constructs to Verilog, including the following:<br />\n
          — Extensions to data types for better encapsulation and compactness of code and for tighter<br />\n
          specification<br />\n
          — C data types: int, typedef, struct, union, enum<br />\n
          — Other data types: bounded queues, logic (0, 1, X, Z) and bit (0, 1), tagged unions for safety<br />\n
          — Dynamic data types: string, classes, dynamic queues, dynamic arrays, associative arrays<br />\n
          including automatic memory management freeing users from deallocation issues<br />\n
          — Dynamic casting and bit-stream casting<br />\n
          — Automatic/static specification on a per-variable-instance basis<br />\n
          — Extended operators for concise description<br />\n
          — Wild equality and inequality<br />\n
          — Built-in methods to extend the language<br />\n
          — Operator overloading<br />\n
          — Streaming operators<br />\n
          — Set membership<br />\n
          — Extended procedural statements<br />\n
          — Pattern matching on selection statements for use with tagged unions<br />\n
          — Enhanced loop statements plus the foreach statement<br />\n
          — C-like jump statements: return, break, continue<br />\n
          — final blocks that execute at the end of simulation (inverse of initial)<br />\n
          — Extended event control and sequence events<br />\n
          — Enhanced process control<br />\n
          — Extensions to always blocks to include synthesis consistent simulation semantics<br />\n
          — Extensions to fork…join to model pipelines and for enhanced process control<br />\n
          — Fine-grain process control<br />\n
          — Enhanced tasks and functions<br />\n
          — C-like void functions<br />\n
          — Pass by reference<br />\n
          — Default arguments<br />\n
          — Argument binding by name<br />\n
          — Optional arguments<br />\n
          — Import/export functions for DPI<br />\n
          — Classes: object-oriented mechanism that provides abstraction, encapsulation, and safe pointer<br />\n
          capabilities<br />\n
          — Automated testbench support with random constraints<br />\n
          — Interprocess communication synchronization<br />\n
          — Semaphores<br />\n
          — Mailboxes<br />\n
          — Event extensions, event variables, and event sequencing<br />\n
          — Clarification and extension of the scheduling semantics<br />\n
          — Cycle-based functionality: clocking blocks and cycle-based attributes that help reduce development,<br />\n
          ease maintainability, and promote reusability<br />\n
          — Cycle-based signal drives and samples<br />\n
          — Synchronous samples<br />\n
          SystemVerilog is built on top of IEEE Std 1364. SystemVerilog improves the productivity, readability, and<br />\n
          reusability of Verilog-based code. The language enhancements in SystemVerilog provide more concise<br />\n
          hardware descriptions, while still providing an easy route with existing tools into current hardware<br />\n
          implementation flows. The enhancements also provide extensive support for directed and constrainedrandom<br />\n
          testbench development, coverage-driven verification, and assertion-based verification.<br />\n
          1Information on references can be found in Clause 2.<br />\n
          2The numbers in brackets correspond to the numbers in the bibliography in Annex K.<br />\n
          — Race-free program context<br />\n
          — Assertion mechanism for verifying design intent and functional coverage intent<br />\n
          — Property and sequence declarations<br />\n
          — Assertions and coverage statements with action blocks<br />\n
          — Extended hierarchy support<br />\n
          — Packages for declaration encapsulation with import for controlled access<br />\n
          — Compilation-unit scope nested modules and extern modules for separate compilation support<br />\n
          — Extension of port declarations to support interfaces, events, and variables<br />\n
          — $root to provide unambiguous access using hierarchical references<br />\n
          — Interfaces to encapsulate communication and facilitate communication-oriented design<br />\n
          — Functional coverage<br />\n
          — DPI for clean, efficient interoperation with other languages (C provided)<br />\n
          — Assertion API<br />\n
          — Coverage API<br />\n
          — Data read API<br />\n
          — Verilog procedural interface (VPI) extensions for SystemVerilog constructs<br />\n
          — Concurrent assertion formal semantics
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#100299 …}
    #channels: Doctrine\ORM\PersistentCollection {#100293 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#100297 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#100295 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#100309 …}
    -apiLastModifiedAt: DateTime @1754517600 {#100316
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#100320
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1197154800 {#100274
      date: 2007-12-09 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "62530"
    -bookCollection: ""
    -pageCount: 668
    -documents: Doctrine\ORM\PersistentCollection {#100306 …}
    -favorites: Doctrine\ORM\PersistentCollection {#100304 …}
  }
  "showFullLabel" => "true"
]

[
  "showFullLabel" => "true"
]

App\Twig\Components\ProductState {#100482
  +product: App\Entity\Product\Product {#100308
    #id: 10370
    #code: "IEEE00004256"
    #attributes: Doctrine\ORM\PersistentCollection {#100291 …}
    #variants: Doctrine\ORM\PersistentCollection {#100288 …}
    #options: Doctrine\ORM\PersistentCollection {#100284 …}
    #associations: Doctrine\ORM\PersistentCollection {#100286 …}
    #createdAt: DateTime @1751039020 {#100276
      date: 2025-06-27 17:43:40.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#100289
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#100302 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#100467
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#100308}
        #id: 36489
        #name: "IEEE/IEC 62530:2007"
        #slug: "ieee-iec-62530-2007-ieee00004256-242022"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          This standard provides a set of extensions to the IEEE 1364™ Verilog® hardware<br />\n
          description language (HDL) to aid in the creation and verification of abstract architectural level<br />\n
          models. It also includes design specification methods, embedded assertions language, testbench<br />\n
          language including coverage and an assertions application programming interface (API), and a<br />\n
          direct programming interface (DPI). This standard enables a productivity boost in design and<br />\n
          validation and covers design, simulation, validation, and formal assertion-based verification flows.<br />\n
          \t\t\t\t<br />\n
          This standard specifies extensions for a higher level of abstraction for modeling and verification with the<br />\n
          Verilog® hardware description language (HDL). These additions extend Verilog into the systems space and<br />\n
          the verification space. SystemVerilog is built on top of IEEE Std 1364™1 for the Verilog HDL. This<br />\n
          standard includes design specification methods, embedded assertions language, testbench language<br />\n
          including coverage and assertions application programming interface (API), and a direct programming<br />\n
          interface (DPI).<br />\n
          Throughout this standard, the following terms apply:<br />\n
          — Verilog refers to IEEE Std 1364 for the Verilog HDL.<br />\n
          — Verilog-2001 refers to IEEE Std 1364-2001 [B4]2 for the Verilog HDL.<br />\n
          — Verilog-1995 refers to IEEE Std 1364-1995 [B3] for the Verilog HDL.<br />\n
          — SystemVerilog refers to the extensions to the Verilog standard (IEEE Std 1364) as defined in this<br />\n
          standard.<br />\n
          SystemVerilog adds extended and new constructs to Verilog, including the following:<br />\n
          — Extensions to data types for better encapsulation and compactness of code and for tighter<br />\n
          specification<br />\n
          — C data types: int, typedef, struct, union, enum<br />\n
          — Other data types: bounded queues, logic (0, 1, X, Z) and bit (0, 1), tagged unions for safety<br />\n
          — Dynamic data types: string, classes, dynamic queues, dynamic arrays, associative arrays<br />\n
          including automatic memory management freeing users from deallocation issues<br />\n
          — Dynamic casting and bit-stream casting<br />\n
          — Automatic/static specification on a per-variable-instance basis<br />\n
          — Extended operators for concise description<br />\n
          — Wild equality and inequality<br />\n
          — Built-in methods to extend the language<br />\n
          — Operator overloading<br />\n
          — Streaming operators<br />\n
          — Set membership<br />\n
          — Extended procedural statements<br />\n
          — Pattern matching on selection statements for use with tagged unions<br />\n
          — Enhanced loop statements plus the foreach statement<br />\n
          — C-like jump statements: return, break, continue<br />\n
          — final blocks that execute at the end of simulation (inverse of initial)<br />\n
          — Extended event control and sequence events<br />\n
          — Enhanced process control<br />\n
          — Extensions to always blocks to include synthesis consistent simulation semantics<br />\n
          — Extensions to fork…join to model pipelines and for enhanced process control<br />\n
          — Fine-grain process control<br />\n
          — Enhanced tasks and functions<br />\n
          — C-like void functions<br />\n
          — Pass by reference<br />\n
          — Default arguments<br />\n
          — Argument binding by name<br />\n
          — Optional arguments<br />\n
          — Import/export functions for DPI<br />\n
          — Classes: object-oriented mechanism that provides abstraction, encapsulation, and safe pointer<br />\n
          capabilities<br />\n
          — Automated testbench support with random constraints<br />\n
          — Interprocess communication synchronization<br />\n
          — Semaphores<br />\n
          — Mailboxes<br />\n
          — Event extensions, event variables, and event sequencing<br />\n
          — Clarification and extension of the scheduling semantics<br />\n
          — Cycle-based functionality: clocking blocks and cycle-based attributes that help reduce development,<br />\n
          ease maintainability, and promote reusability<br />\n
          — Cycle-based signal drives and samples<br />\n
          — Synchronous samples<br />\n
          SystemVerilog is built on top of IEEE Std 1364. SystemVerilog improves the productivity, readability, and<br />\n
          reusability of Verilog-based code. The language enhancements in SystemVerilog provide more concise<br />\n
          hardware descriptions, while still providing an easy route with existing tools into current hardware<br />\n
          implementation flows. The enhancements also provide extensive support for directed and constrainedrandom<br />\n
          testbench development, coverage-driven verification, and assertion-based verification.<br />\n
          1Information on references can be found in Clause 2.<br />\n
          2The numbers in brackets correspond to the numbers in the bibliography in Annex K.<br />\n
          — Race-free program context<br />\n
          — Assertion mechanism for verifying design intent and functional coverage intent<br />\n
          — Property and sequence declarations<br />\n
          — Assertions and coverage statements with action blocks<br />\n
          — Extended hierarchy support<br />\n
          — Packages for declaration encapsulation with import for controlled access<br />\n
          — Compilation-unit scope nested modules and extern modules for separate compilation support<br />\n
          — Extension of port declarations to support interfaces, events, and variables<br />\n
          — $root to provide unambiguous access using hierarchical references<br />\n
          — Interfaces to encapsulate communication and facilitate communication-oriented design<br />\n
          — Functional coverage<br />\n
          — DPI for clean, efficient interoperation with other languages (C provided)<br />\n
          — Assertion API<br />\n
          — Coverage API<br />\n
          — Data read API<br />\n
          — Verilog procedural interface (VPI) extensions for SystemVerilog constructs<br />\n
          — Concurrent assertion formal semantics
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#100299 …}
    #channels: Doctrine\ORM\PersistentCollection {#100293 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#100297 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#100295 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#100309 …}
    -apiLastModifiedAt: DateTime @1754517600 {#100316
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#100320
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1197154800 {#100274
      date: 2007-12-09 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "62530"
    -bookCollection: ""
    -pageCount: 668
    -documents: Doctrine\ORM\PersistentCollection {#100306 …}
    -favorites: Doctrine\ORM\PersistentCollection {#100304 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

[
  "product" => App\Entity\Product\Product {#100308
    #id: 10370
    #code: "IEEE00004256"
    #attributes: Doctrine\ORM\PersistentCollection {#100291 …}
    #variants: Doctrine\ORM\PersistentCollection {#100288 …}
    #options: Doctrine\ORM\PersistentCollection {#100284 …}
    #associations: Doctrine\ORM\PersistentCollection {#100286 …}
    #createdAt: DateTime @1751039020 {#100276
      date: 2025-06-27 17:43:40.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#100289
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#100302 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#100467
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#100308}
        #id: 36489
        #name: "IEEE/IEC 62530:2007"
        #slug: "ieee-iec-62530-2007-ieee00004256-242022"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          This standard provides a set of extensions to the IEEE 1364™ Verilog® hardware<br />\n
          description language (HDL) to aid in the creation and verification of abstract architectural level<br />\n
          models. It also includes design specification methods, embedded assertions language, testbench<br />\n
          language including coverage and an assertions application programming interface (API), and a<br />\n
          direct programming interface (DPI). This standard enables a productivity boost in design and<br />\n
          validation and covers design, simulation, validation, and formal assertion-based verification flows.<br />\n
          \t\t\t\t<br />\n
          This standard specifies extensions for a higher level of abstraction for modeling and verification with the<br />\n
          Verilog® hardware description language (HDL). These additions extend Verilog into the systems space and<br />\n
          the verification space. SystemVerilog is built on top of IEEE Std 1364™1 for the Verilog HDL. This<br />\n
          standard includes design specification methods, embedded assertions language, testbench language<br />\n
          including coverage and assertions application programming interface (API), and a direct programming<br />\n
          interface (DPI).<br />\n
          Throughout this standard, the following terms apply:<br />\n
          — Verilog refers to IEEE Std 1364 for the Verilog HDL.<br />\n
          — Verilog-2001 refers to IEEE Std 1364-2001 [B4]2 for the Verilog HDL.<br />\n
          — Verilog-1995 refers to IEEE Std 1364-1995 [B3] for the Verilog HDL.<br />\n
          — SystemVerilog refers to the extensions to the Verilog standard (IEEE Std 1364) as defined in this<br />\n
          standard.<br />\n
          SystemVerilog adds extended and new constructs to Verilog, including the following:<br />\n
          — Extensions to data types for better encapsulation and compactness of code and for tighter<br />\n
          specification<br />\n
          — C data types: int, typedef, struct, union, enum<br />\n
          — Other data types: bounded queues, logic (0, 1, X, Z) and bit (0, 1), tagged unions for safety<br />\n
          — Dynamic data types: string, classes, dynamic queues, dynamic arrays, associative arrays<br />\n
          including automatic memory management freeing users from deallocation issues<br />\n
          — Dynamic casting and bit-stream casting<br />\n
          — Automatic/static specification on a per-variable-instance basis<br />\n
          — Extended operators for concise description<br />\n
          — Wild equality and inequality<br />\n
          — Built-in methods to extend the language<br />\n
          — Operator overloading<br />\n
          — Streaming operators<br />\n
          — Set membership<br />\n
          — Extended procedural statements<br />\n
          — Pattern matching on selection statements for use with tagged unions<br />\n
          — Enhanced loop statements plus the foreach statement<br />\n
          — C-like jump statements: return, break, continue<br />\n
          — final blocks that execute at the end of simulation (inverse of initial)<br />\n
          — Extended event control and sequence events<br />\n
          — Enhanced process control<br />\n
          — Extensions to always blocks to include synthesis consistent simulation semantics<br />\n
          — Extensions to fork…join to model pipelines and for enhanced process control<br />\n
          — Fine-grain process control<br />\n
          — Enhanced tasks and functions<br />\n
          — C-like void functions<br />\n
          — Pass by reference<br />\n
          — Default arguments<br />\n
          — Argument binding by name<br />\n
          — Optional arguments<br />\n
          — Import/export functions for DPI<br />\n
          — Classes: object-oriented mechanism that provides abstraction, encapsulation, and safe pointer<br />\n
          capabilities<br />\n
          — Automated testbench support with random constraints<br />\n
          — Interprocess communication synchronization<br />\n
          — Semaphores<br />\n
          — Mailboxes<br />\n
          — Event extensions, event variables, and event sequencing<br />\n
          — Clarification and extension of the scheduling semantics<br />\n
          — Cycle-based functionality: clocking blocks and cycle-based attributes that help reduce development,<br />\n
          ease maintainability, and promote reusability<br />\n
          — Cycle-based signal drives and samples<br />\n
          — Synchronous samples<br />\n
          SystemVerilog is built on top of IEEE Std 1364. SystemVerilog improves the productivity, readability, and<br />\n
          reusability of Verilog-based code. The language enhancements in SystemVerilog provide more concise<br />\n
          hardware descriptions, while still providing an easy route with existing tools into current hardware<br />\n
          implementation flows. The enhancements also provide extensive support for directed and constrainedrandom<br />\n
          testbench development, coverage-driven verification, and assertion-based verification.<br />\n
          1Information on references can be found in Clause 2.<br />\n
          2The numbers in brackets correspond to the numbers in the bibliography in Annex K.<br />\n
          — Race-free program context<br />\n
          — Assertion mechanism for verifying design intent and functional coverage intent<br />\n
          — Property and sequence declarations<br />\n
          — Assertions and coverage statements with action blocks<br />\n
          — Extended hierarchy support<br />\n
          — Packages for declaration encapsulation with import for controlled access<br />\n
          — Compilation-unit scope nested modules and extern modules for separate compilation support<br />\n
          — Extension of port declarations to support interfaces, events, and variables<br />\n
          — $root to provide unambiguous access using hierarchical references<br />\n
          — Interfaces to encapsulate communication and facilitate communication-oriented design<br />\n
          — Functional coverage<br />\n
          — DPI for clean, efficient interoperation with other languages (C provided)<br />\n
          — Assertion API<br />\n
          — Coverage API<br />\n
          — Data read API<br />\n
          — Verilog procedural interface (VPI) extensions for SystemVerilog constructs<br />\n
          — Concurrent assertion formal semantics
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#100299 …}
    #channels: Doctrine\ORM\PersistentCollection {#100293 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#100297 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#100295 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#100309 …}
    -apiLastModifiedAt: DateTime @1754517600 {#100316
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#100320
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1197154800 {#100274
      date: 2007-12-09 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "62530"
    -bookCollection: ""
    -pageCount: 668
    -documents: Doctrine\ORM\PersistentCollection {#100306 …}
    -favorites: Doctrine\ORM\PersistentCollection {#100304 …}
  }
]

App\Twig\Components\ProductMostRecent {#100534
  +product: App\Entity\Product\Product {#100308
    #id: 10370
    #code: "IEEE00004256"
    #attributes: Doctrine\ORM\PersistentCollection {#100291 …}
    #variants: Doctrine\ORM\PersistentCollection {#100288 …}
    #options: Doctrine\ORM\PersistentCollection {#100284 …}
    #associations: Doctrine\ORM\PersistentCollection {#100286 …}
    #createdAt: DateTime @1751039020 {#100276
      date: 2025-06-27 17:43:40.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#100289
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#100302 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#100467
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#100308}
        #id: 36489
        #name: "IEEE/IEC 62530:2007"
        #slug: "ieee-iec-62530-2007-ieee00004256-242022"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          This standard provides a set of extensions to the IEEE 1364™ Verilog® hardware<br />\n
          description language (HDL) to aid in the creation and verification of abstract architectural level<br />\n
          models. It also includes design specification methods, embedded assertions language, testbench<br />\n
          language including coverage and an assertions application programming interface (API), and a<br />\n
          direct programming interface (DPI). This standard enables a productivity boost in design and<br />\n
          validation and covers design, simulation, validation, and formal assertion-based verification flows.<br />\n
          \t\t\t\t<br />\n
          This standard specifies extensions for a higher level of abstraction for modeling and verification with the<br />\n
          Verilog® hardware description language (HDL). These additions extend Verilog into the systems space and<br />\n
          the verification space. SystemVerilog is built on top of IEEE Std 1364™1 for the Verilog HDL. This<br />\n
          standard includes design specification methods, embedded assertions language, testbench language<br />\n
          including coverage and assertions application programming interface (API), and a direct programming<br />\n
          interface (DPI).<br />\n
          Throughout this standard, the following terms apply:<br />\n
          — Verilog refers to IEEE Std 1364 for the Verilog HDL.<br />\n
          — Verilog-2001 refers to IEEE Std 1364-2001 [B4]2 for the Verilog HDL.<br />\n
          — Verilog-1995 refers to IEEE Std 1364-1995 [B3] for the Verilog HDL.<br />\n
          — SystemVerilog refers to the extensions to the Verilog standard (IEEE Std 1364) as defined in this<br />\n
          standard.<br />\n
          SystemVerilog adds extended and new constructs to Verilog, including the following:<br />\n
          — Extensions to data types for better encapsulation and compactness of code and for tighter<br />\n
          specification<br />\n
          — C data types: int, typedef, struct, union, enum<br />\n
          — Other data types: bounded queues, logic (0, 1, X, Z) and bit (0, 1), tagged unions for safety<br />\n
          — Dynamic data types: string, classes, dynamic queues, dynamic arrays, associative arrays<br />\n
          including automatic memory management freeing users from deallocation issues<br />\n
          — Dynamic casting and bit-stream casting<br />\n
          — Automatic/static specification on a per-variable-instance basis<br />\n
          — Extended operators for concise description<br />\n
          — Wild equality and inequality<br />\n
          — Built-in methods to extend the language<br />\n
          — Operator overloading<br />\n
          — Streaming operators<br />\n
          — Set membership<br />\n
          — Extended procedural statements<br />\n
          — Pattern matching on selection statements for use with tagged unions<br />\n
          — Enhanced loop statements plus the foreach statement<br />\n
          — C-like jump statements: return, break, continue<br />\n
          — final blocks that execute at the end of simulation (inverse of initial)<br />\n
          — Extended event control and sequence events<br />\n
          — Enhanced process control<br />\n
          — Extensions to always blocks to include synthesis consistent simulation semantics<br />\n
          — Extensions to fork…join to model pipelines and for enhanced process control<br />\n
          — Fine-grain process control<br />\n
          — Enhanced tasks and functions<br />\n
          — C-like void functions<br />\n
          — Pass by reference<br />\n
          — Default arguments<br />\n
          — Argument binding by name<br />\n
          — Optional arguments<br />\n
          — Import/export functions for DPI<br />\n
          — Classes: object-oriented mechanism that provides abstraction, encapsulation, and safe pointer<br />\n
          capabilities<br />\n
          — Automated testbench support with random constraints<br />\n
          — Interprocess communication synchronization<br />\n
          — Semaphores<br />\n
          — Mailboxes<br />\n
          — Event extensions, event variables, and event sequencing<br />\n
          — Clarification and extension of the scheduling semantics<br />\n
          — Cycle-based functionality: clocking blocks and cycle-based attributes that help reduce development,<br />\n
          ease maintainability, and promote reusability<br />\n
          — Cycle-based signal drives and samples<br />\n
          — Synchronous samples<br />\n
          SystemVerilog is built on top of IEEE Std 1364. SystemVerilog improves the productivity, readability, and<br />\n
          reusability of Verilog-based code. The language enhancements in SystemVerilog provide more concise<br />\n
          hardware descriptions, while still providing an easy route with existing tools into current hardware<br />\n
          implementation flows. The enhancements also provide extensive support for directed and constrainedrandom<br />\n
          testbench development, coverage-driven verification, and assertion-based verification.<br />\n
          1Information on references can be found in Clause 2.<br />\n
          2The numbers in brackets correspond to the numbers in the bibliography in Annex K.<br />\n
          — Race-free program context<br />\n
          — Assertion mechanism for verifying design intent and functional coverage intent<br />\n
          — Property and sequence declarations<br />\n
          — Assertions and coverage statements with action blocks<br />\n
          — Extended hierarchy support<br />\n
          — Packages for declaration encapsulation with import for controlled access<br />\n
          — Compilation-unit scope nested modules and extern modules for separate compilation support<br />\n
          — Extension of port declarations to support interfaces, events, and variables<br />\n
          — $root to provide unambiguous access using hierarchical references<br />\n
          — Interfaces to encapsulate communication and facilitate communication-oriented design<br />\n
          — Functional coverage<br />\n
          — DPI for clean, efficient interoperation with other languages (C provided)<br />\n
          — Assertion API<br />\n
          — Coverage API<br />\n
          — Data read API<br />\n
          — Verilog procedural interface (VPI) extensions for SystemVerilog constructs<br />\n
          — Concurrent assertion formal semantics
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#100299 …}
    #channels: Doctrine\ORM\PersistentCollection {#100293 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#100297 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#100295 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#100309 …}
    -apiLastModifiedAt: DateTime @1754517600 {#100316
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#100320
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1197154800 {#100274
      date: 2007-12-09 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "62530"
    -bookCollection: ""
    -pageCount: 668
    -documents: Doctrine\ORM\PersistentCollection {#100306 …}
    -favorites: Doctrine\ORM\PersistentCollection {#100304 …}
  }
  +label: "Historical"
  +icon: "historical"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

[
  "product" => App\Entity\Product\Product {#121975
    #id: 9390
    #code: "IEEE00002235"
    #attributes: Doctrine\ORM\PersistentCollection {#121955 …}
    #variants: Doctrine\ORM\PersistentCollection {#121953 …}
    #options: Doctrine\ORM\PersistentCollection {#121948 …}
    #associations: Doctrine\ORM\PersistentCollection {#121950 …}
    #createdAt: DateTime @1751038225 {#121946
      date: 2025-06-27 17:30:25.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#121939
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#121966 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#122090
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#121975}
        #id: 32569
        #name: "IEEE 1497:2001 (R2010)"
        #slug: "ieee-1497-2001-r2010-ieee00002235-241042"
        #description: """
          New IEEE Standard - Inactive-Reserved.<br />\n
          IEC 61523-3: 2004 Dual-logo document. Replaces IEEE Std 1497-2001. The Standard Delay Format (SDF) is defined in this standard. SDF is a textual file format for representing the delay and timing information of electronic systems. While both human and machine readable, in its most common usage it will be machine written and machine read in support of timing analysis and verification tools, and of other tools requiring delay and timing information. The primary audience for this standard is the implementors of tools supporting the format, but anyone with a need to understand the format’s contents will find it useful.<br />\n
          \t\t\t\t<br />\n
          SDF (Standard Delay Format) is an existing OVI standard for the representation and interpretation of timing data for use at any stage of the electronic design process. The ASCII data in the SDF file is represented in a tool and language independent way and includes path delays, timing constraint values, interconnect delays and high level technology parameters.<br />\n
          SDF has come to be accepted as a standard by many companies both in the EDA industry and among their customers, but minor differences have gradually arisen, primarily due to the rapid adoption and evolution. IEEE standardization brings with it an opportunity to reduce and eventually eliminate non-standard implementations and usages of SDF, enhance and improve it based on new input, and also to broaden usage around the world.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Standard Delay Format (SDF) for the Electronic Design Process"
        -notes: "Inactive-Reserved"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#121963 …}
    #channels: Doctrine\ORM\PersistentCollection {#121957 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#121961 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#121959 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#121972 …}
    -apiLastModifiedAt: DateTime @1754517600 {#121932
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1618178400 {#121981
      date: 2021-04-12 00:00:00.0 Europe/Paris (+02:00)
    }
    -author: ""
    -publishedAt: DateTime @1008284400 {#121952
      date: 2001-12-14 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: DateTime @1276725600 {#121933
      date: 2010-06-17 00:00:00.0 Europe/Paris (+02:00)
    }
    -canceledAt: DateTime @1616626800 {#121973
      date: 2021-03-25 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1497"
    -bookCollection: ""
    -pageCount: 80
    -documents: Doctrine\ORM\PersistentCollection {#121970 …}
    -favorites: Doctrine\ORM\PersistentCollection {#121968 …}
  }
  "layout" => "vertical"
  "showPrice" => true
  "showStatusBadges" => true
  "additionalClasses" => "product__teaser--with-grey-border"
  "hasStretchedLink" => true
  "hoverType" => "shadow"
  "linkLabel" => "See more"
]

App\Twig\Components\ProductCard {#122007
  +product: App\Entity\Product\Product {#121975
    #id: 9390
    #code: "IEEE00002235"
    #attributes: Doctrine\ORM\PersistentCollection {#121955 …}
    #variants: Doctrine\ORM\PersistentCollection {#121953 …}
    #options: Doctrine\ORM\PersistentCollection {#121948 …}
    #associations: Doctrine\ORM\PersistentCollection {#121950 …}
    #createdAt: DateTime @1751038225 {#121946
      date: 2025-06-27 17:30:25.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#121939
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#121966 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#122090
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#121975}
        #id: 32569
        #name: "IEEE 1497:2001 (R2010)"
        #slug: "ieee-1497-2001-r2010-ieee00002235-241042"
        #description: """
          New IEEE Standard - Inactive-Reserved.<br />\n
          IEC 61523-3: 2004 Dual-logo document. Replaces IEEE Std 1497-2001. The Standard Delay Format (SDF) is defined in this standard. SDF is a textual file format for representing the delay and timing information of electronic systems. While both human and machine readable, in its most common usage it will be machine written and machine read in support of timing analysis and verification tools, and of other tools requiring delay and timing information. The primary audience for this standard is the implementors of tools supporting the format, but anyone with a need to understand the format’s contents will find it useful.<br />\n
          \t\t\t\t<br />\n
          SDF (Standard Delay Format) is an existing OVI standard for the representation and interpretation of timing data for use at any stage of the electronic design process. The ASCII data in the SDF file is represented in a tool and language independent way and includes path delays, timing constraint values, interconnect delays and high level technology parameters.<br />\n
          SDF has come to be accepted as a standard by many companies both in the EDA industry and among their customers, but minor differences have gradually arisen, primarily due to the rapid adoption and evolution. IEEE standardization brings with it an opportunity to reduce and eventually eliminate non-standard implementations and usages of SDF, enhance and improve it based on new input, and also to broaden usage around the world.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Standard Delay Format (SDF) for the Electronic Design Process"
        -notes: "Inactive-Reserved"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#121963 …}
    #channels: Doctrine\ORM\PersistentCollection {#121957 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#121961 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#121959 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#121972 …}
    -apiLastModifiedAt: DateTime @1754517600 {#121932
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1618178400 {#121981
      date: 2021-04-12 00:00:00.0 Europe/Paris (+02:00)
    }
    -author: ""
    -publishedAt: DateTime @1008284400 {#121952
      date: 2001-12-14 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: DateTime @1276725600 {#121933
      date: 2010-06-17 00:00:00.0 Europe/Paris (+02:00)
    }
    -canceledAt: DateTime @1616626800 {#121973
      date: 2021-03-25 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1497"
    -bookCollection: ""
    -pageCount: 80
    -documents: Doctrine\ORM\PersistentCollection {#121970 …}
    -favorites: Doctrine\ORM\PersistentCollection {#121968 …}
  }
  +layout: "vertical"
  +showPrice: true
  +showStatusBadges: true
  +additionalClasses: "product__teaser--with-grey-border"
  +linkLabel: "See more"
  +imageFilter: "product_thumbnail_teaser"
  +hasStretchedLink: true
  +backgroundColor: "white"
  +hoverType: "shadow"
}

[
  "product" => App\Entity\Product\Product {#121975
    #id: 9390
    #code: "IEEE00002235"
    #attributes: Doctrine\ORM\PersistentCollection {#121955 …}
    #variants: Doctrine\ORM\PersistentCollection {#121953 …}
    #options: Doctrine\ORM\PersistentCollection {#121948 …}
    #associations: Doctrine\ORM\PersistentCollection {#121950 …}
    #createdAt: DateTime @1751038225 {#121946
      date: 2025-06-27 17:30:25.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#121939
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#121966 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#122090
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#121975}
        #id: 32569
        #name: "IEEE 1497:2001 (R2010)"
        #slug: "ieee-1497-2001-r2010-ieee00002235-241042"
        #description: """
          New IEEE Standard - Inactive-Reserved.<br />\n
          IEC 61523-3: 2004 Dual-logo document. Replaces IEEE Std 1497-2001. The Standard Delay Format (SDF) is defined in this standard. SDF is a textual file format for representing the delay and timing information of electronic systems. While both human and machine readable, in its most common usage it will be machine written and machine read in support of timing analysis and verification tools, and of other tools requiring delay and timing information. The primary audience for this standard is the implementors of tools supporting the format, but anyone with a need to understand the format’s contents will find it useful.<br />\n
          \t\t\t\t<br />\n
          SDF (Standard Delay Format) is an existing OVI standard for the representation and interpretation of timing data for use at any stage of the electronic design process. The ASCII data in the SDF file is represented in a tool and language independent way and includes path delays, timing constraint values, interconnect delays and high level technology parameters.<br />\n
          SDF has come to be accepted as a standard by many companies both in the EDA industry and among their customers, but minor differences have gradually arisen, primarily due to the rapid adoption and evolution. IEEE standardization brings with it an opportunity to reduce and eventually eliminate non-standard implementations and usages of SDF, enhance and improve it based on new input, and also to broaden usage around the world.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Standard Delay Format (SDF) for the Electronic Design Process"
        -notes: "Inactive-Reserved"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#121963 …}
    #channels: Doctrine\ORM\PersistentCollection {#121957 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#121961 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#121959 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#121972 …}
    -apiLastModifiedAt: DateTime @1754517600 {#121932
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1618178400 {#121981
      date: 2021-04-12 00:00:00.0 Europe/Paris (+02:00)
    }
    -author: ""
    -publishedAt: DateTime @1008284400 {#121952
      date: 2001-12-14 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: DateTime @1276725600 {#121933
      date: 2010-06-17 00:00:00.0 Europe/Paris (+02:00)
    }
    -canceledAt: DateTime @1616626800 {#121973
      date: 2021-03-25 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1497"
    -bookCollection: ""
    -pageCount: 80
    -documents: Doctrine\ORM\PersistentCollection {#121970 …}
    -favorites: Doctrine\ORM\PersistentCollection {#121968 …}
  }
]

[
  "showFullLabel" => false
]

App\Twig\Components\ProductState {#122094
  +product: App\Entity\Product\Product {#121975
    #id: 9390
    #code: "IEEE00002235"
    #attributes: Doctrine\ORM\PersistentCollection {#121955 …}
    #variants: Doctrine\ORM\PersistentCollection {#121953 …}
    #options: Doctrine\ORM\PersistentCollection {#121948 …}
    #associations: Doctrine\ORM\PersistentCollection {#121950 …}
    #createdAt: DateTime @1751038225 {#121946
      date: 2025-06-27 17:30:25.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#121939
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#121966 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#122090
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#121975}
        #id: 32569
        #name: "IEEE 1497:2001 (R2010)"
        #slug: "ieee-1497-2001-r2010-ieee00002235-241042"
        #description: """
          New IEEE Standard - Inactive-Reserved.<br />\n
          IEC 61523-3: 2004 Dual-logo document. Replaces IEEE Std 1497-2001. The Standard Delay Format (SDF) is defined in this standard. SDF is a textual file format for representing the delay and timing information of electronic systems. While both human and machine readable, in its most common usage it will be machine written and machine read in support of timing analysis and verification tools, and of other tools requiring delay and timing information. The primary audience for this standard is the implementors of tools supporting the format, but anyone with a need to understand the format’s contents will find it useful.<br />\n
          \t\t\t\t<br />\n
          SDF (Standard Delay Format) is an existing OVI standard for the representation and interpretation of timing data for use at any stage of the electronic design process. The ASCII data in the SDF file is represented in a tool and language independent way and includes path delays, timing constraint values, interconnect delays and high level technology parameters.<br />\n
          SDF has come to be accepted as a standard by many companies both in the EDA industry and among their customers, but minor differences have gradually arisen, primarily due to the rapid adoption and evolution. IEEE standardization brings with it an opportunity to reduce and eventually eliminate non-standard implementations and usages of SDF, enhance and improve it based on new input, and also to broaden usage around the world.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Standard Delay Format (SDF) for the Electronic Design Process"
        -notes: "Inactive-Reserved"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#121963 …}
    #channels: Doctrine\ORM\PersistentCollection {#121957 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#121961 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#121959 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#121972 …}
    -apiLastModifiedAt: DateTime @1754517600 {#121932
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1618178400 {#121981
      date: 2021-04-12 00:00:00.0 Europe/Paris (+02:00)
    }
    -author: ""
    -publishedAt: DateTime @1008284400 {#121952
      date: 2001-12-14 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: DateTime @1276725600 {#121933
      date: 2010-06-17 00:00:00.0 Europe/Paris (+02:00)
    }
    -canceledAt: DateTime @1616626800 {#121973
      date: 2021-03-25 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1497"
    -bookCollection: ""
    -pageCount: 80
    -documents: Doctrine\ORM\PersistentCollection {#121970 …}
    -favorites: Doctrine\ORM\PersistentCollection {#121968 …}
  }
  +appearance: "state-withdrawn"
  +labels: [
    "Withdrawn"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

[
  "product" => App\Entity\Product\Product {#121975
    #id: 9390
    #code: "IEEE00002235"
    #attributes: Doctrine\ORM\PersistentCollection {#121955 …}
    #variants: Doctrine\ORM\PersistentCollection {#121953 …}
    #options: Doctrine\ORM\PersistentCollection {#121948 …}
    #associations: Doctrine\ORM\PersistentCollection {#121950 …}
    #createdAt: DateTime @1751038225 {#121946
      date: 2025-06-27 17:30:25.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#121939
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#121966 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#122090
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#121975}
        #id: 32569
        #name: "IEEE 1497:2001 (R2010)"
        #slug: "ieee-1497-2001-r2010-ieee00002235-241042"
        #description: """
          New IEEE Standard - Inactive-Reserved.<br />\n
          IEC 61523-3: 2004 Dual-logo document. Replaces IEEE Std 1497-2001. The Standard Delay Format (SDF) is defined in this standard. SDF is a textual file format for representing the delay and timing information of electronic systems. While both human and machine readable, in its most common usage it will be machine written and machine read in support of timing analysis and verification tools, and of other tools requiring delay and timing information. The primary audience for this standard is the implementors of tools supporting the format, but anyone with a need to understand the format’s contents will find it useful.<br />\n
          \t\t\t\t<br />\n
          SDF (Standard Delay Format) is an existing OVI standard for the representation and interpretation of timing data for use at any stage of the electronic design process. The ASCII data in the SDF file is represented in a tool and language independent way and includes path delays, timing constraint values, interconnect delays and high level technology parameters.<br />\n
          SDF has come to be accepted as a standard by many companies both in the EDA industry and among their customers, but minor differences have gradually arisen, primarily due to the rapid adoption and evolution. IEEE standardization brings with it an opportunity to reduce and eventually eliminate non-standard implementations and usages of SDF, enhance and improve it based on new input, and also to broaden usage around the world.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Standard Delay Format (SDF) for the Electronic Design Process"
        -notes: "Inactive-Reserved"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#121963 …}
    #channels: Doctrine\ORM\PersistentCollection {#121957 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#121961 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#121959 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#121972 …}
    -apiLastModifiedAt: DateTime @1754517600 {#121932
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1618178400 {#121981
      date: 2021-04-12 00:00:00.0 Europe/Paris (+02:00)
    }
    -author: ""
    -publishedAt: DateTime @1008284400 {#121952
      date: 2001-12-14 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: DateTime @1276725600 {#121933
      date: 2010-06-17 00:00:00.0 Europe/Paris (+02:00)
    }
    -canceledAt: DateTime @1616626800 {#121973
      date: 2021-03-25 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1497"
    -bookCollection: ""
    -pageCount: 80
    -documents: Doctrine\ORM\PersistentCollection {#121970 …}
    -favorites: Doctrine\ORM\PersistentCollection {#121968 …}
  }
]

App\Twig\Components\ProductMostRecent {#122172
  +product: App\Entity\Product\Product {#121975
    #id: 9390
    #code: "IEEE00002235"
    #attributes: Doctrine\ORM\PersistentCollection {#121955 …}
    #variants: Doctrine\ORM\PersistentCollection {#121953 …}
    #options: Doctrine\ORM\PersistentCollection {#121948 …}
    #associations: Doctrine\ORM\PersistentCollection {#121950 …}
    #createdAt: DateTime @1751038225 {#121946
      date: 2025-06-27 17:30:25.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#121939
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#121966 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#122090
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#121975}
        #id: 32569
        #name: "IEEE 1497:2001 (R2010)"
        #slug: "ieee-1497-2001-r2010-ieee00002235-241042"
        #description: """
          New IEEE Standard - Inactive-Reserved.<br />\n
          IEC 61523-3: 2004 Dual-logo document. Replaces IEEE Std 1497-2001. The Standard Delay Format (SDF) is defined in this standard. SDF is a textual file format for representing the delay and timing information of electronic systems. While both human and machine readable, in its most common usage it will be machine written and machine read in support of timing analysis and verification tools, and of other tools requiring delay and timing information. The primary audience for this standard is the implementors of tools supporting the format, but anyone with a need to understand the format’s contents will find it useful.<br />\n
          \t\t\t\t<br />\n
          SDF (Standard Delay Format) is an existing OVI standard for the representation and interpretation of timing data for use at any stage of the electronic design process. The ASCII data in the SDF file is represented in a tool and language independent way and includes path delays, timing constraint values, interconnect delays and high level technology parameters.<br />\n
          SDF has come to be accepted as a standard by many companies both in the EDA industry and among their customers, but minor differences have gradually arisen, primarily due to the rapid adoption and evolution. IEEE standardization brings with it an opportunity to reduce and eventually eliminate non-standard implementations and usages of SDF, enhance and improve it based on new input, and also to broaden usage around the world.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Standard Delay Format (SDF) for the Electronic Design Process"
        -notes: "Inactive-Reserved"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#121963 …}
    #channels: Doctrine\ORM\PersistentCollection {#121957 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#121961 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#121959 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#121972 …}
    -apiLastModifiedAt: DateTime @1754517600 {#121932
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1618178400 {#121981
      date: 2021-04-12 00:00:00.0 Europe/Paris (+02:00)
    }
    -author: ""
    -publishedAt: DateTime @1008284400 {#121952
      date: 2001-12-14 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: DateTime @1276725600 {#121933
      date: 2010-06-17 00:00:00.0 Europe/Paris (+02:00)
    }
    -canceledAt: DateTime @1616626800 {#121973
      date: 2021-03-25 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1497"
    -bookCollection: ""
    -pageCount: 80
    -documents: Doctrine\ORM\PersistentCollection {#121970 …}
    -favorites: Doctrine\ORM\PersistentCollection {#121968 …}
  }
  +label: "Most Recent"
  +icon: "check-xs"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

[
  "product" => App\Entity\Product\Product {#121940
    #id: 10090
    #code: "IEEE00003617"
    #attributes: Doctrine\ORM\PersistentCollection {#122024 …}
    #variants: Doctrine\ORM\PersistentCollection {#122023 …}
    #options: Doctrine\ORM\PersistentCollection {#122018 …}
    #associations: Doctrine\ORM\PersistentCollection {#122020 …}
    #createdAt: DateTime @1751038807 {#121945
      date: 2025-06-27 17:40:07.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#121944
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#122021 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#122289
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#121940}
        #id: 35369
        #name: "IEEE 1800:2005"
        #slug: "ieee-1800-2005-ieee00003617-241742"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          This standard represents a merger of two previous standards: IEEE 1364-2005 Verilog hardware description language (HDL) and IEEE 1800-2005 SystemVerilog unified hardware design, specification and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard enables users to have all information regarding syntax and semantics in a single document.<br />\n
          \t\t\t\t<br />\n
          SystemVerilog is a Unified Hardware Design, Specification and Verification language that is based on the work done by Accellera, a consortium of Electronic Design Automation (EDA), semiconductor, and system companies. The proposed project will create an IEEE standard that is leveraged from Accellera SystemVerilog 3.1a. The new standard will include design specification methods, embedded assertions language, test bench language including coverage and assertions API, and a direct programming interface. The proposed SystemVerilog standard enables a productivity boost in design and validation, and covers design, simulation, validation, and formal assertion based verification flows.<br />\n
          The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a well-defined and official IEEE Unified Hardware Design, Specification and Verification standard language. The language is designed to co-exist and enhance those hardware description languages presently used by designers while providing the capabilities lacking in those languages.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog: Unified Hardware Design, Specification and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#122006 …}
    #channels: Doctrine\ORM\PersistentCollection {#122029 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#121984 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#122030 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#121938 …}
    -apiLastModifiedAt: DateTime @1754517600 {#121943
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#121942
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1132614000 {#121941
      date: 2005-11-22 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 648
    -documents: Doctrine\ORM\PersistentCollection {#121936 …}
    -favorites: Doctrine\ORM\PersistentCollection {#121929 …}
  }
  "layout" => "vertical"
  "showPrice" => true
  "showStatusBadges" => true
  "additionalClasses" => "product__teaser--with-grey-border"
  "hasStretchedLink" => true
  "hoverType" => "shadow"
  "linkLabel" => "See more"
]

App\Twig\Components\ProductCard {#122247
  +product: App\Entity\Product\Product {#121940
    #id: 10090
    #code: "IEEE00003617"
    #attributes: Doctrine\ORM\PersistentCollection {#122024 …}
    #variants: Doctrine\ORM\PersistentCollection {#122023 …}
    #options: Doctrine\ORM\PersistentCollection {#122018 …}
    #associations: Doctrine\ORM\PersistentCollection {#122020 …}
    #createdAt: DateTime @1751038807 {#121945
      date: 2025-06-27 17:40:07.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#121944
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#122021 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#122289
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#121940}
        #id: 35369
        #name: "IEEE 1800:2005"
        #slug: "ieee-1800-2005-ieee00003617-241742"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          This standard represents a merger of two previous standards: IEEE 1364-2005 Verilog hardware description language (HDL) and IEEE 1800-2005 SystemVerilog unified hardware design, specification and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard enables users to have all information regarding syntax and semantics in a single document.<br />\n
          \t\t\t\t<br />\n
          SystemVerilog is a Unified Hardware Design, Specification and Verification language that is based on the work done by Accellera, a consortium of Electronic Design Automation (EDA), semiconductor, and system companies. The proposed project will create an IEEE standard that is leveraged from Accellera SystemVerilog 3.1a. The new standard will include design specification methods, embedded assertions language, test bench language including coverage and assertions API, and a direct programming interface. The proposed SystemVerilog standard enables a productivity boost in design and validation, and covers design, simulation, validation, and formal assertion based verification flows.<br />\n
          The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a well-defined and official IEEE Unified Hardware Design, Specification and Verification standard language. The language is designed to co-exist and enhance those hardware description languages presently used by designers while providing the capabilities lacking in those languages.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog: Unified Hardware Design, Specification and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#122006 …}
    #channels: Doctrine\ORM\PersistentCollection {#122029 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#121984 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#122030 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#121938 …}
    -apiLastModifiedAt: DateTime @1754517600 {#121943
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#121942
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1132614000 {#121941
      date: 2005-11-22 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 648
    -documents: Doctrine\ORM\PersistentCollection {#121936 …}
    -favorites: Doctrine\ORM\PersistentCollection {#121929 …}
  }
  +layout: "vertical"
  +showPrice: true
  +showStatusBadges: true
  +additionalClasses: "product__teaser--with-grey-border"
  +linkLabel: "See more"
  +imageFilter: "product_thumbnail_teaser"
  +hasStretchedLink: true
  +backgroundColor: "white"
  +hoverType: "shadow"
}

[
  "product" => App\Entity\Product\Product {#121940
    #id: 10090
    #code: "IEEE00003617"
    #attributes: Doctrine\ORM\PersistentCollection {#122024 …}
    #variants: Doctrine\ORM\PersistentCollection {#122023 …}
    #options: Doctrine\ORM\PersistentCollection {#122018 …}
    #associations: Doctrine\ORM\PersistentCollection {#122020 …}
    #createdAt: DateTime @1751038807 {#121945
      date: 2025-06-27 17:40:07.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#121944
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#122021 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#122289
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#121940}
        #id: 35369
        #name: "IEEE 1800:2005"
        #slug: "ieee-1800-2005-ieee00003617-241742"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          This standard represents a merger of two previous standards: IEEE 1364-2005 Verilog hardware description language (HDL) and IEEE 1800-2005 SystemVerilog unified hardware design, specification and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard enables users to have all information regarding syntax and semantics in a single document.<br />\n
          \t\t\t\t<br />\n
          SystemVerilog is a Unified Hardware Design, Specification and Verification language that is based on the work done by Accellera, a consortium of Electronic Design Automation (EDA), semiconductor, and system companies. The proposed project will create an IEEE standard that is leveraged from Accellera SystemVerilog 3.1a. The new standard will include design specification methods, embedded assertions language, test bench language including coverage and assertions API, and a direct programming interface. The proposed SystemVerilog standard enables a productivity boost in design and validation, and covers design, simulation, validation, and formal assertion based verification flows.<br />\n
          The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a well-defined and official IEEE Unified Hardware Design, Specification and Verification standard language. The language is designed to co-exist and enhance those hardware description languages presently used by designers while providing the capabilities lacking in those languages.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog: Unified Hardware Design, Specification and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#122006 …}
    #channels: Doctrine\ORM\PersistentCollection {#122029 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#121984 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#122030 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#121938 …}
    -apiLastModifiedAt: DateTime @1754517600 {#121943
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#121942
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1132614000 {#121941
      date: 2005-11-22 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 648
    -documents: Doctrine\ORM\PersistentCollection {#121936 …}
    -favorites: Doctrine\ORM\PersistentCollection {#121929 …}
  }
]

[
  "showFullLabel" => false
]

App\Twig\Components\ProductState {#122296
  +product: App\Entity\Product\Product {#121940
    #id: 10090
    #code: "IEEE00003617"
    #attributes: Doctrine\ORM\PersistentCollection {#122024 …}
    #variants: Doctrine\ORM\PersistentCollection {#122023 …}
    #options: Doctrine\ORM\PersistentCollection {#122018 …}
    #associations: Doctrine\ORM\PersistentCollection {#122020 …}
    #createdAt: DateTime @1751038807 {#121945
      date: 2025-06-27 17:40:07.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#121944
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#122021 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#122289
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#121940}
        #id: 35369
        #name: "IEEE 1800:2005"
        #slug: "ieee-1800-2005-ieee00003617-241742"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          This standard represents a merger of two previous standards: IEEE 1364-2005 Verilog hardware description language (HDL) and IEEE 1800-2005 SystemVerilog unified hardware design, specification and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard enables users to have all information regarding syntax and semantics in a single document.<br />\n
          \t\t\t\t<br />\n
          SystemVerilog is a Unified Hardware Design, Specification and Verification language that is based on the work done by Accellera, a consortium of Electronic Design Automation (EDA), semiconductor, and system companies. The proposed project will create an IEEE standard that is leveraged from Accellera SystemVerilog 3.1a. The new standard will include design specification methods, embedded assertions language, test bench language including coverage and assertions API, and a direct programming interface. The proposed SystemVerilog standard enables a productivity boost in design and validation, and covers design, simulation, validation, and formal assertion based verification flows.<br />\n
          The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a well-defined and official IEEE Unified Hardware Design, Specification and Verification standard language. The language is designed to co-exist and enhance those hardware description languages presently used by designers while providing the capabilities lacking in those languages.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog: Unified Hardware Design, Specification and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#122006 …}
    #channels: Doctrine\ORM\PersistentCollection {#122029 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#121984 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#122030 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#121938 …}
    -apiLastModifiedAt: DateTime @1754517600 {#121943
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#121942
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1132614000 {#121941
      date: 2005-11-22 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 648
    -documents: Doctrine\ORM\PersistentCollection {#121936 …}
    -favorites: Doctrine\ORM\PersistentCollection {#121929 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

[
  "product" => App\Entity\Product\Product {#121940
    #id: 10090
    #code: "IEEE00003617"
    #attributes: Doctrine\ORM\PersistentCollection {#122024 …}
    #variants: Doctrine\ORM\PersistentCollection {#122023 …}
    #options: Doctrine\ORM\PersistentCollection {#122018 …}
    #associations: Doctrine\ORM\PersistentCollection {#122020 …}
    #createdAt: DateTime @1751038807 {#121945
      date: 2025-06-27 17:40:07.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#121944
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#122021 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#122289
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#121940}
        #id: 35369
        #name: "IEEE 1800:2005"
        #slug: "ieee-1800-2005-ieee00003617-241742"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          This standard represents a merger of two previous standards: IEEE 1364-2005 Verilog hardware description language (HDL) and IEEE 1800-2005 SystemVerilog unified hardware design, specification and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard enables users to have all information regarding syntax and semantics in a single document.<br />\n
          \t\t\t\t<br />\n
          SystemVerilog is a Unified Hardware Design, Specification and Verification language that is based on the work done by Accellera, a consortium of Electronic Design Automation (EDA), semiconductor, and system companies. The proposed project will create an IEEE standard that is leveraged from Accellera SystemVerilog 3.1a. The new standard will include design specification methods, embedded assertions language, test bench language including coverage and assertions API, and a direct programming interface. The proposed SystemVerilog standard enables a productivity boost in design and validation, and covers design, simulation, validation, and formal assertion based verification flows.<br />\n
          The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a well-defined and official IEEE Unified Hardware Design, Specification and Verification standard language. The language is designed to co-exist and enhance those hardware description languages presently used by designers while providing the capabilities lacking in those languages.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog: Unified Hardware Design, Specification and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#122006 …}
    #channels: Doctrine\ORM\PersistentCollection {#122029 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#121984 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#122030 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#121938 …}
    -apiLastModifiedAt: DateTime @1754517600 {#121943
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#121942
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1132614000 {#121941
      date: 2005-11-22 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 648
    -documents: Doctrine\ORM\PersistentCollection {#121936 …}
    -favorites: Doctrine\ORM\PersistentCollection {#121929 …}
  }
]

App\Twig\Components\ProductMostRecent {#122373
  +product: App\Entity\Product\Product {#121940
    #id: 10090
    #code: "IEEE00003617"
    #attributes: Doctrine\ORM\PersistentCollection {#122024 …}
    #variants: Doctrine\ORM\PersistentCollection {#122023 …}
    #options: Doctrine\ORM\PersistentCollection {#122018 …}
    #associations: Doctrine\ORM\PersistentCollection {#122020 …}
    #createdAt: DateTime @1751038807 {#121945
      date: 2025-06-27 17:40:07.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#121944
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#122021 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#122289
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#121940}
        #id: 35369
        #name: "IEEE 1800:2005"
        #slug: "ieee-1800-2005-ieee00003617-241742"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          This standard represents a merger of two previous standards: IEEE 1364-2005 Verilog hardware description language (HDL) and IEEE 1800-2005 SystemVerilog unified hardware design, specification and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard enables users to have all information regarding syntax and semantics in a single document.<br />\n
          \t\t\t\t<br />\n
          SystemVerilog is a Unified Hardware Design, Specification and Verification language that is based on the work done by Accellera, a consortium of Electronic Design Automation (EDA), semiconductor, and system companies. The proposed project will create an IEEE standard that is leveraged from Accellera SystemVerilog 3.1a. The new standard will include design specification methods, embedded assertions language, test bench language including coverage and assertions API, and a direct programming interface. The proposed SystemVerilog standard enables a productivity boost in design and validation, and covers design, simulation, validation, and formal assertion based verification flows.<br />\n
          The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a well-defined and official IEEE Unified Hardware Design, Specification and Verification standard language. The language is designed to co-exist and enhance those hardware description languages presently used by designers while providing the capabilities lacking in those languages.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog: Unified Hardware Design, Specification and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#122006 …}
    #channels: Doctrine\ORM\PersistentCollection {#122029 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#121984 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#122030 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#121938 …}
    -apiLastModifiedAt: DateTime @1754517600 {#121943
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#121942
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1132614000 {#121941
      date: 2005-11-22 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 648
    -documents: Doctrine\ORM\PersistentCollection {#121936 …}
    -favorites: Doctrine\ORM\PersistentCollection {#121929 …}
  }
  +label: "Historical"
  +icon: "historical"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}