Components
6
Twig Components
18
Render Count
38
ms
Render Time
260.0
MiB
Memory Usage
Components
| Name | Metadata | Render Count | Render Time |
|---|---|---|---|
| ProductCard |
"App\Twig\Components\ProductCard"components/ProductCard.html.twig |
5 | 33.15ms |
| ProductState |
"App\Twig\Components\ProductState"components/ProductState.html.twig |
5 | 0.84ms |
| ProductMostRecent |
"App\Twig\Components\ProductMostRecent"components/ProductMostRecent.html.twig |
5 | 3.08ms |
| PageBanner |
"App\Twig\Components\PageBanner"components/PageBanner.html.twig |
1 | 4.67ms |
| BackButton |
"App\Twig\Components\BackButton"components/BackButton.html.twig |
1 | 0.23ms |
| ResponsiveCollapsibleGrid |
"App\Twig\Components\ResponsiveCollapsibleGrid"components/ResponsiveCollapsibleGrid.html.twig |
1 | 0.57ms |
Render calls
| PageBanner | App\Twig\Components\PageBanner | 260.0 MiB | 4.67 ms | |
|---|---|---|---|---|
| Input props | [ "backLabel" => "31 : Electronics" "backUrl" => "/taxons/main/ics-2277/31-electronics-4445" "paddingClasses" => "p-2 px-lg-5 py-lg-0" "searchPlaceholder" => "sylius.ui.search" "showSearch" => "true" "title" => "31.080 : Semiconductor devices" ] |
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| Attributes | [] |
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| Component | App\Twig\Components\PageBanner {#94294 +supTitle: null +title: "31.080 : Semiconductor devices" +subTitle: null +backUrl: "/taxons/main/ics-2277/31-electronics-4445" +backLabel: "31 : Electronics" +customClasses: null +backgroundType: null +centered: true +showSearch: true +searchPlaceholder: "sylius.ui.search" +searchValue: null +paddingClasses: "p-2 px-lg-5 py-lg-0" } |
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| BackButton | App\Twig\Components\BackButton | 260.0 MiB | 0.23 ms | |
|---|---|---|---|---|
| Input props | [ "url" => "/taxons/main/ics-2277/31-electronics-4445" "label" => "31 : Electronics" ] |
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| Attributes | [] |
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| Component | App\Twig\Components\BackButton {#94385 +label: "31 : Electronics" +url: "/taxons/main/ics-2277/31-electronics-4445" } |
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| ResponsiveCollapsibleGrid | App\Twig\Components\ResponsiveCollapsibleGrid | 260.0 MiB | 0.57 ms | |
|---|---|---|---|---|
| Input props | [ "items" => Doctrine\ORM\PersistentCollection {#8717 #collection: Doctrine\Common\Collections\ArrayCollection {#8663 …} #initialized: true -snapshot: [ …5] -owner: App\Entity\Taxonomy\Taxon {#8646 …} -association: [ …16] -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#773 …} -backRefFieldName: "parent" -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#130465 …} -isDirty: false } "responsiveItemsPerRow" => [ "mobile" => 2 "tablet" => 4 "desktop" => 6 ] "responsiveVisibleRows" => [ "mobile" => 50 "tablet" => 25 "desktop" => 17 ] "containerClass" => "taxon-grid-subcategories-listing mb-4 px-4 px-sm-0" "itemTemplate" => "@BitBagSyliusElasticsearchPlugin/Shop/Product/Index/DisplayStyle/_grid_subcategory_item.html.twig" "showMoreText" => "app.ui.collapsible_choices.show_more" "showLessText" => "app.ui.collapsible_choices.show_less" ] |
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| Attributes | [] |
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| Component | App\Twig\Components\ResponsiveCollapsibleGrid {#94572 +items: Doctrine\ORM\PersistentCollection {#8717 #collection: Doctrine\Common\Collections\ArrayCollection {#8663 …} #initialized: true -snapshot: [ …5] -owner: App\Entity\Taxonomy\Taxon {#8646 …} -association: [ …16] -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#773 …} -backRefFieldName: "parent" -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#130465 …} -isDirty: false } +responsiveItemsPerRow: [ "mobile" => 2 "tablet" => 4 "desktop" => 6 ] +responsiveVisibleRows: [ "mobile" => 50 "tablet" => 25 "desktop" => 17 ] +containerClass: "taxon-grid-subcategories-listing mb-4 px-4 px-sm-0" +buttonClass: "" +itemTemplate: "@BitBagSyliusElasticsearchPlugin/Shop/Product/Index/DisplayStyle/_grid_subcategory_item.html.twig" +showMoreText: "app.ui.collapsible_choices.show_more" +showLessText: "app.ui.collapsible_choices.show_less" +gridItemsIdentifierClass: "responsive-collapsible-grid-item-442007" } |
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| ProductCard | App\Twig\Components\ProductCard | 260.0 MiB | 10.36 ms | |
|---|---|---|---|---|
| Input props | [ "product" => App\Entity\Product\Product {#95002 #id: 10557 #code: "IEEE00004604" #attributes: Doctrine\ORM\PersistentCollection {#95065 …} #variants: Doctrine\ORM\PersistentCollection {#95063 …} #options: Doctrine\ORM\PersistentCollection {#95059 …} #associations: Doctrine\ORM\PersistentCollection {#95061 …} #createdAt: DateTime @1751039135 {#95001 : 2025-06-27 17:45:35.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608190 {#95009 : 2025-08-08 01:09:50.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#95075 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#95296 #locale: "en_US" #translatable: App\Entity\Product\Product {#95002} #id: 37237 #name: "IEEE 1804:2017" #slug: "ieee-1804-2017-ieee00004604-242209" #description: """ New IEEE Standard - Active.<br />\n The standard formalizes aspects of fault models as they are relevant to the generation of test patterns for digital circuits. Its scope includes (i) fault counting, (ii) fault classification, and (iii) fault coverage reporting across different ATPG (automatic test pattern generation) tools, for the single stuck-at fault model. With this standard, it shall be incumbent on all ATPG tools (which comply with this standard) to report fault coverage in a uniform way. This will facilitate the generation of a uniform coverage (and hence a uniform test quality) metric for large chips (including systems-on-chips – SOCs) with different cores and modules, for which test patterns have been independently generated.<br />\n \t\t\t\t<br />\n This standard formalizes aspects of the stuck-at fault model as they are relevant to the generation of test patterns for digital circuits. Its scope includes a) fault counting, b) fault classification, and c) fault coverage reporting across different automatic test pattern generation (ATPG) tools, for the single stuck-at fault model. Fault grading and simulation is limited to the Verilog gate level representation of a digital circuit. With this standard, it shall be incumbent on all ATPG tools (that comply with this standard) to report fault coverage in a uniform way. This can facilitate the generation of a uniform coverage (and hence a test quality) metric for large chips with different cores and modules, for which test patterns have been independently generated using an ATPG tool, or have been supplied externally and have been simulated using an ATPG tool to ascertain the fault coverage.<br />\n Digital circuits have various structural representations either in high level hardware description languages (HDLs) which can then be synthesized, or in netlist forms. Commercial tools today for Automatic Test Pattern Generation (ATPG) using algorithmic techniques operate on a structural netlist of the Design Under Test (DUT). The test quality signoff process mandatorily includes a minimal coverage requirement, to<br />\n 19 be obtained using these ATPG tool generated patterns on the DUT. This motivates the need for standard processes for (i) counting faults across different fault models, (ii) classifying these faults, and (iii) reporting the coverage, across different ATPG tools which are used to generate test patterns for these digital circuits. Such standard processes shall enable test qualification based on ATPG tool generated<br />\n 24 patterns and based upon fault coverage metrics in a uniform way and independent of the ATPG tool used. A uniform fault coverage and pattern count based metric can now be generated for large chips with complex functionality. Such metric are commonly used in today’s system-on-chips (SOCs) with a heterogeneous mix of modules thereein, often consisting of intellectual property (IP) cores (which are often sourced from design teams different from those designing the chips themselves), and test patterns for which are generated using different ATPG tools. This points to the need for such a standard. This standard shall help to build consensus amongst the chip designers, tool vendors and end customers of integrated circuits. The coverage metrics reported by the designers shall be consistent across all tools. Coverage requirements set by the customers can now also be uniformly targeted by the designers, independent of the ATPG tool used. The standard will also help in merging coverage reports from different tools when different IPs are integrated into an SOC. In the first version of this standard, only the classical stuck-at 0 and stuck-at 1 fault model shall be considered. The following are outside the scope of this document: a) Standards on ATPG algorithms, ATPG efficiency 1 (speed, memory), fault grading efficiency, fault models other than the stuck-at fault model, test vector compaction. b) Standards on how a gate-level netlist is created for a design. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Fault Accounting and Coverage Reporting(FACR) for Digital Modules" -notes: "Active" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#95073 …} #channels: Doctrine\ORM\PersistentCollection {#95067 …} #mainTaxon: App\Entity\Taxonomy\Taxon {#8838 …} #reviews: Doctrine\ORM\PersistentCollection {#95071 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#95069 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#95082 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#95081 …} -apiLastModifiedAt: DateTime @1754517600 {#95014 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#95017 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1517353200 {#95015 : 2018-01-31 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1804" -bookCollection: "" -pageCount: 29 -documents: Doctrine\ORM\PersistentCollection {#95079 …} -favorites: Doctrine\ORM\PersistentCollection {#95077 …} } "layout" => "vertical" "showPrice" => true "showStatusBadges" => true "imageFilter" => "product_listing_thumbnail" "additionalClasses" => "h-100 border-0" "hasStretchedLink" => true "backgroundColor" => "white" "hoverType" => "border-black" ] |
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| Attributes | [] |
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| Component | App\Twig\Components\ProductCard {#95181 +product: App\Entity\Product\Product {#95002 #id: 10557 #code: "IEEE00004604" #attributes: Doctrine\ORM\PersistentCollection {#95065 …} #variants: Doctrine\ORM\PersistentCollection {#95063 …} #options: Doctrine\ORM\PersistentCollection {#95059 …} #associations: Doctrine\ORM\PersistentCollection {#95061 …} #createdAt: DateTime @1751039135 {#95001 : 2025-06-27 17:45:35.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608190 {#95009 : 2025-08-08 01:09:50.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#95075 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#95296 #locale: "en_US" #translatable: App\Entity\Product\Product {#95002} #id: 37237 #name: "IEEE 1804:2017" #slug: "ieee-1804-2017-ieee00004604-242209" #description: """ New IEEE Standard - Active.<br />\n The standard formalizes aspects of fault models as they are relevant to the generation of test patterns for digital circuits. Its scope includes (i) fault counting, (ii) fault classification, and (iii) fault coverage reporting across different ATPG (automatic test pattern generation) tools, for the single stuck-at fault model. With this standard, it shall be incumbent on all ATPG tools (which comply with this standard) to report fault coverage in a uniform way. This will facilitate the generation of a uniform coverage (and hence a uniform test quality) metric for large chips (including systems-on-chips – SOCs) with different cores and modules, for which test patterns have been independently generated.<br />\n \t\t\t\t<br />\n This standard formalizes aspects of the stuck-at fault model as they are relevant to the generation of test patterns for digital circuits. Its scope includes a) fault counting, b) fault classification, and c) fault coverage reporting across different automatic test pattern generation (ATPG) tools, for the single stuck-at fault model. Fault grading and simulation is limited to the Verilog gate level representation of a digital circuit. With this standard, it shall be incumbent on all ATPG tools (that comply with this standard) to report fault coverage in a uniform way. This can facilitate the generation of a uniform coverage (and hence a test quality) metric for large chips with different cores and modules, for which test patterns have been independently generated using an ATPG tool, or have been supplied externally and have been simulated using an ATPG tool to ascertain the fault coverage.<br />\n Digital circuits have various structural representations either in high level hardware description languages (HDLs) which can then be synthesized, or in netlist forms. Commercial tools today for Automatic Test Pattern Generation (ATPG) using algorithmic techniques operate on a structural netlist of the Design Under Test (DUT). The test quality signoff process mandatorily includes a minimal coverage requirement, to<br />\n 19 be obtained using these ATPG tool generated patterns on the DUT. This motivates the need for standard processes for (i) counting faults across different fault models, (ii) classifying these faults, and (iii) reporting the coverage, across different ATPG tools which are used to generate test patterns for these digital circuits. Such standard processes shall enable test qualification based on ATPG tool generated<br />\n 24 patterns and based upon fault coverage metrics in a uniform way and independent of the ATPG tool used. A uniform fault coverage and pattern count based metric can now be generated for large chips with complex functionality. Such metric are commonly used in today’s system-on-chips (SOCs) with a heterogeneous mix of modules thereein, often consisting of intellectual property (IP) cores (which are often sourced from design teams different from those designing the chips themselves), and test patterns for which are generated using different ATPG tools. This points to the need for such a standard. This standard shall help to build consensus amongst the chip designers, tool vendors and end customers of integrated circuits. The coverage metrics reported by the designers shall be consistent across all tools. Coverage requirements set by the customers can now also be uniformly targeted by the designers, independent of the ATPG tool used. The standard will also help in merging coverage reports from different tools when different IPs are integrated into an SOC. In the first version of this standard, only the classical stuck-at 0 and stuck-at 1 fault model shall be considered. The following are outside the scope of this document: a) Standards on ATPG algorithms, ATPG efficiency 1 (speed, memory), fault grading efficiency, fault models other than the stuck-at fault model, test vector compaction. b) Standards on how a gate-level netlist is created for a design. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Fault Accounting and Coverage Reporting(FACR) for Digital Modules" -notes: "Active" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#95073 …} #channels: Doctrine\ORM\PersistentCollection {#95067 …} #mainTaxon: App\Entity\Taxonomy\Taxon {#8838 …} #reviews: Doctrine\ORM\PersistentCollection {#95071 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#95069 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#95082 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#95081 …} -apiLastModifiedAt: DateTime @1754517600 {#95014 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#95017 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1517353200 {#95015 : 2018-01-31 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1804" -bookCollection: "" -pageCount: 29 -documents: Doctrine\ORM\PersistentCollection {#95079 …} -favorites: Doctrine\ORM\PersistentCollection {#95077 …} } +layout: "vertical" +showPrice: true +showStatusBadges: true +additionalClasses: "h-100 border-0" +linkLabel: "" +imageFilter: "product_listing_thumbnail" +hasStretchedLink: true +backgroundColor: "white" +hoverType: "border-black" } |
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| ProductState | App\Twig\Components\ProductState | 260.0 MiB | 0.22 ms | |
|---|---|---|---|---|
| Input props | [ "product" => App\Entity\Product\Product {#95002 #id: 10557 #code: "IEEE00004604" #attributes: Doctrine\ORM\PersistentCollection {#95065 …} #variants: Doctrine\ORM\PersistentCollection {#95063 …} #options: Doctrine\ORM\PersistentCollection {#95059 …} #associations: Doctrine\ORM\PersistentCollection {#95061 …} #createdAt: DateTime @1751039135 {#95001 : 2025-06-27 17:45:35.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608190 {#95009 : 2025-08-08 01:09:50.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#95075 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#95296 #locale: "en_US" #translatable: App\Entity\Product\Product {#95002} #id: 37237 #name: "IEEE 1804:2017" #slug: "ieee-1804-2017-ieee00004604-242209" #description: """ New IEEE Standard - Active.<br />\n The standard formalizes aspects of fault models as they are relevant to the generation of test patterns for digital circuits. Its scope includes (i) fault counting, (ii) fault classification, and (iii) fault coverage reporting across different ATPG (automatic test pattern generation) tools, for the single stuck-at fault model. With this standard, it shall be incumbent on all ATPG tools (which comply with this standard) to report fault coverage in a uniform way. This will facilitate the generation of a uniform coverage (and hence a uniform test quality) metric for large chips (including systems-on-chips – SOCs) with different cores and modules, for which test patterns have been independently generated.<br />\n \t\t\t\t<br />\n This standard formalizes aspects of the stuck-at fault model as they are relevant to the generation of test patterns for digital circuits. Its scope includes a) fault counting, b) fault classification, and c) fault coverage reporting across different automatic test pattern generation (ATPG) tools, for the single stuck-at fault model. Fault grading and simulation is limited to the Verilog gate level representation of a digital circuit. With this standard, it shall be incumbent on all ATPG tools (that comply with this standard) to report fault coverage in a uniform way. This can facilitate the generation of a uniform coverage (and hence a test quality) metric for large chips with different cores and modules, for which test patterns have been independently generated using an ATPG tool, or have been supplied externally and have been simulated using an ATPG tool to ascertain the fault coverage.<br />\n Digital circuits have various structural representations either in high level hardware description languages (HDLs) which can then be synthesized, or in netlist forms. Commercial tools today for Automatic Test Pattern Generation (ATPG) using algorithmic techniques operate on a structural netlist of the Design Under Test (DUT). The test quality signoff process mandatorily includes a minimal coverage requirement, to<br />\n 19 be obtained using these ATPG tool generated patterns on the DUT. This motivates the need for standard processes for (i) counting faults across different fault models, (ii) classifying these faults, and (iii) reporting the coverage, across different ATPG tools which are used to generate test patterns for these digital circuits. Such standard processes shall enable test qualification based on ATPG tool generated<br />\n 24 patterns and based upon fault coverage metrics in a uniform way and independent of the ATPG tool used. A uniform fault coverage and pattern count based metric can now be generated for large chips with complex functionality. Such metric are commonly used in today’s system-on-chips (SOCs) with a heterogeneous mix of modules thereein, often consisting of intellectual property (IP) cores (which are often sourced from design teams different from those designing the chips themselves), and test patterns for which are generated using different ATPG tools. This points to the need for such a standard. This standard shall help to build consensus amongst the chip designers, tool vendors and end customers of integrated circuits. The coverage metrics reported by the designers shall be consistent across all tools. Coverage requirements set by the customers can now also be uniformly targeted by the designers, independent of the ATPG tool used. The standard will also help in merging coverage reports from different tools when different IPs are integrated into an SOC. In the first version of this standard, only the classical stuck-at 0 and stuck-at 1 fault model shall be considered. The following are outside the scope of this document: a) Standards on ATPG algorithms, ATPG efficiency 1 (speed, memory), fault grading efficiency, fault models other than the stuck-at fault model, test vector compaction. b) Standards on how a gate-level netlist is created for a design. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Fault Accounting and Coverage Reporting(FACR) for Digital Modules" -notes: "Active" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#95073 …} #channels: Doctrine\ORM\PersistentCollection {#95067 …} #mainTaxon: App\Entity\Taxonomy\Taxon {#8838 …} #reviews: Doctrine\ORM\PersistentCollection {#95071 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#95069 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#95082 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#95081 …} -apiLastModifiedAt: DateTime @1754517600 {#95014 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#95017 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1517353200 {#95015 : 2018-01-31 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1804" -bookCollection: "" -pageCount: 29 -documents: Doctrine\ORM\PersistentCollection {#95079 …} -favorites: Doctrine\ORM\PersistentCollection {#95077 …} } ] |
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| Attributes | [ "showFullLabel" => false ] |
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| Component | App\Twig\Components\ProductState {#95303 +product: App\Entity\Product\Product {#95002 #id: 10557 #code: "IEEE00004604" #attributes: Doctrine\ORM\PersistentCollection {#95065 …} #variants: Doctrine\ORM\PersistentCollection {#95063 …} #options: Doctrine\ORM\PersistentCollection {#95059 …} #associations: Doctrine\ORM\PersistentCollection {#95061 …} #createdAt: DateTime @1751039135 {#95001 : 2025-06-27 17:45:35.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608190 {#95009 : 2025-08-08 01:09:50.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#95075 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#95296 #locale: "en_US" #translatable: App\Entity\Product\Product {#95002} #id: 37237 #name: "IEEE 1804:2017" #slug: "ieee-1804-2017-ieee00004604-242209" #description: """ New IEEE Standard - Active.<br />\n The standard formalizes aspects of fault models as they are relevant to the generation of test patterns for digital circuits. Its scope includes (i) fault counting, (ii) fault classification, and (iii) fault coverage reporting across different ATPG (automatic test pattern generation) tools, for the single stuck-at fault model. With this standard, it shall be incumbent on all ATPG tools (which comply with this standard) to report fault coverage in a uniform way. This will facilitate the generation of a uniform coverage (and hence a uniform test quality) metric for large chips (including systems-on-chips – SOCs) with different cores and modules, for which test patterns have been independently generated.<br />\n \t\t\t\t<br />\n This standard formalizes aspects of the stuck-at fault model as they are relevant to the generation of test patterns for digital circuits. Its scope includes a) fault counting, b) fault classification, and c) fault coverage reporting across different automatic test pattern generation (ATPG) tools, for the single stuck-at fault model. Fault grading and simulation is limited to the Verilog gate level representation of a digital circuit. With this standard, it shall be incumbent on all ATPG tools (that comply with this standard) to report fault coverage in a uniform way. This can facilitate the generation of a uniform coverage (and hence a test quality) metric for large chips with different cores and modules, for which test patterns have been independently generated using an ATPG tool, or have been supplied externally and have been simulated using an ATPG tool to ascertain the fault coverage.<br />\n Digital circuits have various structural representations either in high level hardware description languages (HDLs) which can then be synthesized, or in netlist forms. Commercial tools today for Automatic Test Pattern Generation (ATPG) using algorithmic techniques operate on a structural netlist of the Design Under Test (DUT). The test quality signoff process mandatorily includes a minimal coverage requirement, to<br />\n 19 be obtained using these ATPG tool generated patterns on the DUT. This motivates the need for standard processes for (i) counting faults across different fault models, (ii) classifying these faults, and (iii) reporting the coverage, across different ATPG tools which are used to generate test patterns for these digital circuits. Such standard processes shall enable test qualification based on ATPG tool generated<br />\n 24 patterns and based upon fault coverage metrics in a uniform way and independent of the ATPG tool used. A uniform fault coverage and pattern count based metric can now be generated for large chips with complex functionality. Such metric are commonly used in today’s system-on-chips (SOCs) with a heterogeneous mix of modules thereein, often consisting of intellectual property (IP) cores (which are often sourced from design teams different from those designing the chips themselves), and test patterns for which are generated using different ATPG tools. This points to the need for such a standard. This standard shall help to build consensus amongst the chip designers, tool vendors and end customers of integrated circuits. The coverage metrics reported by the designers shall be consistent across all tools. Coverage requirements set by the customers can now also be uniformly targeted by the designers, independent of the ATPG tool used. The standard will also help in merging coverage reports from different tools when different IPs are integrated into an SOC. In the first version of this standard, only the classical stuck-at 0 and stuck-at 1 fault model shall be considered. The following are outside the scope of this document: a) Standards on ATPG algorithms, ATPG efficiency 1 (speed, memory), fault grading efficiency, fault models other than the stuck-at fault model, test vector compaction. b) Standards on how a gate-level netlist is created for a design. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Fault Accounting and Coverage Reporting(FACR) for Digital Modules" -notes: "Active" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#95073 …} #channels: Doctrine\ORM\PersistentCollection {#95067 …} #mainTaxon: App\Entity\Taxonomy\Taxon {#8838 …} #reviews: Doctrine\ORM\PersistentCollection {#95071 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#95069 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#95082 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#95081 …} -apiLastModifiedAt: DateTime @1754517600 {#95014 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#95017 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1517353200 {#95015 : 2018-01-31 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1804" -bookCollection: "" -pageCount: 29 -documents: Doctrine\ORM\PersistentCollection {#95079 …} -favorites: Doctrine\ORM\PersistentCollection {#95077 …} } +appearance: "state-active" +labels: [ "Active" ] -stateAttributeCode: "state" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1831 …} } |
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| ProductMostRecent | App\Twig\Components\ProductMostRecent | 260.0 MiB | 0.66 ms | |
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| Input props | [ "product" => App\Entity\Product\Product {#95002 #id: 10557 #code: "IEEE00004604" #attributes: Doctrine\ORM\PersistentCollection {#95065 …} #variants: Doctrine\ORM\PersistentCollection {#95063 …} #options: Doctrine\ORM\PersistentCollection {#95059 …} #associations: Doctrine\ORM\PersistentCollection {#95061 …} #createdAt: DateTime @1751039135 {#95001 : 2025-06-27 17:45:35.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608190 {#95009 : 2025-08-08 01:09:50.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#95075 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#95296 #locale: "en_US" #translatable: App\Entity\Product\Product {#95002} #id: 37237 #name: "IEEE 1804:2017" #slug: "ieee-1804-2017-ieee00004604-242209" #description: """ New IEEE Standard - Active.<br />\n The standard formalizes aspects of fault models as they are relevant to the generation of test patterns for digital circuits. Its scope includes (i) fault counting, (ii) fault classification, and (iii) fault coverage reporting across different ATPG (automatic test pattern generation) tools, for the single stuck-at fault model. With this standard, it shall be incumbent on all ATPG tools (which comply with this standard) to report fault coverage in a uniform way. This will facilitate the generation of a uniform coverage (and hence a uniform test quality) metric for large chips (including systems-on-chips – SOCs) with different cores and modules, for which test patterns have been independently generated.<br />\n \t\t\t\t<br />\n This standard formalizes aspects of the stuck-at fault model as they are relevant to the generation of test patterns for digital circuits. Its scope includes a) fault counting, b) fault classification, and c) fault coverage reporting across different automatic test pattern generation (ATPG) tools, for the single stuck-at fault model. Fault grading and simulation is limited to the Verilog gate level representation of a digital circuit. With this standard, it shall be incumbent on all ATPG tools (that comply with this standard) to report fault coverage in a uniform way. This can facilitate the generation of a uniform coverage (and hence a test quality) metric for large chips with different cores and modules, for which test patterns have been independently generated using an ATPG tool, or have been supplied externally and have been simulated using an ATPG tool to ascertain the fault coverage.<br />\n Digital circuits have various structural representations either in high level hardware description languages (HDLs) which can then be synthesized, or in netlist forms. Commercial tools today for Automatic Test Pattern Generation (ATPG) using algorithmic techniques operate on a structural netlist of the Design Under Test (DUT). The test quality signoff process mandatorily includes a minimal coverage requirement, to<br />\n 19 be obtained using these ATPG tool generated patterns on the DUT. This motivates the need for standard processes for (i) counting faults across different fault models, (ii) classifying these faults, and (iii) reporting the coverage, across different ATPG tools which are used to generate test patterns for these digital circuits. Such standard processes shall enable test qualification based on ATPG tool generated<br />\n 24 patterns and based upon fault coverage metrics in a uniform way and independent of the ATPG tool used. A uniform fault coverage and pattern count based metric can now be generated for large chips with complex functionality. Such metric are commonly used in today’s system-on-chips (SOCs) with a heterogeneous mix of modules thereein, often consisting of intellectual property (IP) cores (which are often sourced from design teams different from those designing the chips themselves), and test patterns for which are generated using different ATPG tools. This points to the need for such a standard. This standard shall help to build consensus amongst the chip designers, tool vendors and end customers of integrated circuits. The coverage metrics reported by the designers shall be consistent across all tools. Coverage requirements set by the customers can now also be uniformly targeted by the designers, independent of the ATPG tool used. The standard will also help in merging coverage reports from different tools when different IPs are integrated into an SOC. In the first version of this standard, only the classical stuck-at 0 and stuck-at 1 fault model shall be considered. The following are outside the scope of this document: a) Standards on ATPG algorithms, ATPG efficiency 1 (speed, memory), fault grading efficiency, fault models other than the stuck-at fault model, test vector compaction. b) Standards on how a gate-level netlist is created for a design. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Fault Accounting and Coverage Reporting(FACR) for Digital Modules" -notes: "Active" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#95073 …} #channels: Doctrine\ORM\PersistentCollection {#95067 …} #mainTaxon: App\Entity\Taxonomy\Taxon {#8838 …} #reviews: Doctrine\ORM\PersistentCollection {#95071 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#95069 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#95082 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#95081 …} -apiLastModifiedAt: DateTime @1754517600 {#95014 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#95017 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1517353200 {#95015 : 2018-01-31 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1804" -bookCollection: "" -pageCount: 29 -documents: Doctrine\ORM\PersistentCollection {#95079 …} -favorites: Doctrine\ORM\PersistentCollection {#95077 …} } ] |
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The test quality signoff process mandatorily includes a minimal coverage requirement, to<br />\n 19 be obtained using these ATPG tool generated patterns on the DUT. This motivates the need for standard processes for (i) counting faults across different fault models, (ii) classifying these faults, and (iii) reporting the coverage, across different ATPG tools which are used to generate test patterns for these digital circuits. Such standard processes shall enable test qualification based on ATPG tool generated<br />\n 24 patterns and based upon fault coverage metrics in a uniform way and independent of the ATPG tool used. A uniform fault coverage and pattern count based metric can now be generated for large chips with complex functionality. Such metric are commonly used in today’s system-on-chips (SOCs) with a heterogeneous mix of modules thereein, often consisting of intellectual property (IP) cores (which are often sourced from design teams different from those designing the chips themselves), and test patterns for which are generated using different ATPG tools. This points to the need for such a standard. This standard shall help to build consensus amongst the chip designers, tool vendors and end customers of integrated circuits. The coverage metrics reported by the designers shall be consistent across all tools. Coverage requirements set by the customers can now also be uniformly targeted by the designers, independent of the ATPG tool used. The standard will also help in merging coverage reports from different tools when different IPs are integrated into an SOC. In the first version of this standard, only the classical stuck-at 0 and stuck-at 1 fault model shall be considered. The following are outside the scope of this document: a) Standards on ATPG algorithms, ATPG efficiency 1 (speed, memory), fault grading efficiency, fault models other than the stuck-at fault model, test vector compaction. b) Standards on how a gate-level netlist is created for a design. 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| ProductCard | App\Twig\Components\ProductCard | 260.0 MiB | 5.69 ms | |
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| Input props | [ "product" => App\Entity\Product\Product {#95027 #id: 10777 #code: "IEEE00004993" #attributes: Doctrine\ORM\PersistentCollection {#95047 …} #variants: Doctrine\ORM\PersistentCollection {#95049 …} #options: Doctrine\ORM\PersistentCollection {#95084 …} #associations: Doctrine\ORM\PersistentCollection {#95051 …} #createdAt: DateTime @1751039276 {#95057 : 2025-06-27 17:47:56.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1753969918 {#95056 : 2025-07-31 15:51:58.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#95022 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#95627 #locale: "en_US" #translatable: App\Entity\Product\Product {#95027} #id: 38117 #name: "IEEE C62.37.1:2012" #slug: "ieee-c62-37-1-2012-ieee00004993-242429" #description: """ Revision Standard - Active.<br />\n Applications information on fixed-voltage and gated-thyristor surge protective components (SPCs) is provided. Key device parameters and their sensitivities are explained. Several worked telecommunication circuit design examples are given.<br />\n \t\t\t\t<br />\n This application guide applies to Thyristor Surge Protective Components (SPCs)used in systems with voltages up to 1000 Vrms or 1200 Vdc. These components are designed to limit overvoltages and divert surge currents by limiting the voltage and switching to a low impedance state. Although telecommunication circuits are the main application of Thyristor SPCs, this guide will also provide useful information for other protection applications. This guide is intended to complement and be used in conjunction with the IEEE Standard Test Specification for Thyristor Diode Surge Protective Devices (IEEE C62.37).<br />\n This guide is intended to provide assistance in selecting the most appropriate type of thyristor surge protective component (SPC) for use in a surge protective device (SPD), equipment, or system application. The IEEE Standard Test Specification for Thyristor Diode Surge Protective Devices (ANSI/IEEE C62.37) defines thyristor SPC parameters and their measurement. This guide explains the basic functions, component structures, surge environment, comparative thyristor technologies, how parameters are interpreted and selected for example applications. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Guide for the Application of Thyristor Surge Protective Device Components" -notes: "Active" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#95033 …} #channels: Doctrine\ORM\PersistentCollection {#95045 …} #mainTaxon: App\Entity\Taxonomy\Taxon {#8838 …} #reviews: Doctrine\ORM\PersistentCollection {#95041 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#95043 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#95082 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#95031 …} -apiLastModifiedAt: DateTime @1743289200 {#95055 : 2025-03-30 00:00:00.0 Europe/Paris (+01:00) } -lastUpdatedAt: DateTime @1578006000 {#95054 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1366927200 {#95053 : 2013-04-26 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1366927200 {#95052 : 2013-04-26 00:00:00.0 Europe/Paris (+02:00) } -edition: null -coreDocument: "C62.37.1" -bookCollection: "" -pageCount: 78 -documents: Doctrine\ORM\PersistentCollection {#95028 …} -favorites: Doctrine\ORM\PersistentCollection {#95024 …} } "layout" => "vertical" "showPrice" => true "showStatusBadges" => true "imageFilter" => "product_listing_thumbnail" "additionalClasses" => "h-100 border-0" "hasStretchedLink" => true "backgroundColor" => "secondary-lighter" "hoverType" => "border-black" ] |
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| ProductState | App\Twig\Components\ProductState | 260.0 MiB | 0.15 ms | |
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| Input props | [ "product" => App\Entity\Product\Product {#95027 #id: 10777 #code: "IEEE00004993" #attributes: Doctrine\ORM\PersistentCollection {#95047 …} #variants: Doctrine\ORM\PersistentCollection {#95049 …} #options: Doctrine\ORM\PersistentCollection {#95084 …} #associations: Doctrine\ORM\PersistentCollection {#95051 …} #createdAt: DateTime @1751039276 {#95057 : 2025-06-27 17:47:56.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1753969918 {#95056 : 2025-07-31 15:51:58.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#95022 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#95627 #locale: "en_US" #translatable: App\Entity\Product\Product {#95027} #id: 38117 #name: "IEEE C62.37.1:2012" #slug: "ieee-c62-37-1-2012-ieee00004993-242429" #description: """ Revision Standard - Active.<br />\n Applications information on fixed-voltage and gated-thyristor surge protective components (SPCs) is provided. Key device parameters and their sensitivities are explained. Several worked telecommunication circuit design examples are given.<br />\n \t\t\t\t<br />\n This application guide applies to Thyristor Surge Protective Components (SPCs)used in systems with voltages up to 1000 Vrms or 1200 Vdc. These components are designed to limit overvoltages and divert surge currents by limiting the voltage and switching to a low impedance state. Although telecommunication circuits are the main application of Thyristor SPCs, this guide will also provide useful information for other protection applications. This guide is intended to complement and be used in conjunction with the IEEE Standard Test Specification for Thyristor Diode Surge Protective Devices (IEEE C62.37).<br />\n This guide is intended to provide assistance in selecting the most appropriate type of thyristor surge protective component (SPC) for use in a surge protective device (SPD), equipment, or system application. The IEEE Standard Test Specification for Thyristor Diode Surge Protective Devices (ANSI/IEEE C62.37) defines thyristor SPC parameters and their measurement. This guide explains the basic functions, component structures, surge environment, comparative thyristor technologies, how parameters are interpreted and selected for example applications. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Guide for the Application of Thyristor Surge Protective Device Components" -notes: "Active" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#95033 …} #channels: Doctrine\ORM\PersistentCollection {#95045 …} #mainTaxon: App\Entity\Taxonomy\Taxon {#8838 …} #reviews: Doctrine\ORM\PersistentCollection {#95041 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#95043 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#95082 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#95031 …} -apiLastModifiedAt: DateTime @1743289200 {#95055 : 2025-03-30 00:00:00.0 Europe/Paris (+01:00) } -lastUpdatedAt: DateTime @1578006000 {#95054 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1366927200 {#95053 : 2013-04-26 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1366927200 {#95052 : 2013-04-26 00:00:00.0 Europe/Paris (+02:00) } -edition: null -coreDocument: "C62.37.1" -bookCollection: "" -pageCount: 78 -documents: Doctrine\ORM\PersistentCollection {#95028 …} -favorites: Doctrine\ORM\PersistentCollection {#95024 …} } ] |
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| ProductCard | App\Twig\Components\ProductCard | 260.0 MiB | 5.95 ms | |
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| Input props | [ "product" => App\Entity\Product\Product {#95151 #id: 11954 #code: "IEEE00006827" #attributes: Doctrine\ORM\PersistentCollection {#95168 …} #variants: Doctrine\ORM\PersistentCollection {#95170 …} #options: Doctrine\ORM\PersistentCollection {#95174 …} #associations: Doctrine\ORM\PersistentCollection {#95172 …} #createdAt: DateTime @1751040099 {#95146 : 2025-06-27 18:01:39.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608621 {#95147 : 2025-08-08 01:17:01.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#95158 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#96338 #locale: "en_US" #translatable: App\Entity\Product\Product {#95151} #id: 42825 #name: "IEEE C62.59:2019" #slug: "ieee-c62-59-2019-ieee00006827-243606" #description: """ New IEEE Standard - Active.<br />\n Supersedes IEEE C62.35-2010 and IEEE C62.35-2010/Cor1-2018. The basic electrical parameters to be met by silicon PN junction voltage clamping components used for the protection of telecommunications equipment or lines from surges are defined in this standard. It is intended that this standard be used for the harmonization of existing or future specifications issued by PN diode surge protective component manufacturers, telecommunication equipment manufacturers, administrations, or network operators.<br />\n \t\t\t\t<br />\n This standard sets terms, test methods, test circuits, measurement procedures and preferred result values for diodes with one or more silicon PN-junctions used for surge voltage clamping in low-voltage systems.<br />\n The technology types covered are:<br />\n - Forward biased diodes<br />\n - Zener breakdown diodes<br />\n - Avalanche breakdown diodes<br />\n - Punch-through diodes<br />\n - Foldback diodes """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Test Methods and Preferred Values for Silicon PN-Junction Clamping Diodes" -notes: "Active" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#95160 …} #channels: Doctrine\ORM\PersistentCollection {#95166 …} #mainTaxon: App\Entity\Taxonomy\Taxon {#8838 …} #reviews: Doctrine\ORM\PersistentCollection {#95162 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#95164 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#95082 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#95152 …} -apiLastModifiedAt: DateTime @1754517600 {#95148 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1582066800 {#95149 : 2020-02-19 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1572476400 {#95150 : 2019-10-31 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "C62.59" -bookCollection: "" -pageCount: 41 -documents: Doctrine\ORM\PersistentCollection {#95154 …} -favorites: Doctrine\ORM\PersistentCollection {#95156 …} } "layout" => "vertical" "showPrice" => true "showStatusBadges" => true "imageFilter" => "product_listing_thumbnail" "additionalClasses" => "h-100 border-0" "hasStretchedLink" => true "backgroundColor" => "white" "hoverType" => "border-black" ] |
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| Attributes | [] |
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| Component | App\Twig\Components\ProductCard {#96318 +product: App\Entity\Product\Product {#95151 #id: 11954 #code: "IEEE00006827" #attributes: Doctrine\ORM\PersistentCollection {#95168 …} #variants: Doctrine\ORM\PersistentCollection {#95170 …} #options: Doctrine\ORM\PersistentCollection {#95174 …} #associations: Doctrine\ORM\PersistentCollection {#95172 …} #createdAt: DateTime @1751040099 {#95146 : 2025-06-27 18:01:39.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608621 {#95147 : 2025-08-08 01:17:01.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#95158 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#96338 #locale: "en_US" #translatable: App\Entity\Product\Product {#95151} #id: 42825 #name: "IEEE C62.59:2019" #slug: "ieee-c62-59-2019-ieee00006827-243606" #description: """ New IEEE Standard - Active.<br />\n Supersedes IEEE C62.35-2010 and IEEE C62.35-2010/Cor1-2018. The basic electrical parameters to be met by silicon PN junction voltage clamping components used for the protection of telecommunications equipment or lines from surges are defined in this standard. It is intended that this standard be used for the harmonization of existing or future specifications issued by PN diode surge protective component manufacturers, telecommunication equipment manufacturers, administrations, or network operators.<br />\n \t\t\t\t<br />\n This standard sets terms, test methods, test circuits, measurement procedures and preferred result values for diodes with one or more silicon PN-junctions used for surge voltage clamping in low-voltage systems.<br />\n The technology types covered are:<br />\n - Forward biased diodes<br />\n - Zener breakdown diodes<br />\n - Avalanche breakdown diodes<br />\n - Punch-through diodes<br />\n - Foldback diodes """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Test Methods and Preferred Values for Silicon PN-Junction Clamping Diodes" -notes: "Active" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#95160 …} #channels: Doctrine\ORM\PersistentCollection {#95166 …} #mainTaxon: App\Entity\Taxonomy\Taxon {#8838 …} #reviews: Doctrine\ORM\PersistentCollection {#95162 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#95164 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#95082 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#95152 …} -apiLastModifiedAt: DateTime @1754517600 {#95148 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1582066800 {#95149 : 2020-02-19 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1572476400 {#95150 : 2019-10-31 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "C62.59" -bookCollection: "" -pageCount: 41 -documents: Doctrine\ORM\PersistentCollection {#95154 …} -favorites: Doctrine\ORM\PersistentCollection {#95156 …} } +layout: "vertical" +showPrice: true +showStatusBadges: true +additionalClasses: "h-100 border-0" +linkLabel: "" +imageFilter: "product_listing_thumbnail" +hasStretchedLink: true +backgroundColor: "white" +hoverType: "border-black" } |
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| ProductState | App\Twig\Components\ProductState | 260.0 MiB | 0.15 ms | |
|---|---|---|---|---|
| Input props | [ "product" => App\Entity\Product\Product {#95151 #id: 11954 #code: "IEEE00006827" #attributes: Doctrine\ORM\PersistentCollection {#95168 …} #variants: Doctrine\ORM\PersistentCollection {#95170 …} #options: Doctrine\ORM\PersistentCollection {#95174 …} #associations: Doctrine\ORM\PersistentCollection {#95172 …} #createdAt: DateTime @1751040099 {#95146 : 2025-06-27 18:01:39.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608621 {#95147 : 2025-08-08 01:17:01.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#95158 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#96338 #locale: "en_US" #translatable: App\Entity\Product\Product {#95151} #id: 42825 #name: "IEEE C62.59:2019" #slug: "ieee-c62-59-2019-ieee00006827-243606" #description: """ New IEEE Standard - Active.<br />\n Supersedes IEEE C62.35-2010 and IEEE C62.35-2010/Cor1-2018. The basic electrical parameters to be met by silicon PN junction voltage clamping components used for the protection of telecommunications equipment or lines from surges are defined in this standard. It is intended that this standard be used for the harmonization of existing or future specifications issued by PN diode surge protective component manufacturers, telecommunication equipment manufacturers, administrations, or network operators.<br />\n \t\t\t\t<br />\n This standard sets terms, test methods, test circuits, measurement procedures and preferred result values for diodes with one or more silicon PN-junctions used for surge voltage clamping in low-voltage systems.<br />\n The technology types covered are:<br />\n - Forward biased diodes<br />\n - Zener breakdown diodes<br />\n - Avalanche breakdown diodes<br />\n - Punch-through diodes<br />\n - Foldback diodes """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Test Methods and Preferred Values for Silicon PN-Junction Clamping Diodes" -notes: "Active" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#95160 …} #channels: Doctrine\ORM\PersistentCollection {#95166 …} #mainTaxon: App\Entity\Taxonomy\Taxon {#8838 …} #reviews: Doctrine\ORM\PersistentCollection {#95162 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#95164 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#95082 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#95152 …} -apiLastModifiedAt: DateTime @1754517600 {#95148 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1582066800 {#95149 : 2020-02-19 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1572476400 {#95150 : 2019-10-31 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "C62.59" -bookCollection: "" -pageCount: 41 -documents: Doctrine\ORM\PersistentCollection {#95154 …} -favorites: Doctrine\ORM\PersistentCollection {#95156 …} } ] |
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| Attributes | [ "showFullLabel" => false ] |
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| Component | App\Twig\Components\ProductState {#96352 +product: App\Entity\Product\Product {#95151 #id: 11954 #code: "IEEE00006827" #attributes: Doctrine\ORM\PersistentCollection {#95168 …} #variants: Doctrine\ORM\PersistentCollection {#95170 …} #options: Doctrine\ORM\PersistentCollection {#95174 …} #associations: Doctrine\ORM\PersistentCollection {#95172 …} #createdAt: DateTime @1751040099 {#95146 : 2025-06-27 18:01:39.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608621 {#95147 : 2025-08-08 01:17:01.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#95158 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#96338 #locale: "en_US" #translatable: App\Entity\Product\Product {#95151} #id: 42825 #name: "IEEE C62.59:2019" #slug: "ieee-c62-59-2019-ieee00006827-243606" #description: """ New IEEE Standard - Active.<br />\n Supersedes IEEE C62.35-2010 and IEEE C62.35-2010/Cor1-2018. The basic electrical parameters to be met by silicon PN junction voltage clamping components used for the protection of telecommunications equipment or lines from surges are defined in this standard. It is intended that this standard be used for the harmonization of existing or future specifications issued by PN diode surge protective component manufacturers, telecommunication equipment manufacturers, administrations, or network operators.<br />\n \t\t\t\t<br />\n This standard sets terms, test methods, test circuits, measurement procedures and preferred result values for diodes with one or more silicon PN-junctions used for surge voltage clamping in low-voltage systems.<br />\n The technology types covered are:<br />\n - Forward biased diodes<br />\n - Zener breakdown diodes<br />\n - Avalanche breakdown diodes<br />\n - Punch-through diodes<br />\n - Foldback diodes """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Test Methods and Preferred Values for Silicon PN-Junction Clamping Diodes" -notes: "Active" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#95160 …} #channels: Doctrine\ORM\PersistentCollection {#95166 …} #mainTaxon: App\Entity\Taxonomy\Taxon {#8838 …} #reviews: Doctrine\ORM\PersistentCollection {#95162 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#95164 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#95082 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#95152 …} -apiLastModifiedAt: DateTime @1754517600 {#95148 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1582066800 {#95149 : 2020-02-19 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1572476400 {#95150 : 2019-10-31 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "C62.59" -bookCollection: "" -pageCount: 41 -documents: Doctrine\ORM\PersistentCollection {#95154 …} -favorites: Doctrine\ORM\PersistentCollection {#95156 …} } +appearance: "state-active" +labels: [ "Active" ] -stateAttributeCode: "state" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1831 …} } |
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| ProductMostRecent | App\Twig\Components\ProductMostRecent | 260.0 MiB | 0.63 ms | |
|---|---|---|---|---|
| Input props | [ "product" => App\Entity\Product\Product {#95151 #id: 11954 #code: "IEEE00006827" #attributes: Doctrine\ORM\PersistentCollection {#95168 …} #variants: Doctrine\ORM\PersistentCollection {#95170 …} #options: Doctrine\ORM\PersistentCollection {#95174 …} #associations: Doctrine\ORM\PersistentCollection {#95172 …} #createdAt: DateTime @1751040099 {#95146 : 2025-06-27 18:01:39.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608621 {#95147 : 2025-08-08 01:17:01.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#95158 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#96338 #locale: "en_US" #translatable: App\Entity\Product\Product {#95151} #id: 42825 #name: "IEEE C62.59:2019" #slug: "ieee-c62-59-2019-ieee00006827-243606" #description: """ New IEEE Standard - Active.<br />\n Supersedes IEEE C62.35-2010 and IEEE C62.35-2010/Cor1-2018. The basic electrical parameters to be met by silicon PN junction voltage clamping components used for the protection of telecommunications equipment or lines from surges are defined in this standard. It is intended that this standard be used for the harmonization of existing or future specifications issued by PN diode surge protective component manufacturers, telecommunication equipment manufacturers, administrations, or network operators.<br />\n \t\t\t\t<br />\n This standard sets terms, test methods, test circuits, measurement procedures and preferred result values for diodes with one or more silicon PN-junctions used for surge voltage clamping in low-voltage systems.<br />\n The technology types covered are:<br />\n - Forward biased diodes<br />\n - Zener breakdown diodes<br />\n - Avalanche breakdown diodes<br />\n - Punch-through diodes<br />\n - Foldback diodes """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Test Methods and Preferred Values for Silicon PN-Junction Clamping Diodes" -notes: "Active" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#95160 …} #channels: Doctrine\ORM\PersistentCollection {#95166 …} #mainTaxon: App\Entity\Taxonomy\Taxon {#8838 …} #reviews: Doctrine\ORM\PersistentCollection {#95162 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#95164 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#95082 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#95152 …} -apiLastModifiedAt: DateTime @1754517600 {#95148 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1582066800 {#95149 : 2020-02-19 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1572476400 {#95150 : 2019-10-31 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "C62.59" -bookCollection: "" -pageCount: 41 -documents: Doctrine\ORM\PersistentCollection {#95154 …} -favorites: Doctrine\ORM\PersistentCollection {#95156 …} } ] |
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| Attributes | [] |
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| Component | App\Twig\Components\ProductMostRecent {#96426 +product: App\Entity\Product\Product {#95151 #id: 11954 #code: "IEEE00006827" #attributes: Doctrine\ORM\PersistentCollection {#95168 …} #variants: Doctrine\ORM\PersistentCollection {#95170 …} #options: Doctrine\ORM\PersistentCollection {#95174 …} #associations: Doctrine\ORM\PersistentCollection {#95172 …} #createdAt: DateTime @1751040099 {#95146 : 2025-06-27 18:01:39.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608621 {#95147 : 2025-08-08 01:17:01.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#95158 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#96338 #locale: "en_US" #translatable: App\Entity\Product\Product {#95151} #id: 42825 #name: "IEEE C62.59:2019" #slug: "ieee-c62-59-2019-ieee00006827-243606" #description: """ New IEEE Standard - Active.<br />\n Supersedes IEEE C62.35-2010 and IEEE C62.35-2010/Cor1-2018. The basic electrical parameters to be met by silicon PN junction voltage clamping components used for the protection of telecommunications equipment or lines from surges are defined in this standard. It is intended that this standard be used for the harmonization of existing or future specifications issued by PN diode surge protective component manufacturers, telecommunication equipment manufacturers, administrations, or network operators.<br />\n \t\t\t\t<br />\n This standard sets terms, test methods, test circuits, measurement procedures and preferred result values for diodes with one or more silicon PN-junctions used for surge voltage clamping in low-voltage systems.<br />\n The technology types covered are:<br />\n - Forward biased diodes<br />\n - Zener breakdown diodes<br />\n - Avalanche breakdown diodes<br />\n - Punch-through diodes<br />\n - Foldback diodes """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Test Methods and Preferred Values for Silicon PN-Junction Clamping Diodes" -notes: "Active" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#95160 …} #channels: Doctrine\ORM\PersistentCollection {#95166 …} #mainTaxon: App\Entity\Taxonomy\Taxon {#8838 …} #reviews: Doctrine\ORM\PersistentCollection {#95162 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#95164 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#95082 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#95152 …} -apiLastModifiedAt: DateTime @1754517600 {#95148 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1582066800 {#95149 : 2020-02-19 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1572476400 {#95150 : 2019-10-31 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "C62.59" -bookCollection: "" -pageCount: 41 -documents: Doctrine\ORM\PersistentCollection {#95154 …} -favorites: Doctrine\ORM\PersistentCollection {#95156 …} } +label: "Most Recent" +icon: "check-xs" -mostRecentAttributeCode: "most_recent" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1831 …} } |
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