Symfony Profiler

Components

4 Twig Components

12 Render Count

18 ms Render Time

212.0 MiB Memory Usage

Components

Name	Metadata	Render Count	Render Time
ProductState	"App\Twig\Components\ProductState" components/ProductState.html.twig	5	2.73ms
ProductMostRecent	"App\Twig\Components\ProductMostRecent" components/ProductMostRecent.html.twig	5	3.91ms
ProductType	"App\Twig\Components\ProductType" components/ProductType.html.twig	1	0.48ms
ProductCard	"App\Twig\Components\ProductCard" components/ProductCard.html.twig	1	11.53ms

Render calls

ProductState	App\Twig\Components\ProductState	212.0 MiB	1.94 ms
Input props	["product" => App\Entity\Product\Product {#7311 #id: 12374 #code: "IEEE00007567" #attributes: Doctrine\ORM\PersistentCollection {#7701 …} #variants: Doctrine\ORM\PersistentCollection {#7744 …} #options: Doctrine\ORM\PersistentCollection {#7916 …} #associations: Doctrine\ORM\PersistentCollection {#7900 …} #createdAt: DateTime @1751040390 {#7274 date: 2025-06-27 18:06:30.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608642 {#7322 date: 2025-08-08 01:17:22.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7922 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7921 #locale: "en_US" #translatable: App\Entity\Product\Product {#7311} #id: 44505 #name: "IEEE 1800.2:2020 Redline" #slug: "ieee-1800-2-2020-redline-ieee00007567-244027" #description: """ Revision Standard - Active.<br />\n The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.<br />\n (The PDF of this standard is available at no cost compliments of the IEEE GET program https://ieeexplore.ieee.org/browse/standards/get-program/page/series?id=80)<br />\n \t\t\t\t<br />\n This standard establishes the Universal Verification Methodology (UVM), a set of application programming interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog, IEEE Std 1800(TM).<br />\n Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting intellectual property (IP) for each new project or electronic design automation (EDA) tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Universal Verification Methodology Language Reference Manual" -notes: "Active" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …} #channels: Doctrine\ORM\PersistentCollection {#7628 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#7613 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7645 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1604012400 {#7292 date: 2020-10-30 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1600034400 {#7318 date: 2020-09-14 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1600034400 {#7316 date: 2020-09-14 00:00:00.0 Europe/Paris (+02:00) } -edition: null -coreDocument: "1800.2" -bookCollection: "" -pageCount: 752 -documents: Doctrine\ORM\PersistentCollection {#7465 …} -favorites: Doctrine\ORM\PersistentCollection {#7500 …} } "showFullLabel" => "true"]
Attributes	[`"showFullLabel" => "true"`]
Component	App\Twig\Components\ProductState {#92957+product: App\Entity\Product\Product {#7311 #id: 12374 #code: "IEEE00007567" #attributes: Doctrine\ORM\PersistentCollection {#7701 …} #variants: Doctrine\ORM\PersistentCollection {#7744 …} #options: Doctrine\ORM\PersistentCollection {#7916 …} #associations: Doctrine\ORM\PersistentCollection {#7900 …} #createdAt: DateTime @1751040390 {#7274 date: 2025-06-27 18:06:30.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608642 {#7322 date: 2025-08-08 01:17:22.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7922 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7921 #locale: "en_US" #translatable: App\Entity\Product\Product {#7311} #id: 44505 #name: "IEEE 1800.2:2020 Redline" #slug: "ieee-1800-2-2020-redline-ieee00007567-244027" #description: """ Revision Standard - Active.<br />\n The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.<br />\n (The PDF of this standard is available at no cost compliments of the IEEE GET program https://ieeexplore.ieee.org/browse/standards/get-program/page/series?id=80)<br />\n \t\t\t\t<br />\n This standard establishes the Universal Verification Methodology (UVM), a set of application programming interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog, IEEE Std 1800(TM).<br />\n Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting intellectual property (IP) for each new project or electronic design automation (EDA) tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Universal Verification Methodology Language Reference Manual" -notes: "Active" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …} #channels: Doctrine\ORM\PersistentCollection {#7628 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#7613 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7645 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1604012400 {#7292 date: 2020-10-30 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1600034400 {#7318 date: 2020-09-14 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1600034400 {#7316 date: 2020-09-14 00:00:00.0 Europe/Paris (+02:00) } -edition: null -coreDocument: "1800.2" -bookCollection: "" -pageCount: 752 -documents: Doctrine\ORM\PersistentCollection {#7465 …} -favorites: Doctrine\ORM\PersistentCollection {#7500 …} } +appearance: "state-active" +labels: [ "Active" ] -stateAttributeCode: "state" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}}

ProductState

App\Twig\Components\ProductState

212.0 MiB

1.94 ms

Input props

[
  "product" => App\Entity\Product\Product {#7311
    #id: 12374
    #code: "IEEE00007567"
    #attributes: Doctrine\ORM\PersistentCollection {#7701 …}
    #variants: Doctrine\ORM\PersistentCollection {#7744 …}
    #options: Doctrine\ORM\PersistentCollection {#7916 …}
    #associations: Doctrine\ORM\PersistentCollection {#7900 …}
    #createdAt: DateTime @1751040390 {#7274
      date: 2025-06-27 18:06:30.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754608642 {#7322
      date: 2025-08-08 01:17:22.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7922 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7921
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7311}
        #id: 44505
        #name: "IEEE 1800.2:2020  Redline"
        #slug: "ieee-1800-2-2020-redline-ieee00007567-244027"
        #description: """
          Revision Standard - Active.<br />\n
          The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.<br />\n
          (The PDF of this standard is available at no cost compliments of the IEEE GET program https://ieeexplore.ieee.org/browse/standards/get-program/page/series?id=80)<br />\n
          \t\t\t\t<br />\n
          This standard establishes the Universal Verification Methodology (UVM), a set of application programming interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog, IEEE Std 1800(TM).<br />\n
          Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting intellectual property (IP) for each new project or electronic design automation (EDA) tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Universal Verification Methodology Language Reference Manual"
        -notes: "Active"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …}
    #channels: Doctrine\ORM\PersistentCollection {#7628 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7613 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7645 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1604012400 {#7292
      date: 2020-10-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1600034400 {#7318
      date: 2020-09-14 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: DateTime @1600034400 {#7316
      date: 2020-09-14 00:00:00.0 Europe/Paris (+02:00)
    }
    -edition: null
    -coreDocument: "1800.2"
    -bookCollection: ""
    -pageCount: 752
    -documents: Doctrine\ORM\PersistentCollection {#7465 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7500 …}
  }
  "showFullLabel" => "true"
]

Attributes

[
  "showFullLabel" => "true"
]

Component

App\Twig\Components\ProductState {#92957
  +product: App\Entity\Product\Product {#7311
    #id: 12374
    #code: "IEEE00007567"
    #attributes: Doctrine\ORM\PersistentCollection {#7701 …}
    #variants: Doctrine\ORM\PersistentCollection {#7744 …}
    #options: Doctrine\ORM\PersistentCollection {#7916 …}
    #associations: Doctrine\ORM\PersistentCollection {#7900 …}
    #createdAt: DateTime @1751040390 {#7274
      date: 2025-06-27 18:06:30.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754608642 {#7322
      date: 2025-08-08 01:17:22.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7922 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7921
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7311}
        #id: 44505
        #name: "IEEE 1800.2:2020  Redline"
        #slug: "ieee-1800-2-2020-redline-ieee00007567-244027"
        #description: """
          Revision Standard - Active.<br />\n
          The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.<br />\n
          (The PDF of this standard is available at no cost compliments of the IEEE GET program https://ieeexplore.ieee.org/browse/standards/get-program/page/series?id=80)<br />\n
          \t\t\t\t<br />\n
          This standard establishes the Universal Verification Methodology (UVM), a set of application programming interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog, IEEE Std 1800(TM).<br />\n
          Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting intellectual property (IP) for each new project or electronic design automation (EDA) tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Universal Verification Methodology Language Reference Manual"
        -notes: "Active"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …}
    #channels: Doctrine\ORM\PersistentCollection {#7628 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7613 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7645 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1604012400 {#7292
      date: 2020-10-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1600034400 {#7318
      date: 2020-09-14 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: DateTime @1600034400 {#7316
      date: 2020-09-14 00:00:00.0 Europe/Paris (+02:00)
    }
    -edition: null
    -coreDocument: "1800.2"
    -bookCollection: ""
    -pageCount: 752
    -documents: Doctrine\ORM\PersistentCollection {#7465 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7500 …}
  }
  +appearance: "state-active"
  +labels: [
    "Active"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

ProductType	App\Twig\Components\ProductType	212.0 MiB	0.48 ms
Input props	["product" => App\Entity\Product\Product {#7311 #id: 12374 #code: "IEEE00007567" #attributes: Doctrine\ORM\PersistentCollection {#7701 …} #variants: Doctrine\ORM\PersistentCollection {#7744 …} #options: Doctrine\ORM\PersistentCollection {#7916 …} #associations: Doctrine\ORM\PersistentCollection {#7900 …} #createdAt: DateTime @1751040390 {#7274 date: 2025-06-27 18:06:30.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608642 {#7322 date: 2025-08-08 01:17:22.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7922 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7921 #locale: "en_US" #translatable: App\Entity\Product\Product {#7311} #id: 44505 #name: "IEEE 1800.2:2020 Redline" #slug: "ieee-1800-2-2020-redline-ieee00007567-244027" #description: """ Revision Standard - Active.<br />\n The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.<br />\n (The PDF of this standard is available at no cost compliments of the IEEE GET program https://ieeexplore.ieee.org/browse/standards/get-program/page/series?id=80)<br />\n \t\t\t\t<br />\n This standard establishes the Universal Verification Methodology (UVM), a set of application programming interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog, IEEE Std 1800(TM).<br />\n Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting intellectual property (IP) for each new project or electronic design automation (EDA) tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Universal Verification Methodology Language Reference Manual" -notes: "Active" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …} #channels: Doctrine\ORM\PersistentCollection {#7628 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#7613 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7645 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1604012400 {#7292 date: 2020-10-30 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1600034400 {#7318 date: 2020-09-14 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1600034400 {#7316 date: 2020-09-14 00:00:00.0 Europe/Paris (+02:00) } -edition: null -coreDocument: "1800.2" -bookCollection: "" -pageCount: 752 -documents: Doctrine\ORM\PersistentCollection {#7465 …} -favorites: Doctrine\ORM\PersistentCollection {#7500 …} }]
Attributes	[]
Component	App\Twig\Components\ProductType {#93128+product: App\Entity\Product\Product {#7311 #id: 12374 #code: "IEEE00007567" #attributes: Doctrine\ORM\PersistentCollection {#7701 …} #variants: Doctrine\ORM\PersistentCollection {#7744 …} #options: Doctrine\ORM\PersistentCollection {#7916 …} #associations: Doctrine\ORM\PersistentCollection {#7900 …} #createdAt: DateTime @1751040390 {#7274 date: 2025-06-27 18:06:30.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608642 {#7322 date: 2025-08-08 01:17:22.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7922 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7921 #locale: "en_US" #translatable: App\Entity\Product\Product {#7311} #id: 44505 #name: "IEEE 1800.2:2020 Redline" #slug: "ieee-1800-2-2020-redline-ieee00007567-244027" #description: """ Revision Standard - Active.<br />\n The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.<br />\n (The PDF of this standard is available at no cost compliments of the IEEE GET program https://ieeexplore.ieee.org/browse/standards/get-program/page/series?id=80)<br />\n \t\t\t\t<br />\n This standard establishes the Universal Verification Methodology (UVM), a set of application programming interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog, IEEE Std 1800(TM).<br />\n Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting intellectual property (IP) for each new project or electronic design automation (EDA) tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Universal Verification Methodology Language Reference Manual" -notes: "Active" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …} #channels: Doctrine\ORM\PersistentCollection {#7628 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#7613 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7645 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1604012400 {#7292 date: 2020-10-30 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1600034400 {#7318 date: 2020-09-14 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1600034400 {#7316 date: 2020-09-14 00:00:00.0 Europe/Paris (+02:00) } -edition: null -coreDocument: "1800.2" -bookCollection: "" -pageCount: 752 -documents: Doctrine\ORM\PersistentCollection {#7465 …} -favorites: Doctrine\ORM\PersistentCollection {#7500 …} } +label: "Standard" -typeAttributeCode: "type" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}}

ProductType

App\Twig\Components\ProductType

212.0 MiB

0.48 ms

Input props

[
  "product" => App\Entity\Product\Product {#7311
    #id: 12374
    #code: "IEEE00007567"
    #attributes: Doctrine\ORM\PersistentCollection {#7701 …}
    #variants: Doctrine\ORM\PersistentCollection {#7744 …}
    #options: Doctrine\ORM\PersistentCollection {#7916 …}
    #associations: Doctrine\ORM\PersistentCollection {#7900 …}
    #createdAt: DateTime @1751040390 {#7274
      date: 2025-06-27 18:06:30.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754608642 {#7322
      date: 2025-08-08 01:17:22.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7922 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7921
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7311}
        #id: 44505
        #name: "IEEE 1800.2:2020  Redline"
        #slug: "ieee-1800-2-2020-redline-ieee00007567-244027"
        #description: """
          Revision Standard - Active.<br />\n
          The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.<br />\n
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ProductState	App\Twig\Components\ProductState	212.0 MiB	0.21 ms
Input props	["product" => App\Entity\Product\Product {#100213 #id: 11378 #code: "IEEE00006021" #attributes: Doctrine\ORM\PersistentCollection {#100194 …} #variants: Doctrine\ORM\PersistentCollection {#100191 …} #options: Doctrine\ORM\PersistentCollection {#100187 …} #associations: Doctrine\ORM\PersistentCollection {#100189 …} #createdAt: DateTime @1751039666 {#100220 date: 2025-06-27 17:54:26.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608190 {#100193 date: 2025-08-08 01:09:50.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#100204 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#100232 #locale: "en_US" #translatable: App\Entity\Product\Product {#100213} #id: 40521 #name: "IEEE 1800.2:2017" #slug: "ieee-1800-2-2017-ieee00006021-243030" #description: """ New IEEE Standard - Superseded.<br />\n The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.<br />\n \t\t\t\t<br />\n This standard establishes the Universal Verification Methodology (UVM), a set of Application Programming Interfaces (APIs) that define a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE 1800 SystemVerilog standard.<br />\n Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically-dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting Intellectual Property (IP) for each new project or electronic design automation tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Universal Verification Methodology Language Reference Manual" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#100202 …} #channels: Doctrine\ORM\PersistentCollection {#100196 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#100200 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#100198 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#100211 …} -apiLastModifiedAt: DateTime @1754517600 {#100180 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1604012400 {#100219 date: 2020-10-30 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1495749600 {#100218 date: 2017-05-26 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1495749600 {#100212 date: 2017-05-26 00:00:00.0 Europe/Paris (+02:00) } -edition: null -coreDocument: "1800.2" -bookCollection: "" -pageCount: 472 -documents: Doctrine\ORM\PersistentCollection {#100209 …} -favorites: Doctrine\ORM\PersistentCollection {#100207 …} } "showFullLabel" => "true"]
Attributes	[`"showFullLabel" => "true"`]
Component	App\Twig\Components\ProductState {#100271+product: App\Entity\Product\Product {#100213 #id: 11378 #code: "IEEE00006021" #attributes: Doctrine\ORM\PersistentCollection {#100194 …} #variants: Doctrine\ORM\PersistentCollection {#100191 …} #options: Doctrine\ORM\PersistentCollection {#100187 …} #associations: Doctrine\ORM\PersistentCollection {#100189 …} #createdAt: DateTime @1751039666 {#100220 date: 2025-06-27 17:54:26.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608190 {#100193 date: 2025-08-08 01:09:50.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#100204 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#100232 #locale: "en_US" #translatable: App\Entity\Product\Product {#100213} #id: 40521 #name: "IEEE 1800.2:2017" #slug: "ieee-1800-2-2017-ieee00006021-243030" #description: """ New IEEE Standard - Superseded.<br />\n The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.<br />\n \t\t\t\t<br />\n This standard establishes the Universal Verification Methodology (UVM), a set of Application Programming Interfaces (APIs) that define a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE 1800 SystemVerilog standard.<br />\n Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically-dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting Intellectual Property (IP) for each new project or electronic design automation tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Universal Verification Methodology Language Reference Manual" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#100202 …} #channels: Doctrine\ORM\PersistentCollection {#100196 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#100200 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#100198 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#100211 …} -apiLastModifiedAt: DateTime @1754517600 {#100180 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1604012400 {#100219 date: 2020-10-30 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1495749600 {#100218 date: 2017-05-26 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1495749600 {#100212 date: 2017-05-26 00:00:00.0 Europe/Paris (+02:00) } -edition: null -coreDocument: "1800.2" -bookCollection: "" -pageCount: 472 -documents: Doctrine\ORM\PersistentCollection {#100209 …} -favorites: Doctrine\ORM\PersistentCollection {#100207 …} } +appearance: "state-suspended" +labels: [ "Superseded" ] -stateAttributeCode: "state" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}}

ProductState

App\Twig\Components\ProductState

212.0 MiB

0.21 ms

Input props

[
  "product" => App\Entity\Product\Product {#100213
    #id: 11378
    #code: "IEEE00006021"
    #attributes: Doctrine\ORM\PersistentCollection {#100194 …}
    #variants: Doctrine\ORM\PersistentCollection {#100191 …}
    #options: Doctrine\ORM\PersistentCollection {#100187 …}
    #associations: Doctrine\ORM\PersistentCollection {#100189 …}
    #createdAt: DateTime @1751039666 {#100220
      date: 2025-06-27 17:54:26.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754608190 {#100193
      date: 2025-08-08 01:09:50.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#100204 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#100232
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#100213}
        #id: 40521
        #name: "IEEE 1800.2:2017"
        #slug: "ieee-1800-2-2017-ieee00006021-243030"
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          New IEEE Standard - Superseded.<br />\n
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          \t\t\t\t<br />\n
          This standard establishes the Universal Verification Methodology (UVM), a set of Application Programming Interfaces (APIs) that define a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE 1800 SystemVerilog standard.<br />\n
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          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Universal Verification Methodology Language Reference Manual"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#100202 …}
    #channels: Doctrine\ORM\PersistentCollection {#100196 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …}
    #reviews: Doctrine\ORM\PersistentCollection {#100200 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#100198 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
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    -apiLastModifiedAt: DateTime @1754517600 {#100180
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    -lastUpdatedAt: DateTime @1604012400 {#100219
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    }
    -edition: null
    -coreDocument: "1800.2"
    -bookCollection: ""
    -pageCount: 472
    -documents: Doctrine\ORM\PersistentCollection {#100209 …}
    -favorites: Doctrine\ORM\PersistentCollection {#100207 …}
  }
  "showFullLabel" => "true"
]

Attributes

[
  "showFullLabel" => "true"
]

Component

App\Twig\Components\ProductState {#100271
  +product: App\Entity\Product\Product {#100213
    #id: 11378
    #code: "IEEE00006021"
    #attributes: Doctrine\ORM\PersistentCollection {#100194 …}
    #variants: Doctrine\ORM\PersistentCollection {#100191 …}
    #options: Doctrine\ORM\PersistentCollection {#100187 …}
    #associations: Doctrine\ORM\PersistentCollection {#100189 …}
    #createdAt: DateTime @1751039666 {#100220
      date: 2025-06-27 17:54:26.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754608190 {#100193
      date: 2025-08-08 01:09:50.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#100204 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#100232
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#100213}
        #id: 40521
        #name: "IEEE 1800.2:2017"
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        #description: """
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          \t\t\t\t<br />\n
          This standard establishes the Universal Verification Methodology (UVM), a set of Application Programming Interfaces (APIs) that define a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE 1800 SystemVerilog standard.<br />\n
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        #metaKeywords: null
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        #shortDescription: "IEEE Standard for Universal Verification Methodology Language Reference Manual"
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    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#100202 …}
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    #reviews: Doctrine\ORM\PersistentCollection {#100200 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#100198 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
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    -apiLastModifiedAt: DateTime @1754517600 {#100180
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    -lastUpdatedAt: DateTime @1604012400 {#100219
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    -edition: null
    -coreDocument: "1800.2"
    -bookCollection: ""
    -pageCount: 472
    -documents: Doctrine\ORM\PersistentCollection {#100209 …}
    -favorites: Doctrine\ORM\PersistentCollection {#100207 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

ProductMostRecent	App\Twig\Components\ProductMostRecent	212.0 MiB	0.76 ms
Input props	["product" => App\Entity\Product\Product {#100213 #id: 11378 #code: "IEEE00006021" #attributes: Doctrine\ORM\PersistentCollection {#100194 …} #variants: Doctrine\ORM\PersistentCollection {#100191 …} #options: Doctrine\ORM\PersistentCollection {#100187 …} #associations: Doctrine\ORM\PersistentCollection {#100189 …} #createdAt: DateTime @1751039666 {#100220 date: 2025-06-27 17:54:26.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608190 {#100193 date: 2025-08-08 01:09:50.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#100204 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#100232 #locale: "en_US" #translatable: App\Entity\Product\Product {#100213} #id: 40521 #name: "IEEE 1800.2:2017" #slug: "ieee-1800-2-2017-ieee00006021-243030" #description: """ New IEEE Standard - Superseded.<br />\n The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.<br />\n \t\t\t\t<br />\n This standard establishes the Universal Verification Methodology (UVM), a set of Application Programming Interfaces (APIs) that define a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE 1800 SystemVerilog standard.<br />\n Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically-dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting Intellectual Property (IP) for each new project or electronic design automation tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Universal Verification Methodology Language Reference Manual" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#100202 …} #channels: Doctrine\ORM\PersistentCollection {#100196 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#100200 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#100198 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#100211 …} -apiLastModifiedAt: DateTime @1754517600 {#100180 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1604012400 {#100219 date: 2020-10-30 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1495749600 {#100218 date: 2017-05-26 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1495749600 {#100212 date: 2017-05-26 00:00:00.0 Europe/Paris (+02:00) } -edition: null -coreDocument: "1800.2" -bookCollection: "" -pageCount: 472 -documents: Doctrine\ORM\PersistentCollection {#100209 …} -favorites: Doctrine\ORM\PersistentCollection {#100207 …} }]
Attributes	[]
Component	App\Twig\Components\ProductMostRecent {#100338+product: App\Entity\Product\Product {#100213 #id: 11378 #code: "IEEE00006021" #attributes: Doctrine\ORM\PersistentCollection {#100194 …} #variants: Doctrine\ORM\PersistentCollection {#100191 …} #options: Doctrine\ORM\PersistentCollection {#100187 …} #associations: Doctrine\ORM\PersistentCollection {#100189 …} #createdAt: DateTime @1751039666 {#100220 date: 2025-06-27 17:54:26.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608190 {#100193 date: 2025-08-08 01:09:50.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#100204 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#100232 #locale: "en_US" #translatable: App\Entity\Product\Product {#100213} #id: 40521 #name: "IEEE 1800.2:2017" #slug: "ieee-1800-2-2017-ieee00006021-243030" #description: """ New IEEE Standard - Superseded.<br />\n The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.<br />\n \t\t\t\t<br />\n This standard establishes the Universal Verification Methodology (UVM), a set of Application Programming Interfaces (APIs) that define a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE 1800 SystemVerilog standard.<br />\n Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically-dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting Intellectual Property (IP) for each new project or electronic design automation tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Universal Verification Methodology Language Reference Manual" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#100202 …} #channels: Doctrine\ORM\PersistentCollection {#100196 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#100200 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#100198 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#100211 …} -apiLastModifiedAt: DateTime @1754517600 {#100180 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1604012400 {#100219 date: 2020-10-30 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1495749600 {#100218 date: 2017-05-26 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1495749600 {#100212 date: 2017-05-26 00:00:00.0 Europe/Paris (+02:00) } -edition: null -coreDocument: "1800.2" -bookCollection: "" -pageCount: 472 -documents: Doctrine\ORM\PersistentCollection {#100209 …} -favorites: Doctrine\ORM\PersistentCollection {#100207 …} } +label: "Historical" +icon: "historical" -mostRecentAttributeCode: "most_recent" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}}

ProductMostRecent

App\Twig\Components\ProductMostRecent

212.0 MiB

0.76 ms

Input props

[
  "product" => App\Entity\Product\Product {#100213
    #id: 11378
    #code: "IEEE00006021"
    #attributes: Doctrine\ORM\PersistentCollection {#100194 …}
    #variants: Doctrine\ORM\PersistentCollection {#100191 …}
    #options: Doctrine\ORM\PersistentCollection {#100187 …}
    #associations: Doctrine\ORM\PersistentCollection {#100189 …}
    #createdAt: DateTime @1751039666 {#100220
      date: 2025-06-27 17:54:26.0 Europe/Paris (+02:00)
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    #updatedAt: DateTime @1754608190 {#100193
      date: 2025-08-08 01:09:50.0 Europe/Paris (+02:00)
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    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#100204 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#100232
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#100213}
        #id: 40521
        #name: "IEEE 1800.2:2017"
        #slug: "ieee-1800-2-2017-ieee00006021-243030"
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        #metaKeywords: null
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Input props	["product" => App\Entity\Product\Product {#7311 #id: 12374 #code: "IEEE00007567" #attributes: Doctrine\ORM\PersistentCollection {#7701 …} #variants: Doctrine\ORM\PersistentCollection {#7744 …} #options: Doctrine\ORM\PersistentCollection {#7916 …} #associations: Doctrine\ORM\PersistentCollection {#7900 …} #createdAt: DateTime @1751040390 {#7274 date: 2025-06-27 18:06:30.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608642 {#7322 date: 2025-08-08 01:17:22.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7922 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7921 #locale: "en_US" #translatable: App\Entity\Product\Product {#7311} #id: 44505 #name: "IEEE 1800.2:2020 Redline" #slug: "ieee-1800-2-2020-redline-ieee00007567-244027" #description: """ Revision Standard - Active.<br />\n The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.<br />\n (The PDF of this standard is available at no cost compliments of the IEEE GET program https://ieeexplore.ieee.org/browse/standards/get-program/page/series?id=80)<br />\n \t\t\t\t<br />\n This standard establishes the Universal Verification Methodology (UVM), a set of application programming interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog, IEEE Std 1800(TM).<br />\n Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting intellectual property (IP) for each new project or electronic design automation (EDA) tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Universal Verification Methodology Language Reference Manual" -notes: "Active" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …} #channels: Doctrine\ORM\PersistentCollection {#7628 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#7613 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7645 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1604012400 {#7292 date: 2020-10-30 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1600034400 {#7318 date: 2020-09-14 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1600034400 {#7316 date: 2020-09-14 00:00:00.0 Europe/Paris (+02:00) } -edition: null -coreDocument: "1800.2" -bookCollection: "" -pageCount: 752 -documents: Doctrine\ORM\PersistentCollection {#7465 …} -favorites: Doctrine\ORM\PersistentCollection {#7500 …} }]
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App\Twig\Components\ProductMostRecent

212.0 MiB

0.73 ms

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App\Twig\Components\ProductMostRecent {#106970
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        #translatable: App\Entity\Product\Product {#7311}
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ProductState	App\Twig\Components\ProductState	212.0 MiB	0.18 ms
Input props	["product" => App\Entity\Product\Product {#100213 #id: 11378 #code: "IEEE00006021" #attributes: Doctrine\ORM\PersistentCollection {#100194 …} #variants: Doctrine\ORM\PersistentCollection {#100191 …} #options: Doctrine\ORM\PersistentCollection {#100187 …} #associations: Doctrine\ORM\PersistentCollection {#100189 …} #createdAt: DateTime @1751039666 {#100220 date: 2025-06-27 17:54:26.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608190 {#100193 date: 2025-08-08 01:09:50.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#100204 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#100232 #locale: "en_US" #translatable: App\Entity\Product\Product {#100213} #id: 40521 #name: "IEEE 1800.2:2017" #slug: "ieee-1800-2-2017-ieee00006021-243030" #description: """ New IEEE Standard - Superseded.<br />\n The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.<br />\n \t\t\t\t<br />\n This standard establishes the Universal Verification Methodology (UVM), a set of Application Programming Interfaces (APIs) that define a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE 1800 SystemVerilog standard.<br />\n Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically-dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting Intellectual Property (IP) for each new project or electronic design automation tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Universal Verification Methodology Language Reference Manual" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#100202 …} #channels: Doctrine\ORM\PersistentCollection {#100196 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#100200 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#100198 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#100211 …} -apiLastModifiedAt: DateTime @1754517600 {#100180 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1604012400 {#100219 date: 2020-10-30 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1495749600 {#100218 date: 2017-05-26 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1495749600 {#100212 date: 2017-05-26 00:00:00.0 Europe/Paris (+02:00) } -edition: null -coreDocument: "1800.2" -bookCollection: "" -pageCount: 472 -documents: Doctrine\ORM\PersistentCollection {#100209 …} -favorites: Doctrine\ORM\PersistentCollection {#100207 …} } "showFullLabel" => "true"]
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Component	App\Twig\Components\ProductState {#107035+product: App\Entity\Product\Product {#100213 #id: 11378 #code: "IEEE00006021" #attributes: Doctrine\ORM\PersistentCollection {#100194 …} #variants: Doctrine\ORM\PersistentCollection {#100191 …} #options: Doctrine\ORM\PersistentCollection {#100187 …} #associations: Doctrine\ORM\PersistentCollection {#100189 …} #createdAt: DateTime @1751039666 {#100220 date: 2025-06-27 17:54:26.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608190 {#100193 date: 2025-08-08 01:09:50.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#100204 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#100232 #locale: "en_US" #translatable: App\Entity\Product\Product {#100213} #id: 40521 #name: "IEEE 1800.2:2017" #slug: "ieee-1800-2-2017-ieee00006021-243030" #description: """ New IEEE Standard - Superseded.<br />\n The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.<br />\n \t\t\t\t<br />\n This standard establishes the Universal Verification Methodology (UVM), a set of Application Programming Interfaces (APIs) that define a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE 1800 SystemVerilog standard.<br />\n Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically-dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting Intellectual Property (IP) for each new project or electronic design automation tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Universal Verification Methodology Language Reference Manual" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#100202 …} #channels: Doctrine\ORM\PersistentCollection {#100196 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#100200 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#100198 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#100211 …} -apiLastModifiedAt: DateTime @1754517600 {#100180 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1604012400 {#100219 date: 2020-10-30 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1495749600 {#100218 date: 2017-05-26 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1495749600 {#100212 date: 2017-05-26 00:00:00.0 Europe/Paris (+02:00) } -edition: null -coreDocument: "1800.2" -bookCollection: "" -pageCount: 472 -documents: Doctrine\ORM\PersistentCollection {#100209 …} -favorites: Doctrine\ORM\PersistentCollection {#100207 …} } +appearance: "state-suspended" +labels: [ "Superseded" ] -stateAttributeCode: "state" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}}

ProductState

App\Twig\Components\ProductState

212.0 MiB

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[
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App\Twig\Components\ProductState {#107035
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ProductMostRecent	App\Twig\Components\ProductMostRecent	212.0 MiB	0.61 ms
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App\Twig\Components\ProductMostRecent

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Component

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ProductCard	App\Twig\Components\ProductCard	212.0 MiB	11.53 ms
Input props	["product" => App\Entity\Product\Product {#128520 #id: 11861 #code: "IEEE00006700" #attributes: Doctrine\ORM\PersistentCollection {#128525 …} #variants: Doctrine\ORM\PersistentCollection {#128523 …} #options: Doctrine\ORM\PersistentCollection {#128518 …} #associations: Doctrine\ORM\PersistentCollection {#128521 …} #createdAt: DateTime @1751040040 {#128514 date: 2025-06-27 18:00:40.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608621 {#128549 date: 2025-08-08 01:17:01.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#128536 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#128625 #locale: "en_US" #translatable: App\Entity\Product\Product {#128520} #id: 42453 #name: "IEEE 1800:2017" #slug: "ieee-1800-2017-ieee00006700-243513" #description: """ Revision Standard - Superseded.<br />\n The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.<br />\n \t\t\t\t<br />\n This standard provides the definition of the language syntax and semantics for the IEEE 1800(TM) SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#128534 …} #channels: Doctrine\ORM\PersistentCollection {#128527 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#128531 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#128529 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#128541 …} -apiLastModifiedAt: DateTime @1754517600 {#128500 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1709074800 {#128548 date: 2024-02-28 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1519254000 {#128507 date: 2018-02-22 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1800" -bookCollection: "" -pageCount: 1315 -documents: Doctrine\ORM\PersistentCollection {#128540 …} -favorites: Doctrine\ORM\PersistentCollection {#128538 …} } "layout" => "vertical" "showPrice" => true "showStatusBadges" => true "additionalClasses" => "product__teaser--with-grey-border" "hasStretchedLink" => true "hoverType" => "shadow" "linkLabel" => "See more"]
Attributes	[]
Component	App\Twig\Components\ProductCard {#128593+product: App\Entity\Product\Product {#128520 #id: 11861 #code: "IEEE00006700" #attributes: Doctrine\ORM\PersistentCollection {#128525 …} #variants: Doctrine\ORM\PersistentCollection {#128523 …} #options: Doctrine\ORM\PersistentCollection {#128518 …} #associations: Doctrine\ORM\PersistentCollection {#128521 …} #createdAt: DateTime @1751040040 {#128514 date: 2025-06-27 18:00:40.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608621 {#128549 date: 2025-08-08 01:17:01.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#128536 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#128625 #locale: "en_US" #translatable: App\Entity\Product\Product {#128520} #id: 42453 #name: "IEEE 1800:2017" #slug: "ieee-1800-2017-ieee00006700-243513" #description: """ Revision Standard - Superseded.<br />\n The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.<br />\n \t\t\t\t<br />\n This standard provides the definition of the language syntax and semantics for the IEEE 1800(TM) SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#128534 …} #channels: Doctrine\ORM\PersistentCollection {#128527 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#128531 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#128529 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#128541 …} -apiLastModifiedAt: DateTime @1754517600 {#128500 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1709074800 {#128548 date: 2024-02-28 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1519254000 {#128507 date: 2018-02-22 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1800" -bookCollection: "" -pageCount: 1315 -documents: Doctrine\ORM\PersistentCollection {#128540 …} -favorites: Doctrine\ORM\PersistentCollection {#128538 …} } +layout: "vertical" +showPrice: true +showStatusBadges: true +additionalClasses: "product__teaser--with-grey-border" +linkLabel: "See more" +imageFilter: "product_thumbnail_teaser" +hasStretchedLink: true +backgroundColor: "white" +hoverType: "shadow"}

ProductCard

App\Twig\Components\ProductCard

212.0 MiB

11.53 ms

Input props

[
  "product" => App\Entity\Product\Product {#128520
    #id: 11861
    #code: "IEEE00006700"
    #attributes: Doctrine\ORM\PersistentCollection {#128525 …}
    #variants: Doctrine\ORM\PersistentCollection {#128523 …}
    #options: Doctrine\ORM\PersistentCollection {#128518 …}
    #associations: Doctrine\ORM\PersistentCollection {#128521 …}
    #createdAt: DateTime @1751040040 {#128514
      date: 2025-06-27 18:00:40.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754608621 {#128549
      date: 2025-08-08 01:17:01.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#128536 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#128625
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#128520}
        #id: 42453
        #name: "IEEE 1800:2017"
        #slug: "ieee-1800-2017-ieee00006700-243513"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800(TM) SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#128534 …}
    #channels: Doctrine\ORM\PersistentCollection {#128527 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …}
    #reviews: Doctrine\ORM\PersistentCollection {#128531 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#128529 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#128541 …}
    -apiLastModifiedAt: DateTime @1754517600 {#128500
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1709074800 {#128548
      date: 2024-02-28 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1519254000 {#128507
      date: 2018-02-22 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#128540 …}
    -favorites: Doctrine\ORM\PersistentCollection {#128538 …}
  }
  "layout" => "vertical"
  "showPrice" => true
  "showStatusBadges" => true
  "additionalClasses" => "product__teaser--with-grey-border"
  "hasStretchedLink" => true
  "hoverType" => "shadow"
  "linkLabel" => "See more"
]

Attributes

[]

Component

App\Twig\Components\ProductCard {#128593
  +product: App\Entity\Product\Product {#128520
    #id: 11861
    #code: "IEEE00006700"
    #attributes: Doctrine\ORM\PersistentCollection {#128525 …}
    #variants: Doctrine\ORM\PersistentCollection {#128523 …}
    #options: Doctrine\ORM\PersistentCollection {#128518 …}
    #associations: Doctrine\ORM\PersistentCollection {#128521 …}
    #createdAt: DateTime @1751040040 {#128514
      date: 2025-06-27 18:00:40.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754608621 {#128549
      date: 2025-08-08 01:17:01.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#128536 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#128625
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#128520}
        #id: 42453
        #name: "IEEE 1800:2017"
        #slug: "ieee-1800-2017-ieee00006700-243513"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800(TM) SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#128534 …}
    #channels: Doctrine\ORM\PersistentCollection {#128527 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …}
    #reviews: Doctrine\ORM\PersistentCollection {#128531 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#128529 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#128541 …}
    -apiLastModifiedAt: DateTime @1754517600 {#128500
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1709074800 {#128548
      date: 2024-02-28 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1519254000 {#128507
      date: 2018-02-22 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#128540 …}
    -favorites: Doctrine\ORM\PersistentCollection {#128538 …}
  }
  +layout: "vertical"
  +showPrice: true
  +showStatusBadges: true
  +additionalClasses: "product__teaser--with-grey-border"
  +linkLabel: "See more"
  +imageFilter: "product_thumbnail_teaser"
  +hasStretchedLink: true
  +backgroundColor: "white"
  +hoverType: "shadow"
}

ProductState	App\Twig\Components\ProductState	212.0 MiB	0.20 ms
Input props	["product" => App\Entity\Product\Product {#128520 #id: 11861 #code: "IEEE00006700" #attributes: Doctrine\ORM\PersistentCollection {#128525 …} #variants: Doctrine\ORM\PersistentCollection {#128523 …} #options: Doctrine\ORM\PersistentCollection {#128518 …} #associations: Doctrine\ORM\PersistentCollection {#128521 …} #createdAt: DateTime @1751040040 {#128514 date: 2025-06-27 18:00:40.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608621 {#128549 date: 2025-08-08 01:17:01.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#128536 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#128625 #locale: "en_US" #translatable: App\Entity\Product\Product {#128520} #id: 42453 #name: "IEEE 1800:2017" #slug: "ieee-1800-2017-ieee00006700-243513" #description: """ Revision Standard - Superseded.<br />\n The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.<br />\n \t\t\t\t<br />\n This standard provides the definition of the language syntax and semantics for the IEEE 1800(TM) SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#128534 …} #channels: Doctrine\ORM\PersistentCollection {#128527 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#128531 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#128529 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#128541 …} -apiLastModifiedAt: DateTime @1754517600 {#128500 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1709074800 {#128548 date: 2024-02-28 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1519254000 {#128507 date: 2018-02-22 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1800" -bookCollection: "" -pageCount: 1315 -documents: Doctrine\ORM\PersistentCollection {#128540 …} -favorites: Doctrine\ORM\PersistentCollection {#128538 …} }]
Attributes	[`"showFullLabel" => false`]
Component	App\Twig\Components\ProductState {#128629+product: App\Entity\Product\Product {#128520 #id: 11861 #code: "IEEE00006700" #attributes: Doctrine\ORM\PersistentCollection {#128525 …} #variants: Doctrine\ORM\PersistentCollection {#128523 …} #options: Doctrine\ORM\PersistentCollection {#128518 …} #associations: Doctrine\ORM\PersistentCollection {#128521 …} #createdAt: DateTime @1751040040 {#128514 date: 2025-06-27 18:00:40.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608621 {#128549 date: 2025-08-08 01:17:01.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#128536 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#128625 #locale: "en_US" #translatable: App\Entity\Product\Product {#128520} #id: 42453 #name: "IEEE 1800:2017" #slug: "ieee-1800-2017-ieee00006700-243513" #description: """ Revision Standard - Superseded.<br />\n The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.<br />\n \t\t\t\t<br />\n This standard provides the definition of the language syntax and semantics for the IEEE 1800(TM) SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#128534 …} #channels: Doctrine\ORM\PersistentCollection {#128527 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#128531 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#128529 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#128541 …} -apiLastModifiedAt: DateTime @1754517600 {#128500 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1709074800 {#128548 date: 2024-02-28 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1519254000 {#128507 date: 2018-02-22 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1800" -bookCollection: "" -pageCount: 1315 -documents: Doctrine\ORM\PersistentCollection {#128540 …} -favorites: Doctrine\ORM\PersistentCollection {#128538 …} } +appearance: "state-suspended" +labels: [ "Superseded" ] -stateAttributeCode: "state" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}}

ProductState

App\Twig\Components\ProductState

212.0 MiB

0.20 ms

Input props

[
  "product" => App\Entity\Product\Product {#128520
    #id: 11861
    #code: "IEEE00006700"
    #attributes: Doctrine\ORM\PersistentCollection {#128525 …}
    #variants: Doctrine\ORM\PersistentCollection {#128523 …}
    #options: Doctrine\ORM\PersistentCollection {#128518 …}
    #associations: Doctrine\ORM\PersistentCollection {#128521 …}
    #createdAt: DateTime @1751040040 {#128514
      date: 2025-06-27 18:00:40.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754608621 {#128549
      date: 2025-08-08 01:17:01.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#128536 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#128625
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#128520}
        #id: 42453
        #name: "IEEE 1800:2017"
        #slug: "ieee-1800-2017-ieee00006700-243513"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800(TM) SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#128534 …}
    #channels: Doctrine\ORM\PersistentCollection {#128527 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …}
    #reviews: Doctrine\ORM\PersistentCollection {#128531 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#128529 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#128541 …}
    -apiLastModifiedAt: DateTime @1754517600 {#128500
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1709074800 {#128548
      date: 2024-02-28 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1519254000 {#128507
      date: 2018-02-22 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#128540 …}
    -favorites: Doctrine\ORM\PersistentCollection {#128538 …}
  }
]

Attributes

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App\Twig\Components\ProductState {#128629
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Component	App\Twig\Components\ProductMostRecent {#128706+product: App\Entity\Product\Product {#128520 #id: 11861 #code: "IEEE00006700" #attributes: Doctrine\ORM\PersistentCollection {#128525 …} #variants: Doctrine\ORM\PersistentCollection {#128523 …} #options: Doctrine\ORM\PersistentCollection {#128518 …} #associations: Doctrine\ORM\PersistentCollection {#128521 …} #createdAt: DateTime @1751040040 {#128514 date: 2025-06-27 18:00:40.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608621 {#128549 date: 2025-08-08 01:17:01.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#128536 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#128625 #locale: "en_US" #translatable: App\Entity\Product\Product {#128520} #id: 42453 #name: "IEEE 1800:2017" #slug: "ieee-1800-2017-ieee00006700-243513" #description: """ Revision Standard - Superseded.<br />\n The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.<br />\n \t\t\t\t<br />\n This standard provides the definition of the language syntax and semantics for the IEEE 1800(TM) SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#128534 …} #channels: Doctrine\ORM\PersistentCollection {#128527 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#128531 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#128529 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#128541 …} -apiLastModifiedAt: DateTime @1754517600 {#128500 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1709074800 {#128548 date: 2024-02-28 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1519254000 {#128507 date: 2018-02-22 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1800" -bookCollection: "" -pageCount: 1315 -documents: Doctrine\ORM\PersistentCollection {#128540 …} -favorites: Doctrine\ORM\PersistentCollection {#128538 …} } +label: "Historical" +icon: "historical" -mostRecentAttributeCode: "most_recent" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}}

ProductMostRecent

App\Twig\Components\ProductMostRecent

212.0 MiB

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App\Twig\Components\ProductMostRecent {#128706
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