GET https://dev.normadoc.fr/products/ieee-796-1983-r1988-ieee00001021-240444

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IP
216.73.217.103
Profiled on
Token
aae3a5

Forms

  • sylius_add_to_cart
    • cartItem
    • _token

sylius_add_to_cart

Form type: 
"Sylius\Bundle\CoreBundle\Form\Type\Order\AddToCartType"

Errors

This form has no errors.

Default Data

Property Value
Model Format same as normalized format
Normalized Format 
Sylius\Bundle\OrderBundle\Controller\AddToCartCommand {#106899
  -cart: App\Entity\Order\Order {#13332 …}
  -cartItem: App\Entity\Order\OrderItem {#106887
    #id: null
    #order: null
    #quantity: 1
    #unitPrice: 0
    #originalUnitPrice: 0
    #total: 0
    #immutable: false
    #units: Doctrine\Common\Collections\ArrayCollection {#106911 …}
    #unitsTotal: 0
    #adjustments: Doctrine\Common\Collections\ArrayCollection {#106912 …}
    #adjustmentsTotal: 0
    #version: 1
    #variant: App\Entity\Product\ProductVariant {#8101
      #id: 2617
      #code: "IEEE00001021PDF"
      #product: App\Entity\Product\Product {#7309
        #id: 8792
        #code: "IEEE00001021"
        #attributes: Doctrine\ORM\PersistentCollection {#7702 …}
        #variants: Doctrine\ORM\PersistentCollection {#7745 …}
        #options: Doctrine\ORM\PersistentCollection {#7917
          #collection: Doctrine\Common\Collections\ArrayCollection {#7919 …}
          #initialized: true
          -snapshot: [ …4]
          -owner: App\Entity\Product\Product {#7309}
          -association: [ …21]
          -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …}
          -backRefFieldName: null
          -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#245544 …}
          -isDirty: false
        }
        #associations: Doctrine\ORM\PersistentCollection {#7901 …}
        #createdAt: DateTime @1751037714 {#7274
          date: 2025-06-27 17:21:54.0 Europe/Paris (+02:00)
        }
        #updatedAt: DateTime @1754606304 {#7322
          date: 2025-08-08 00:38:24.0 Europe/Paris (+02:00)
        }
        #enabled: true
        #translations: Doctrine\ORM\PersistentCollection {#7923 …}
        #translationsCache: [
          "en_US" => App\Entity\Product\ProductTranslation {#7922
            #locale: "en_US"
            #translatable: App\Entity\Product\Product {#7309}
            #id: 30177
            #name: "IEEE 796:1983 (R1988)"
            #slug: "ieee-796-1983-r1988-ieee00001021-240444"
            #description: """
              New IEEE Standard - Inactive-Withdrawn.<br />\n
              A general-purpose microcomputer system bus is defined, and the device-independent electrical and functional interface requirements that a module shall meet in order to interconnect and communicate unambiguously by way of the system are specified. Signal definitions and timing and electrical specifications are covered in detail for users who evaluate or design products that will be compatible with the IEEE Std 796 system bus structure. Only with the interface characteristics of microcomputer devices are covered; design specifications, performance requirements, and safety requirements of modules are omitted. The use of the standard will enable independently manufactured devices to be connected into a single functional system, permit products with a wide range of capabilities to be introduced to the system simultaneously, and result in a system with a minimum of restrictions on the performance characteristics of devices connected to the system.<br />\n
              \t\t\t\t<br />\n
              One of the most important elements in a computer system is the bus structure that supplies the interface for all the hardware components. This bus structure contains the necessary signals to allow the various system components to interact with each otherre. It allows memory and I/O data transfers, direct memory accesses, generation of interrupts, etc.<br />\n
              This standard provides a detailed description of all the elements and features that make up the IEEE Std 796 bus.<br />\n
              The bus supports two independent address spaces: memory and I/O. During memory cycles, the bus allows direct addressability of up to 16 megabytes using 24-bit addressing. During I/O bus cycles, the bus allows addressing of up to 64 kilobyte I/O ports using 16-bit addressing. Memory and I/O cycles can support 8-bit or 16-bit data transfers.<br />\n
              The bus structure is built upon the masterslave concept where the master device in the system takes control of the bus and the slave device, upon decoding its address, and acts upon the command provided by the master. This handshake (master-slave relationship) between the master and slave devices allows modules of different speeds to be interface by way of the bus. It also allows data rates up to five million transfers per second (bytes or words) to take place across the bus.<br />\n
              Anotherre important feature of the bus is the ability to connect multiple master modules for multiprocessing configurations. The bus provides control signals for connecting multiple masters in either a serial or parallel priority fashion. With either of these two arrangements, more than one master may share bus resources.<br />\n
              This standard has been prepared for those users who evaluate or design products that will be compatible with the IEEE Std 796 system bus structure. To this end, the necessary signal definitions and timing and electrical specifications have been covered in detail.<br />\n
              This standard deals only with the interface characteristics of microcomputer devices, not with design specifications, performance requirements, and safety requirements of modules.<br />\n
              Throughout this standard, the term system denotes the byte or word interface system that, in general, includes all the circuits, connectors, and control protocol to effect unambiguous data transfer between devices. The term device or module denotes any product connected to the interface system that communicates information by way of the bus, and that conforms to the interface system definition.
              """
            #metaKeywords: null
            #metaDescription: null
            #shortDescription: "IEEE Standard Microcomputer System Bus"
            -notes: "Inactive-Withdrawn"
          }
        ]
        #currentLocale: "en_US"
        #currentTranslation: null
        #fallbackLocale: "en_US"
        #variantSelectionMethod: "match"
        #productTaxons: Doctrine\ORM\PersistentCollection {#7535 …}
        #channels: Doctrine\ORM\PersistentCollection {#7629 …}
        #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7308 …}
        #reviews: Doctrine\ORM\PersistentCollection {#7614 …}
        #averageRating: 0.0
        #images: Doctrine\ORM\PersistentCollection {#7646 …}
        -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7422 …}
        -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7420 …}
        -apiLastModifiedAt: DateTime @1754517600 {#7317
          date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
        }
        -lastUpdatedAt: DateTime @1578006000 {#7292
          date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
        }
        -author: ""
        -publishedAt: DateTime @441500400 {#7318
          date: 1983-12-29 00:00:00.0 Europe/Paris (+01:00)
        }
        -releasedAt: null
        -confirmedAt: DateTime @581810400 {#7316
          date: 1988-06-09 00:00:00.0 Europe/Paris (+02:00)
        }
        -canceledAt: DateTime @979513200 {#7315
          date: 2001-01-15 00:00:00.0 Europe/Paris (+01:00)
        }
        -edition: null
        -coreDocument: "796"
        -bookCollection: ""
        -pageCount: 46
        -documents: Doctrine\ORM\PersistentCollection {#7466 …}
        -favorites: Doctrine\ORM\PersistentCollection {#7501 …}
      }
      #optionValues: Doctrine\ORM\PersistentCollection {#8317 …}
      #position: 0
      #createdAt: DateTime @1751041129 {#7283
        date: 2025-06-27 18:18:49.0 Europe/Paris (+02:00)
      }
      #updatedAt: DateTime @1756908201 {#8118
        date: 2025-09-03 16:03:21.0 Europe/Paris (+02:00)
      }
      #enabled: true
      #translations: Doctrine\ORM\PersistentCollection {#8261 …}
      #translationsCache: [
        "en_US" => App\Entity\Product\ProductVariantTranslation {#93335
          #locale: "en_US"
          #translatable: App\Entity\Product\ProductVariant {#8101}
          #id: 2635
          #name: null
          -shortDescription: null
          -description: null
          -notes: null
          -shippingInformation: "Instant download"
        }
      ]
      #currentLocale: "en_US"
      #currentTranslation: null
      #fallbackLocale: "en_US"
      #version: 9
      #onHold: 0
      #onHand: 0
      #tracked: false
      #weight: 0.0
      #width: null
      #height: null
      #depth: null
      #taxCategory: Proxies\__CG__\App\Entity\Taxation\TaxCategory {#8133 …}
      #shippingCategory: null
      #channelPricings: Doctrine\ORM\PersistentCollection {#8295 …}
      #shippingRequired: true
      #images: Doctrine\ORM\PersistentCollection {#8292 …}
      -apiLastModifiedAt: DateTime @1756850400 {#8100
        date: 2025-09-03 00:00:00.0 Europe/Paris (+02:00)
      }
      -publishedAt: null
      -isbn: "978-0-7381-2753-8"
      -ean: "9780738127538"
      -numberOfUsers: 1
      -physicalProduct: false
      -downloadableImmediately: true
      -downloadable: true
      -drmViewerUrl: "https://online-viewer.normadoc.com/bPmxYV"
      -sellable: true
      -documents: Doctrine\ORM\PersistentCollection {#8129 …}
      -drmTokens: Doctrine\ORM\PersistentCollection {#8121 …}
      -enabledForSubscribers: true
      -currentAreaContext: null
    }
    #productName: null
    #variantName: null
  }
}
View Format same as normalized format

Submitted Data

This form was not submitted.

Passed Options

Option Passed Value Resolved Value
data 
Sylius\Bundle\OrderBundle\Controller\AddToCartCommand {#106899
  -cart: App\Entity\Order\Order {#13332 …}
  -cartItem: App\Entity\Order\OrderItem {#106887
    #id: null
    #order: null
    #quantity: 1
    #unitPrice: 0
    #originalUnitPrice: 0
    #total: 0
    #immutable: false
    #units: Doctrine\Common\Collections\ArrayCollection {#106911 …}
    #unitsTotal: 0
    #adjustments: Doctrine\Common\Collections\ArrayCollection {#106912 …}
    #adjustmentsTotal: 0
    #version: 1
    #variant: App\Entity\Product\ProductVariant {#8101
      #id: 2617
      #code: "IEEE00001021PDF"
      #product: App\Entity\Product\Product {#7309
        #id: 8792
        #code: "IEEE00001021"
        #attributes: Doctrine\ORM\PersistentCollection {#7702 …}
        #variants: Doctrine\ORM\PersistentCollection {#7745 …}
        #options: Doctrine\ORM\PersistentCollection {#7917
          #collection: Doctrine\Common\Collections\ArrayCollection {#7919 …}
          #initialized: true
          -snapshot: [ …4]
          -owner: App\Entity\Product\Product {#7309}
          -association: [ …21]
          -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …}
          -backRefFieldName: null
          -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#245544 …}
          -isDirty: false
        }
        #associations: Doctrine\ORM\PersistentCollection {#7901 …}
        #createdAt: DateTime @1751037714 {#7274
          date: 2025-06-27 17:21:54.0 Europe/Paris (+02:00)
        }
        #updatedAt: DateTime @1754606304 {#7322
          date: 2025-08-08 00:38:24.0 Europe/Paris (+02:00)
        }
        #enabled: true
        #translations: Doctrine\ORM\PersistentCollection {#7923 …}
        #translationsCache: [
          "en_US" => App\Entity\Product\ProductTranslation {#7922
            #locale: "en_US"
            #translatable: App\Entity\Product\Product {#7309}
            #id: 30177
            #name: "IEEE 796:1983 (R1988)"
            #slug: "ieee-796-1983-r1988-ieee00001021-240444"
            #description: """
              New IEEE Standard - Inactive-Withdrawn.<br />\n
              A general-purpose microcomputer system bus is defined, and the device-independent electrical and functional interface requirements that a module shall meet in order to interconnect and communicate unambiguously by way of the system are specified. Signal definitions and timing and electrical specifications are covered in detail for users who evaluate or design products that will be compatible with the IEEE Std 796 system bus structure. Only with the interface characteristics of microcomputer devices are covered; design specifications, performance requirements, and safety requirements of modules are omitted. The use of the standard will enable independently manufactured devices to be connected into a single functional system, permit products with a wide range of capabilities to be introduced to the system simultaneously, and result in a system with a minimum of restrictions on the performance characteristics of devices connected to the system.<br />\n
              \t\t\t\t<br />\n
              One of the most important elements in a computer system is the bus structure that supplies the interface for all the hardware components. This bus structure contains the necessary signals to allow the various system components to interact with each otherre. It allows memory and I/O data transfers, direct memory accesses, generation of interrupts, etc.<br />\n
              This standard provides a detailed description of all the elements and features that make up the IEEE Std 796 bus.<br />\n
              The bus supports two independent address spaces: memory and I/O. During memory cycles, the bus allows direct addressability of up to 16 megabytes using 24-bit addressing. During I/O bus cycles, the bus allows addressing of up to 64 kilobyte I/O ports using 16-bit addressing. Memory and I/O cycles can support 8-bit or 16-bit data transfers.<br />\n
              The bus structure is built upon the masterslave concept where the master device in the system takes control of the bus and the slave device, upon decoding its address, and acts upon the command provided by the master. This handshake (master-slave relationship) between the master and slave devices allows modules of different speeds to be interface by way of the bus. It also allows data rates up to five million transfers per second (bytes or words) to take place across the bus.<br />\n
              Anotherre important feature of the bus is the ability to connect multiple master modules for multiprocessing configurations. The bus provides control signals for connecting multiple masters in either a serial or parallel priority fashion. With either of these two arrangements, more than one master may share bus resources.<br />\n
              This standard has been prepared for those users who evaluate or design products that will be compatible with the IEEE Std 796 system bus structure. To this end, the necessary signal definitions and timing and electrical specifications have been covered in detail.<br />\n
              This standard deals only with the interface characteristics of microcomputer devices, not with design specifications, performance requirements, and safety requirements of modules.<br />\n
              Throughout this standard, the term system denotes the byte or word interface system that, in general, includes all the circuits, connectors, and control protocol to effect unambiguous data transfer between devices. The term device or module denotes any product connected to the interface system that communicates information by way of the bus, and that conforms to the interface system definition.
              """
            #metaKeywords: null
            #metaDescription: null
            #shortDescription: "IEEE Standard Microcomputer System Bus"
            -notes: "Inactive-Withdrawn"
          }
        ]
        #currentLocale: "en_US"
        #currentTranslation: null
        #fallbackLocale: "en_US"
        #variantSelectionMethod: "match"
        #productTaxons: Doctrine\ORM\PersistentCollection {#7535 …}
        #channels: Doctrine\ORM\PersistentCollection {#7629 …}
        #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7308 …}
        #reviews: Doctrine\ORM\PersistentCollection {#7614 …}
        #averageRating: 0.0
        #images: Doctrine\ORM\PersistentCollection {#7646 …}
        -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7422 …}
        -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7420 …}
        -apiLastModifiedAt: DateTime @1754517600 {#7317
          date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
        }
        -lastUpdatedAt: DateTime @1578006000 {#7292
          date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
        }
        -author: ""
        -publishedAt: DateTime @441500400 {#7318
          date: 1983-12-29 00:00:00.0 Europe/Paris (+01:00)
        }
        -releasedAt: null
        -confirmedAt: DateTime @581810400 {#7316
          date: 1988-06-09 00:00:00.0 Europe/Paris (+02:00)
        }
        -canceledAt: DateTime @979513200 {#7315
          date: 2001-01-15 00:00:00.0 Europe/Paris (+01:00)
        }
        -edition: null
        -coreDocument: "796"
        -bookCollection: ""
        -pageCount: 46
        -documents: Doctrine\ORM\PersistentCollection {#7466 …}
        -favorites: Doctrine\ORM\PersistentCollection {#7501 …}
      }
      #optionValues: Doctrine\ORM\PersistentCollection {#8317 …}
      #position: 0
      #createdAt: DateTime @1751041129 {#7283
        date: 2025-06-27 18:18:49.0 Europe/Paris (+02:00)
      }
      #updatedAt: DateTime @1756908201 {#8118
        date: 2025-09-03 16:03:21.0 Europe/Paris (+02:00)
      }
      #enabled: true
      #translations: Doctrine\ORM\PersistentCollection {#8261 …}
      #translationsCache: [
        "en_US" => App\Entity\Product\ProductVariantTranslation {#93335
          #locale: "en_US"
          #translatable: App\Entity\Product\ProductVariant {#8101}
          #id: 2635
          #name: null
          -shortDescription: null
          -description: null
          -notes: null
          -shippingInformation: "Instant download"
        }
      ]
      #currentLocale: "en_US"
      #currentTranslation: null
      #fallbackLocale: "en_US"
      #version: 9
      #onHold: 0
      #onHand: 0
      #tracked: false
      #weight: 0.0
      #width: null
      #height: null
      #depth: null
      #taxCategory: Proxies\__CG__\App\Entity\Taxation\TaxCategory {#8133 …}
      #shippingCategory: null
      #channelPricings: Doctrine\ORM\PersistentCollection {#8295 …}
      #shippingRequired: true
      #images: Doctrine\ORM\PersistentCollection {#8292 …}
      -apiLastModifiedAt: DateTime @1756850400 {#8100
        date: 2025-09-03 00:00:00.0 Europe/Paris (+02:00)
      }
      -publishedAt: null
      -isbn: "978-0-7381-2753-8"
      -ean: "9780738127538"
      -numberOfUsers: 1
      -physicalProduct: false
      -downloadableImmediately: true
      -downloadable: true
      -drmViewerUrl: "https://online-viewer.normadoc.com/bPmxYV"
      -sellable: true
      -documents: Doctrine\ORM\PersistentCollection {#8129 …}
      -drmTokens: Doctrine\ORM\PersistentCollection {#8121 …}
      -enabledForSubscribers: true
      -currentAreaContext: null
    }
    #productName: null
    #variantName: null
  }
}
 same as passed value
product 
App\Entity\Product\Product {#7309
  #id: 8792
  #code: "IEEE00001021"
  #attributes: Doctrine\ORM\PersistentCollection {#7702 …}
  #variants: Doctrine\ORM\PersistentCollection {#7745 …}
  #options: Doctrine\ORM\PersistentCollection {#7917
    #collection: Doctrine\Common\Collections\ArrayCollection {#7919 …}
    #initialized: true
    -snapshot: [ …4]
    -owner: App\Entity\Product\Product {#7309}
    -association: [ …21]
    -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …}
    -backRefFieldName: null
    -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#245544 …}
    -isDirty: false
  }
  #associations: Doctrine\ORM\PersistentCollection {#7901 …}
  #createdAt: DateTime @1751037714 {#7274
    date: 2025-06-27 17:21:54.0 Europe/Paris (+02:00)
  }
  #updatedAt: DateTime @1754606304 {#7322
    date: 2025-08-08 00:38:24.0 Europe/Paris (+02:00)
  }
  #enabled: true
  #translations: Doctrine\ORM\PersistentCollection {#7923 …}
  #translationsCache: [
    "en_US" => App\Entity\Product\ProductTranslation {#7922
      #locale: "en_US"
      #translatable: App\Entity\Product\Product {#7309}
      #id: 30177
      #name: "IEEE 796:1983 (R1988)"
      #slug: "ieee-796-1983-r1988-ieee00001021-240444"
      #description: """
        New IEEE Standard - Inactive-Withdrawn.<br />\n
        A general-purpose microcomputer system bus is defined, and the device-independent electrical and functional interface requirements that a module shall meet in order to interconnect and communicate unambiguously by way of the system are specified. Signal definitions and timing and electrical specifications are covered in detail for users who evaluate or design products that will be compatible with the IEEE Std 796 system bus structure. Only with the interface characteristics of microcomputer devices are covered; design specifications, performance requirements, and safety requirements of modules are omitted. The use of the standard will enable independently manufactured devices to be connected into a single functional system, permit products with a wide range of capabilities to be introduced to the system simultaneously, and result in a system with a minimum of restrictions on the performance characteristics of devices connected to the system.<br />\n
        \t\t\t\t<br />\n
        One of the most important elements in a computer system is the bus structure that supplies the interface for all the hardware components. This bus structure contains the necessary signals to allow the various system components to interact with each otherre. It allows memory and I/O data transfers, direct memory accesses, generation of interrupts, etc.<br />\n
        This standard provides a detailed description of all the elements and features that make up the IEEE Std 796 bus.<br />\n
        The bus supports two independent address spaces: memory and I/O. During memory cycles, the bus allows direct addressability of up to 16 megabytes using 24-bit addressing. During I/O bus cycles, the bus allows addressing of up to 64 kilobyte I/O ports using 16-bit addressing. Memory and I/O cycles can support 8-bit or 16-bit data transfers.<br />\n
        The bus structure is built upon the masterslave concept where the master device in the system takes control of the bus and the slave device, upon decoding its address, and acts upon the command provided by the master. This handshake (master-slave relationship) between the master and slave devices allows modules of different speeds to be interface by way of the bus. It also allows data rates up to five million transfers per second (bytes or words) to take place across the bus.<br />\n
        Anotherre important feature of the bus is the ability to connect multiple master modules for multiprocessing configurations. The bus provides control signals for connecting multiple masters in either a serial or parallel priority fashion. With either of these two arrangements, more than one master may share bus resources.<br />\n
        This standard has been prepared for those users who evaluate or design products that will be compatible with the IEEE Std 796 system bus structure. To this end, the necessary signal definitions and timing and electrical specifications have been covered in detail.<br />\n
        This standard deals only with the interface characteristics of microcomputer devices, not with design specifications, performance requirements, and safety requirements of modules.<br />\n
        Throughout this standard, the term system denotes the byte or word interface system that, in general, includes all the circuits, connectors, and control protocol to effect unambiguous data transfer between devices. The term device or module denotes any product connected to the interface system that communicates information by way of the bus, and that conforms to the interface system definition.
        """
      #metaKeywords: null
      #metaDescription: null
      #shortDescription: "IEEE Standard Microcomputer System Bus"
      -notes: "Inactive-Withdrawn"
    }
  ]
  #currentLocale: "en_US"
  #currentTranslation: null
  #fallbackLocale: "en_US"
  #variantSelectionMethod: "match"
  #productTaxons: Doctrine\ORM\PersistentCollection {#7535 …}
  #channels: Doctrine\ORM\PersistentCollection {#7629 …}
  #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7308 …}
  #reviews: Doctrine\ORM\PersistentCollection {#7614 …}
  #averageRating: 0.0
  #images: Doctrine\ORM\PersistentCollection {#7646 …}
  -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7422 …}
  -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7420 …}
  -apiLastModifiedAt: DateTime @1754517600 {#7317
    date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
  }
  -lastUpdatedAt: DateTime @1578006000 {#7292
    date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
  }
  -author: ""
  -publishedAt: DateTime @441500400 {#7318
    date: 1983-12-29 00:00:00.0 Europe/Paris (+01:00)
  }
  -releasedAt: null
  -confirmedAt: DateTime @581810400 {#7316
    date: 1988-06-09 00:00:00.0 Europe/Paris (+02:00)
  }
  -canceledAt: DateTime @979513200 {#7315
    date: 2001-01-15 00:00:00.0 Europe/Paris (+01:00)
  }
  -edition: null
  -coreDocument: "796"
  -bookCollection: ""
  -pageCount: 46
  -documents: Doctrine\ORM\PersistentCollection {#7466 …}
  -favorites: Doctrine\ORM\PersistentCollection {#7501 …}
}
 same as passed value

Resolved Options

Option Value
action 
""
allow_extra_fields 
false
allow_file_upload 
false
attr 
[]
attr_translation_parameters 
[]
auto_initialize 
true
block_name 
null
block_prefix 
null
by_reference 
true
compound 
true
constraints 
[]
csrf_field_name 
"_token"
csrf_message 
"The CSRF token is invalid. Please try to resubmit the form."
csrf_protection 
true
csrf_token_id 
null
csrf_token_manager 
Symfony\Component\Security\Csrf\CsrfTokenManager {#106919
  -generator: Symfony\Component\Security\Csrf\TokenGenerator\UriSafeTokenGenerator {#106920 …}
  -storage: Symfony\Component\Security\Csrf\TokenStorage\SessionTokenStorage {#106921 …}
  -namespace: Closure() {#106923 …}
}
data 
Sylius\Bundle\OrderBundle\Controller\AddToCartCommand {#106899
  -cart: App\Entity\Order\Order {#13332 …}
  -cartItem: App\Entity\Order\OrderItem {#106887
    #id: null
    #order: null
    #quantity: 1
    #unitPrice: 0
    #originalUnitPrice: 0
    #total: 0
    #immutable: false
    #units: Doctrine\Common\Collections\ArrayCollection {#106911 …}
    #unitsTotal: 0
    #adjustments: Doctrine\Common\Collections\ArrayCollection {#106912 …}
    #adjustmentsTotal: 0
    #version: 1
    #variant: App\Entity\Product\ProductVariant {#8101
      #id: 2617
      #code: "IEEE00001021PDF"
      #product: App\Entity\Product\Product {#7309
        #id: 8792
        #code: "IEEE00001021"
        #attributes: Doctrine\ORM\PersistentCollection {#7702 …}
        #variants: Doctrine\ORM\PersistentCollection {#7745 …}
        #options: Doctrine\ORM\PersistentCollection {#7917
          #collection: Doctrine\Common\Collections\ArrayCollection {#7919 …}
          #initialized: true
          -snapshot: [ …4]
          -owner: App\Entity\Product\Product {#7309}
          -association: [ …21]
          -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …}
          -backRefFieldName: null
          -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#245544 …}
          -isDirty: false
        }
        #associations: Doctrine\ORM\PersistentCollection {#7901 …}
        #createdAt: DateTime @1751037714 {#7274
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              New IEEE Standard - Inactive-Withdrawn.<br />\n
              A general-purpose microcomputer system bus is defined, and the device-independent electrical and functional interface requirements that a module shall meet in order to interconnect and communicate unambiguously by way of the system are specified. Signal definitions and timing and electrical specifications are covered in detail for users who evaluate or design products that will be compatible with the IEEE Std 796 system bus structure. Only with the interface characteristics of microcomputer devices are covered; design specifications, performance requirements, and safety requirements of modules are omitted. The use of the standard will enable independently manufactured devices to be connected into a single functional system, permit products with a wide range of capabilities to be introduced to the system simultaneously, and result in a system with a minimum of restrictions on the performance characteristics of devices connected to the system.<br />\n
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              The bus supports two independent address spaces: memory and I/O. During memory cycles, the bus allows direct addressability of up to 16 megabytes using 24-bit addressing. During I/O bus cycles, the bus allows addressing of up to 64 kilobyte I/O ports using 16-bit addressing. Memory and I/O cycles can support 8-bit or 16-bit data transfers.<br />\n
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              This standard has been prepared for those users who evaluate or design products that will be compatible with the IEEE Std 796 system bus structure. To this end, the necessary signal definitions and timing and electrical specifications have been covered in detail.<br />\n
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        This standard provides a detailed description of all the elements and features that make up the IEEE Std 796 bus.<br />\n
        The bus supports two independent address spaces: memory and I/O. During memory cycles, the bus allows direct addressability of up to 16 megabytes using 24-bit addressing. During I/O bus cycles, the bus allows addressing of up to 64 kilobyte I/O ports using 16-bit addressing. Memory and I/O cycles can support 8-bit or 16-bit data transfers.<br />\n
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        Anotherre important feature of the bus is the ability to connect multiple master modules for multiprocessing configurations. The bus provides control signals for connecting multiple masters in either a serial or parallel priority fashion. With either of these two arrangements, more than one master may share bus resources.<br />\n
        This standard has been prepared for those users who evaluate or design products that will be compatible with the IEEE Std 796 system bus structure. To this end, the necessary signal definitions and timing and electrical specifications have been covered in detail.<br />\n
        This standard deals only with the interface characteristics of microcomputer devices, not with design specifications, performance requirements, and safety requirements of modules.<br />\n
        Throughout this standard, the term system denotes the byte or word interface system that, in general, includes all the circuits, connectors, and control protocol to effect unambiguous data transfer between devices. The term device or module denotes any product connected to the interface system that communicates information by way of the bus, and that conforms to the interface system definition.
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upload_max_size_message 
Closure() {#106948
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    $message: Closure() {#106947 …}
    $translationDomain: "validators"
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              A general-purpose microcomputer system bus is defined, and the device-independent electrical and functional interface requirements that a module shall meet in order to interconnect and communicate unambiguously by way of the system are specified. Signal definitions and timing and electrical specifications are covered in detail for users who evaluate or design products that will be compatible with the IEEE Std 796 system bus structure. Only with the interface characteristics of microcomputer devices are covered; design specifications, performance requirements, and safety requirements of modules are omitted. The use of the standard will enable independently manufactured devices to be connected into a single functional system, permit products with a wide range of capabilities to be introduced to the system simultaneously, and result in a system with a minimum of restrictions on the performance characteristics of devices connected to the system.<br />\n
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              New IEEE Standard - Inactive-Withdrawn.<br />\n
              A general-purpose microcomputer system bus is defined, and the device-independent electrical and functional interface requirements that a module shall meet in order to interconnect and communicate unambiguously by way of the system are specified. Signal definitions and timing and electrical specifications are covered in detail for users who evaluate or design products that will be compatible with the IEEE Std 796 system bus structure. Only with the interface characteristics of microcomputer devices are covered; design specifications, performance requirements, and safety requirements of modules are omitted. The use of the standard will enable independently manufactured devices to be connected into a single functional system, permit products with a wide range of capabilities to be introduced to the system simultaneously, and result in a system with a minimum of restrictions on the performance characteristics of devices connected to the system.<br />\n
              \t\t\t\t<br />\n
              One of the most important elements in a computer system is the bus structure that supplies the interface for all the hardware components. This bus structure contains the necessary signals to allow the various system components to interact with each otherre. It allows memory and I/O data transfers, direct memory accesses, generation of interrupts, etc.<br />\n
              This standard provides a detailed description of all the elements and features that make up the IEEE Std 796 bus.<br />\n
              The bus supports two independent address spaces: memory and I/O. During memory cycles, the bus allows direct addressability of up to 16 megabytes using 24-bit addressing. During I/O bus cycles, the bus allows addressing of up to 64 kilobyte I/O ports using 16-bit addressing. Memory and I/O cycles can support 8-bit or 16-bit data transfers.<br />\n
              The bus structure is built upon the masterslave concept where the master device in the system takes control of the bus and the slave device, upon decoding its address, and acts upon the command provided by the master. This handshake (master-slave relationship) between the master and slave devices allows modules of different speeds to be interface by way of the bus. It also allows data rates up to five million transfers per second (bytes or words) to take place across the bus.<br />\n
              Anotherre important feature of the bus is the ability to connect multiple master modules for multiprocessing configurations. The bus provides control signals for connecting multiple masters in either a serial or parallel priority fashion. With either of these two arrangements, more than one master may share bus resources.<br />\n
              This standard has been prepared for those users who evaluate or design products that will be compatible with the IEEE Std 796 system bus structure. To this end, the necessary signal definitions and timing and electrical specifications have been covered in detail.<br />\n
              This standard deals only with the interface characteristics of microcomputer devices, not with design specifications, performance requirements, and safety requirements of modules.<br />\n
              Throughout this standard, the term system denotes the byte or word interface system that, in general, includes all the circuits, connectors, and control protocol to effect unambiguous data transfer between devices. The term device or module denotes any product connected to the interface system that communicates information by way of the bus, and that conforms to the interface system definition.
              """
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          date: 1983-12-29 00:00:00.0 Europe/Paris (+01:00)
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          date: 1988-06-09 00:00:00.0 Europe/Paris (+02:00)
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