GET https://dev.normadoc.fr/products/ieee-1076-3-1997-ieee00001615-240749

Response
200 OK
IP
216.73.216.116
Profiled on
Token
a273f8

Forms

  • sylius_add_to_cart
    • cartItem
    • _token

sylius_add_to_cart

Form type: 
"Sylius\Bundle\CoreBundle\Form\Type\Order\AddToCartType"

Errors

This form has no errors.

Default Data

Property Value
Model Format same as normalized format
Normalized Format 
Sylius\Bundle\OrderBundle\Controller\AddToCartCommand {#106903
  -cart: App\Entity\Order\Order {#13330 …}
  -cartItem: App\Entity\Order\OrderItem {#106891
    #id: null
    #order: null
    #quantity: 1
    #unitPrice: 0
    #originalUnitPrice: 0
    #total: 0
    #immutable: false
    #units: Doctrine\Common\Collections\ArrayCollection {#106915 …}
    #unitsTotal: 0
    #adjustments: Doctrine\Common\Collections\ArrayCollection {#106916 …}
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    #version: 1
    #variant: App\Entity\Product\ProductVariant {#8099
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      #code: "IEEE00001615PDF"
      #product: App\Entity\Product\Product {#7310
        #id: 9097
        #code: "IEEE00001615"
        #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
        #variants: Doctrine\ORM\PersistentCollection {#7743 …}
        #options: Doctrine\ORM\PersistentCollection {#7915
          #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …}
          #initialized: true
          -snapshot: [ …4]
          -owner: App\Entity\Product\Product {#7310}
          -association: [ …21]
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        #associations: Doctrine\ORM\PersistentCollection {#7899 …}
        #createdAt: DateTime @1751037968 {#7274
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        }
        #updatedAt: DateTime @1754607004 {#7322
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        }
        #enabled: true
        #translations: Doctrine\ORM\PersistentCollection {#7921 …}
        #translationsCache: [
          "en_US" => App\Entity\Product\ProductTranslation {#7920
            #locale: "en_US"
            #translatable: App\Entity\Product\Product {#7310}
            #id: 31397
            #name: "IEEE 1076.3:1997"
            #slug: "ieee-1076-3-1997-ieee00001615-240749"
            #description: """
              New IEEE Standard - Superseded.<br />\n
              The current interpretation of common logic values and the association of numeric values to specific VHDL array types is described. This standard provides semantic for the VHDL synthesis domain, and enables formal verification and simulation acceleration in the VHDL based design. The standard interpretations are provided for values of standard logic types defined by IEEE Std 1164-1993, and of the BIT and BOOLEAN types defined in IEEE Std 1076-1993. The numeric types SIGNED and UNSIGNED and their associated operators define integer and natural number arithmetic for arrays of common logic values. Twos complement and binary encoding techniques are used. The numeric semantic is conveyed by two VHDL packages. This standard also contains any allowable modifications.<br />\n
              \t\t\t\t<br />\n
              This standard defines standard practices for synthesizing binary digital electronic circuits from VHDL source code. It includes the following:<br />\n
              a) The hardware interpretation of values belonging to the BIT and BOOLEAN types deÞned by IEEE<br />\n
              Std 1076-1993 and to the STD_ULOGIC type defined by IEEE Std 1164-1993.<br />\n
              b) A function (STD_MATCH) that provides &quot;don't care&quot; or &quot;wild card&quot; testing of values based on the<br />\n
              STD_ULOGIC type.<br />\n
              c) Standard functions for representing sensitivity to the edge of a signal.<br />\n
              d) Two packages that deÞne vector types for representing signed and unsigned arithmetic values, and<br />\n
              that define arithmetic, shift, and type conversion operations on those types.<br />\n
              This standard is designed for use with IEEE Std 1076-1993. Modifications that may be made to the packages for use with the previous edition, IEEE Std 1076-1987, are described in 7.2.<br />\n
              Only some parts of the VHSIC Hardware Description Language (VHDL) are able to be synthesized currently. There are also no current standards describing how to create these needed portable descriptions in VHDL that can be synthesized. This standard will define a set of packages to allow this portability of synthesizable descriptions.
              """
            #metaKeywords: null
            #metaDescription: null
            #shortDescription: "IEEE Standard VHDL Synthesis Packages"
            -notes: "Superseded"
          }
        ]
        #currentLocale: "en_US"
        #currentTranslation: null
        #fallbackLocale: "en_US"
        #variantSelectionMethod: "match"
        #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
        #channels: Doctrine\ORM\PersistentCollection {#7627 …}
        #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
        #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
        #averageRating: 0.0
        #images: Doctrine\ORM\PersistentCollection {#7644 …}
        -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
        -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
        -apiLastModifiedAt: DateTime @1754517600 {#7317
          date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
        }
        -lastUpdatedAt: DateTime @1578006000 {#7292
          date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
        }
        -author: ""
        -publishedAt: DateTime @865461600 {#7318
          date: 1997-06-05 00:00:00.0 Europe/Paris (+02:00)
        }
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        -confirmedAt: null
        -canceledAt: null
        -edition: null
        -coreDocument: "1076.3"
        -bookCollection: ""
        -pageCount: 52
        -documents: Doctrine\ORM\PersistentCollection {#7464 …}
        -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
      }
      #optionValues: Doctrine\ORM\PersistentCollection {#8315 …}
      #position: 0
      #createdAt: DateTime @1751041138 {#7283
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      }
      #updatedAt: DateTime @1757772163 {#8116
        date: 2025-09-13 16:02:43.0 Europe/Paris (+02:00)
      }
      #enabled: true
      #translations: Doctrine\ORM\PersistentCollection {#8259 …}
      #translationsCache: [
        "en_US" => App\Entity\Product\ProductVariantTranslation {#93313
          #locale: "en_US"
          #translatable: App\Entity\Product\ProductVariant {#8099}
          #id: 2958
          #name: null
          -shortDescription: null
          -description: null
          -notes: null
          -shippingInformation: "Instant download"
        }
      ]
      #currentLocale: "en_US"
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      #version: 10
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      #weight: 0.0
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      #taxCategory: Proxies\__CG__\App\Entity\Taxation\TaxCategory {#8131 …}
      #shippingCategory: null
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      #shippingRequired: true
      #images: Doctrine\ORM\PersistentCollection {#8290 …}
      -apiLastModifiedAt: DateTime @1757714400 {#8098
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      -publishedAt: null
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      -documents: Doctrine\ORM\PersistentCollection {#8127 …}
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      -currentAreaContext: null
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    #productName: null
    #variantName: null
  }
}
View Format same as normalized format

Submitted Data

This form was not submitted.

Passed Options

Option Passed Value Resolved Value
data 
Sylius\Bundle\OrderBundle\Controller\AddToCartCommand {#106903
  -cart: App\Entity\Order\Order {#13330 …}
  -cartItem: App\Entity\Order\OrderItem {#106891
    #id: null
    #order: null
    #quantity: 1
    #unitPrice: 0
    #originalUnitPrice: 0
    #total: 0
    #immutable: false
    #units: Doctrine\Common\Collections\ArrayCollection {#106915 …}
    #unitsTotal: 0
    #adjustments: Doctrine\Common\Collections\ArrayCollection {#106916 …}
    #adjustmentsTotal: 0
    #version: 1
    #variant: App\Entity\Product\ProductVariant {#8099
      #id: 2940
      #code: "IEEE00001615PDF"
      #product: App\Entity\Product\Product {#7310
        #id: 9097
        #code: "IEEE00001615"
        #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
        #variants: Doctrine\ORM\PersistentCollection {#7743 …}
        #options: Doctrine\ORM\PersistentCollection {#7915
          #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …}
          #initialized: true
          -snapshot: [ …4]
          -owner: App\Entity\Product\Product {#7310}
          -association: [ …21]
          -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …}
          -backRefFieldName: null
          -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#246214 …}
          -isDirty: false
        }
        #associations: Doctrine\ORM\PersistentCollection {#7899 …}
        #createdAt: DateTime @1751037968 {#7274
          date: 2025-06-27 17:26:08.0 Europe/Paris (+02:00)
        }
        #updatedAt: DateTime @1754607004 {#7322
          date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
        }
        #enabled: true
        #translations: Doctrine\ORM\PersistentCollection {#7921 …}
        #translationsCache: [
          "en_US" => App\Entity\Product\ProductTranslation {#7920
            #locale: "en_US"
            #translatable: App\Entity\Product\Product {#7310}
            #id: 31397
            #name: "IEEE 1076.3:1997"
            #slug: "ieee-1076-3-1997-ieee00001615-240749"
            #description: """
              New IEEE Standard - Superseded.<br />\n
              The current interpretation of common logic values and the association of numeric values to specific VHDL array types is described. This standard provides semantic for the VHDL synthesis domain, and enables formal verification and simulation acceleration in the VHDL based design. The standard interpretations are provided for values of standard logic types defined by IEEE Std 1164-1993, and of the BIT and BOOLEAN types defined in IEEE Std 1076-1993. The numeric types SIGNED and UNSIGNED and their associated operators define integer and natural number arithmetic for arrays of common logic values. Twos complement and binary encoding techniques are used. The numeric semantic is conveyed by two VHDL packages. This standard also contains any allowable modifications.<br />\n
              \t\t\t\t<br />\n
              This standard defines standard practices for synthesizing binary digital electronic circuits from VHDL source code. It includes the following:<br />\n
              a) The hardware interpretation of values belonging to the BIT and BOOLEAN types deÞned by IEEE<br />\n
              Std 1076-1993 and to the STD_ULOGIC type defined by IEEE Std 1164-1993.<br />\n
              b) A function (STD_MATCH) that provides &quot;don't care&quot; or &quot;wild card&quot; testing of values based on the<br />\n
              STD_ULOGIC type.<br />\n
              c) Standard functions for representing sensitivity to the edge of a signal.<br />\n
              d) Two packages that deÞne vector types for representing signed and unsigned arithmetic values, and<br />\n
              that define arithmetic, shift, and type conversion operations on those types.<br />\n
              This standard is designed for use with IEEE Std 1076-1993. Modifications that may be made to the packages for use with the previous edition, IEEE Std 1076-1987, are described in 7.2.<br />\n
              Only some parts of the VHSIC Hardware Description Language (VHDL) are able to be synthesized currently. There are also no current standards describing how to create these needed portable descriptions in VHDL that can be synthesized. This standard will define a set of packages to allow this portability of synthesizable descriptions.
              """
            #metaKeywords: null
            #metaDescription: null
            #shortDescription: "IEEE Standard VHDL Synthesis Packages"
            -notes: "Superseded"
          }
        ]
        #currentLocale: "en_US"
        #currentTranslation: null
        #fallbackLocale: "en_US"
        #variantSelectionMethod: "match"
        #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
        #channels: Doctrine\ORM\PersistentCollection {#7627 …}
        #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
        #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
        #averageRating: 0.0
        #images: Doctrine\ORM\PersistentCollection {#7644 …}
        -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
        -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
        -apiLastModifiedAt: DateTime @1754517600 {#7317
          date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
        }
        -lastUpdatedAt: DateTime @1578006000 {#7292
          date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
        }
        -author: ""
        -publishedAt: DateTime @865461600 {#7318
          date: 1997-06-05 00:00:00.0 Europe/Paris (+02:00)
        }
        -releasedAt: null
        -confirmedAt: null
        -canceledAt: null
        -edition: null
        -coreDocument: "1076.3"
        -bookCollection: ""
        -pageCount: 52
        -documents: Doctrine\ORM\PersistentCollection {#7464 …}
        -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
      }
      #optionValues: Doctrine\ORM\PersistentCollection {#8315 …}
      #position: 0
      #createdAt: DateTime @1751041138 {#7283
        date: 2025-06-27 18:18:58.0 Europe/Paris (+02:00)
      }
      #updatedAt: DateTime @1757772163 {#8116
        date: 2025-09-13 16:02:43.0 Europe/Paris (+02:00)
      }
      #enabled: true
      #translations: Doctrine\ORM\PersistentCollection {#8259 …}
      #translationsCache: [
        "en_US" => App\Entity\Product\ProductVariantTranslation {#93313
          #locale: "en_US"
          #translatable: App\Entity\Product\ProductVariant {#8099}
          #id: 2958
          #name: null
          -shortDescription: null
          -description: null
          -notes: null
          -shippingInformation: "Instant download"
        }
      ]
      #currentLocale: "en_US"
      #currentTranslation: null
      #fallbackLocale: "en_US"
      #version: 10
      #onHold: 0
      #onHand: 0
      #tracked: false
      #weight: 0.0
      #width: null
      #height: null
      #depth: null
      #taxCategory: Proxies\__CG__\App\Entity\Taxation\TaxCategory {#8131 …}
      #shippingCategory: null
      #channelPricings: Doctrine\ORM\PersistentCollection {#8293 …}
      #shippingRequired: true
      #images: Doctrine\ORM\PersistentCollection {#8290 …}
      -apiLastModifiedAt: DateTime @1757714400 {#8098
        date: 2025-09-13 00:00:00.0 Europe/Paris (+02:00)
      }
      -publishedAt: null
      -isbn: "978-0-7381-0989-3"
      -ean: "9780738109893"
      -numberOfUsers: 1
      -physicalProduct: false
      -downloadableImmediately: true
      -downloadable: true
      -drmViewerUrl: null
      -sellable: true
      -documents: Doctrine\ORM\PersistentCollection {#8127 …}
      -drmTokens: Doctrine\ORM\PersistentCollection {#8119 …}
      -enabledForSubscribers: false
      -currentAreaContext: null
    }
    #productName: null
    #variantName: null
  }
}
 same as passed value
product 
App\Entity\Product\Product {#7310
  #id: 9097
  #code: "IEEE00001615"
  #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
  #variants: Doctrine\ORM\PersistentCollection {#7743 …}
  #options: Doctrine\ORM\PersistentCollection {#7915
    #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …}
    #initialized: true
    -snapshot: [ …4]
    -owner: App\Entity\Product\Product {#7310}
    -association: [ …21]
    -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …}
    -backRefFieldName: null
    -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#246214 …}
    -isDirty: false
  }
  #associations: Doctrine\ORM\PersistentCollection {#7899 …}
  #createdAt: DateTime @1751037968 {#7274
    date: 2025-06-27 17:26:08.0 Europe/Paris (+02:00)
  }
  #updatedAt: DateTime @1754607004 {#7322
    date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
  }
  #enabled: true
  #translations: Doctrine\ORM\PersistentCollection {#7921 …}
  #translationsCache: [
    "en_US" => App\Entity\Product\ProductTranslation {#7920
      #locale: "en_US"
      #translatable: App\Entity\Product\Product {#7310}
      #id: 31397
      #name: "IEEE 1076.3:1997"
      #slug: "ieee-1076-3-1997-ieee00001615-240749"
      #description: """
        New IEEE Standard - Superseded.<br />\n
        The current interpretation of common logic values and the association of numeric values to specific VHDL array types is described. This standard provides semantic for the VHDL synthesis domain, and enables formal verification and simulation acceleration in the VHDL based design. The standard interpretations are provided for values of standard logic types defined by IEEE Std 1164-1993, and of the BIT and BOOLEAN types defined in IEEE Std 1076-1993. The numeric types SIGNED and UNSIGNED and their associated operators define integer and natural number arithmetic for arrays of common logic values. Twos complement and binary encoding techniques are used. The numeric semantic is conveyed by two VHDL packages. This standard also contains any allowable modifications.<br />\n
        \t\t\t\t<br />\n
        This standard defines standard practices for synthesizing binary digital electronic circuits from VHDL source code. It includes the following:<br />\n
        a) The hardware interpretation of values belonging to the BIT and BOOLEAN types deÞned by IEEE<br />\n
        Std 1076-1993 and to the STD_ULOGIC type defined by IEEE Std 1164-1993.<br />\n
        b) A function (STD_MATCH) that provides &quot;don't care&quot; or &quot;wild card&quot; testing of values based on the<br />\n
        STD_ULOGIC type.<br />\n
        c) Standard functions for representing sensitivity to the edge of a signal.<br />\n
        d) Two packages that deÞne vector types for representing signed and unsigned arithmetic values, and<br />\n
        that define arithmetic, shift, and type conversion operations on those types.<br />\n
        This standard is designed for use with IEEE Std 1076-1993. Modifications that may be made to the packages for use with the previous edition, IEEE Std 1076-1987, are described in 7.2.<br />\n
        Only some parts of the VHSIC Hardware Description Language (VHDL) are able to be synthesized currently. There are also no current standards describing how to create these needed portable descriptions in VHDL that can be synthesized. This standard will define a set of packages to allow this portability of synthesizable descriptions.
        """
      #metaKeywords: null
      #metaDescription: null
      #shortDescription: "IEEE Standard VHDL Synthesis Packages"
      -notes: "Superseded"
    }
  ]
  #currentLocale: "en_US"
  #currentTranslation: null
  #fallbackLocale: "en_US"
  #variantSelectionMethod: "match"
  #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
  #channels: Doctrine\ORM\PersistentCollection {#7627 …}
  #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
  #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
  #averageRating: 0.0
  #images: Doctrine\ORM\PersistentCollection {#7644 …}
  -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
  -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
  -apiLastModifiedAt: DateTime @1754517600 {#7317
    date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
  }
  -lastUpdatedAt: DateTime @1578006000 {#7292
    date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
  }
  -author: ""
  -publishedAt: DateTime @865461600 {#7318
    date: 1997-06-05 00:00:00.0 Europe/Paris (+02:00)
  }
  -releasedAt: null
  -confirmedAt: null
  -canceledAt: null
  -edition: null
  -coreDocument: "1076.3"
  -bookCollection: ""
  -pageCount: 52
  -documents: Doctrine\ORM\PersistentCollection {#7464 …}
  -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
}
 same as passed value

Resolved Options

Option Value
action 
""
allow_extra_fields 
false
allow_file_upload 
false
attr 
[]
attr_translation_parameters 
[]
auto_initialize 
true
block_name 
null
block_prefix 
null
by_reference 
true
compound 
true
constraints 
[]
csrf_field_name 
"_token"
csrf_message 
"The CSRF token is invalid. Please try to resubmit the form."
csrf_protection 
true
csrf_token_id 
null
csrf_token_manager 
Symfony\Component\Security\Csrf\CsrfTokenManager {#106923
  -generator: Symfony\Component\Security\Csrf\TokenGenerator\UriSafeTokenGenerator {#106924 …}
  -storage: Symfony\Component\Security\Csrf\TokenStorage\SessionTokenStorage {#106925 …}
  -namespace: Closure() {#106927 …}
}
data 
Sylius\Bundle\OrderBundle\Controller\AddToCartCommand {#106903
  -cart: App\Entity\Order\Order {#13330 …}
  -cartItem: App\Entity\Order\OrderItem {#106891
    #id: null
    #order: null
    #quantity: 1
    #unitPrice: 0
    #originalUnitPrice: 0
    #total: 0
    #immutable: false
    #units: Doctrine\Common\Collections\ArrayCollection {#106915 …}
    #unitsTotal: 0
    #adjustments: Doctrine\Common\Collections\ArrayCollection {#106916 …}
    #adjustmentsTotal: 0
    #version: 1
    #variant: App\Entity\Product\ProductVariant {#8099
      #id: 2940
      #code: "IEEE00001615PDF"
      #product: App\Entity\Product\Product {#7310
        #id: 9097
        #code: "IEEE00001615"
        #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
        #variants: Doctrine\ORM\PersistentCollection {#7743 …}
        #options: Doctrine\ORM\PersistentCollection {#7915
          #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …}
          #initialized: true
          -snapshot: [ …4]
          -owner: App\Entity\Product\Product {#7310}
          -association: [ …21]
          -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …}
          -backRefFieldName: null
          -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#246214 …}
          -isDirty: false
        }
        #associations: Doctrine\ORM\PersistentCollection {#7899 …}
        #createdAt: DateTime @1751037968 {#7274
          date: 2025-06-27 17:26:08.0 Europe/Paris (+02:00)
        }
        #updatedAt: DateTime @1754607004 {#7322
          date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
        }
        #enabled: true
        #translations: Doctrine\ORM\PersistentCollection {#7921 …}
        #translationsCache: [
          "en_US" => App\Entity\Product\ProductTranslation {#7920
            #locale: "en_US"
            #translatable: App\Entity\Product\Product {#7310}
            #id: 31397
            #name: "IEEE 1076.3:1997"
            #slug: "ieee-1076-3-1997-ieee00001615-240749"
            #description: """
              New IEEE Standard - Superseded.<br />\n
              The current interpretation of common logic values and the association of numeric values to specific VHDL array types is described. This standard provides semantic for the VHDL synthesis domain, and enables formal verification and simulation acceleration in the VHDL based design. The standard interpretations are provided for values of standard logic types defined by IEEE Std 1164-1993, and of the BIT and BOOLEAN types defined in IEEE Std 1076-1993. The numeric types SIGNED and UNSIGNED and their associated operators define integer and natural number arithmetic for arrays of common logic values. Twos complement and binary encoding techniques are used. The numeric semantic is conveyed by two VHDL packages. This standard also contains any allowable modifications.<br />\n
              \t\t\t\t<br />\n
              This standard defines standard practices for synthesizing binary digital electronic circuits from VHDL source code. It includes the following:<br />\n
              a) The hardware interpretation of values belonging to the BIT and BOOLEAN types deÞned by IEEE<br />\n
              Std 1076-1993 and to the STD_ULOGIC type defined by IEEE Std 1164-1993.<br />\n
              b) A function (STD_MATCH) that provides &quot;don't care&quot; or &quot;wild card&quot; testing of values based on the<br />\n
              STD_ULOGIC type.<br />\n
              c) Standard functions for representing sensitivity to the edge of a signal.<br />\n
              d) Two packages that deÞne vector types for representing signed and unsigned arithmetic values, and<br />\n
              that define arithmetic, shift, and type conversion operations on those types.<br />\n
              This standard is designed for use with IEEE Std 1076-1993. Modifications that may be made to the packages for use with the previous edition, IEEE Std 1076-1987, are described in 7.2.<br />\n
              Only some parts of the VHSIC Hardware Description Language (VHDL) are able to be synthesized currently. There are also no current standards describing how to create these needed portable descriptions in VHDL that can be synthesized. This standard will define a set of packages to allow this portability of synthesizable descriptions.
              """
            #metaKeywords: null
            #metaDescription: null
            #shortDescription: "IEEE Standard VHDL Synthesis Packages"
            -notes: "Superseded"
          }
        ]
        #currentLocale: "en_US"
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