GET https://dev.normadoc.fr/_partial/cart/summary?template=%40SyliusShop%2FCart%2F_widget.html.twig

Components

3 Twig Components
11 Render Count
5 ms Render Time
202.0 MiB Memory Usage

Components

Name Metadata Render Count Render Time
ProductState
"App\Twig\Components\ProductState"
components/ProductState.html.twig
5 1.18ms
ProductMostRecent
"App\Twig\Components\ProductMostRecent"
components/ProductMostRecent.html.twig
5 3.33ms
ProductType
"App\Twig\Components\ProductType"
components/ProductType.html.twig
1 0.22ms

Render calls

ProductState App\Twig\Components\ProductState 202.0 MiB 0.29 ms
Input props
[
  "product" => App\Entity\Product\Product {#7310
    #id: 9957
    #code: "IEEE00003339"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751038699 {#7274
      date: 2025-06-27 17:38:19.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#7322
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 34837
        #name: "IEEE 1481:2009"
        #slug: "ieee-1481-2009-ieee00003339-241609"
        #description: """
          Revision Standard - Superseded.<br />\n
          Ways for integrated circuit designers to analyze chip timing and power consistently across a broad set of electric design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, this standard covers means by which EDA vendors can meet their application performance and capacity needs.<br />\n
          \t\t\t\t<br />\n
          The scope of this standard focuses on delay and power calculation for integrated circuit design with support for modeling logical behavior and signal integrity.<br />\n
          To improve the IEEE 1481-1999 standard system for integrated circuit designers to more accurately and more completely analyze semiconductor designs across EDA applications and for integrated circuit vendors to express logical behavior, signal integrity, delay, and power information only once per technology while<br />\n
          enabling sufficient EDA application accuracy.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Integrated Circuit (IC) Open Library Architecture (OLA)"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1585778400 {#7292
      date: 2020-04-02 00:00:00.0 Europe/Paris (+02:00)
    }
    -author: ""
    -publishedAt: DateTime @1268262000 {#7318
      date: 2010-03-11 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1481"
    -bookCollection: ""
    -pageCount: 658
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  "showFullLabel" => "true"
]
Attributes
[
  "showFullLabel" => "true"
]
Component
App\Twig\Components\ProductState {#93054
  +product: App\Entity\Product\Product {#7310
    #id: 9957
    #code: "IEEE00003339"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751038699 {#7274
      date: 2025-06-27 17:38:19.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#7322
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 34837
        #name: "IEEE 1481:2009"
        #slug: "ieee-1481-2009-ieee00003339-241609"
        #description: """
          Revision Standard - Superseded.<br />\n
          Ways for integrated circuit designers to analyze chip timing and power consistently across a broad set of electric design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, this standard covers means by which EDA vendors can meet their application performance and capacity needs.<br />\n
          \t\t\t\t<br />\n
          The scope of this standard focuses on delay and power calculation for integrated circuit design with support for modeling logical behavior and signal integrity.<br />\n
          To improve the IEEE 1481-1999 standard system for integrated circuit designers to more accurately and more completely analyze semiconductor designs across EDA applications and for integrated circuit vendors to express logical behavior, signal integrity, delay, and power information only once per technology while<br />\n
          enabling sufficient EDA application accuracy.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Integrated Circuit (IC) Open Library Architecture (OLA)"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1585778400 {#7292
      date: 2020-04-02 00:00:00.0 Europe/Paris (+02:00)
    }
    -author: ""
    -publishedAt: DateTime @1268262000 {#7318
      date: 2010-03-11 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1481"
    -bookCollection: ""
    -pageCount: 658
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductType App\Twig\Components\ProductType 202.0 MiB 0.22 ms
Input props
[
  "product" => App\Entity\Product\Product {#7310
    #id: 9957
    #code: "IEEE00003339"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751038699 {#7274
      date: 2025-06-27 17:38:19.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#7322
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 34837
        #name: "IEEE 1481:2009"
        #slug: "ieee-1481-2009-ieee00003339-241609"
        #description: """
          Revision Standard - Superseded.<br />\n
          Ways for integrated circuit designers to analyze chip timing and power consistently across a broad set of electric design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, this standard covers means by which EDA vendors can meet their application performance and capacity needs.<br />\n
          \t\t\t\t<br />\n
          The scope of this standard focuses on delay and power calculation for integrated circuit design with support for modeling logical behavior and signal integrity.<br />\n
          To improve the IEEE 1481-1999 standard system for integrated circuit designers to more accurately and more completely analyze semiconductor designs across EDA applications and for integrated circuit vendors to express logical behavior, signal integrity, delay, and power information only once per technology while<br />\n
          enabling sufficient EDA application accuracy.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Integrated Circuit (IC) Open Library Architecture (OLA)"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1585778400 {#7292
      date: 2020-04-02 00:00:00.0 Europe/Paris (+02:00)
    }
    -author: ""
    -publishedAt: DateTime @1268262000 {#7318
      date: 2010-03-11 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1481"
    -bookCollection: ""
    -pageCount: 658
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
]
Attributes
[]
Component
App\Twig\Components\ProductType {#93234
  +product: App\Entity\Product\Product {#7310
    #id: 9957
    #code: "IEEE00003339"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751038699 {#7274
      date: 2025-06-27 17:38:19.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#7322
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 34837
        #name: "IEEE 1481:2009"
        #slug: "ieee-1481-2009-ieee00003339-241609"
        #description: """
          Revision Standard - Superseded.<br />\n
          Ways for integrated circuit designers to analyze chip timing and power consistently across a broad set of electric design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, this standard covers means by which EDA vendors can meet their application performance and capacity needs.<br />\n
          \t\t\t\t<br />\n
          The scope of this standard focuses on delay and power calculation for integrated circuit design with support for modeling logical behavior and signal integrity.<br />\n
          To improve the IEEE 1481-1999 standard system for integrated circuit designers to more accurately and more completely analyze semiconductor designs across EDA applications and for integrated circuit vendors to express logical behavior, signal integrity, delay, and power information only once per technology while<br />\n
          enabling sufficient EDA application accuracy.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Integrated Circuit (IC) Open Library Architecture (OLA)"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1585778400 {#7292
      date: 2020-04-02 00:00:00.0 Europe/Paris (+02:00)
    }
    -author: ""
    -publishedAt: DateTime @1268262000 {#7318
      date: 2010-03-11 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1481"
    -bookCollection: ""
    -pageCount: 658
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +label: "Standard"
  -typeAttributeCode: "type"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductMostRecent App\Twig\Components\ProductMostRecent 202.0 MiB 0.65 ms
Input props
[
  "product" => App\Entity\Product\Product {#7310
    #id: 9957
    #code: "IEEE00003339"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751038699 {#7274
      date: 2025-06-27 17:38:19.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#7322
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 34837
        #name: "IEEE 1481:2009"
        #slug: "ieee-1481-2009-ieee00003339-241609"
        #description: """
          Revision Standard - Superseded.<br />\n
          Ways for integrated circuit designers to analyze chip timing and power consistently across a broad set of electric design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, this standard covers means by which EDA vendors can meet their application performance and capacity needs.<br />\n
          \t\t\t\t<br />\n
          The scope of this standard focuses on delay and power calculation for integrated circuit design with support for modeling logical behavior and signal integrity.<br />\n
          To improve the IEEE 1481-1999 standard system for integrated circuit designers to more accurately and more completely analyze semiconductor designs across EDA applications and for integrated circuit vendors to express logical behavior, signal integrity, delay, and power information only once per technology while<br />\n
          enabling sufficient EDA application accuracy.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Integrated Circuit (IC) Open Library Architecture (OLA)"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1585778400 {#7292
      date: 2020-04-02 00:00:00.0 Europe/Paris (+02:00)
    }
    -author: ""
    -publishedAt: DateTime @1268262000 {#7318
      date: 2010-03-11 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1481"
    -bookCollection: ""
    -pageCount: 658
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
]
Attributes
[]
Component
App\Twig\Components\ProductMostRecent {#93309
  +product: App\Entity\Product\Product {#7310
    #id: 9957
    #code: "IEEE00003339"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751038699 {#7274
      date: 2025-06-27 17:38:19.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#7322
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 34837
        #name: "IEEE 1481:2009"
        #slug: "ieee-1481-2009-ieee00003339-241609"
        #description: """
          Revision Standard - Superseded.<br />\n
          Ways for integrated circuit designers to analyze chip timing and power consistently across a broad set of electric design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, this standard covers means by which EDA vendors can meet their application performance and capacity needs.<br />\n
          \t\t\t\t<br />\n
          The scope of this standard focuses on delay and power calculation for integrated circuit design with support for modeling logical behavior and signal integrity.<br />\n
          To improve the IEEE 1481-1999 standard system for integrated circuit designers to more accurately and more completely analyze semiconductor designs across EDA applications and for integrated circuit vendors to express logical behavior, signal integrity, delay, and power information only once per technology while<br />\n
          enabling sufficient EDA application accuracy.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Integrated Circuit (IC) Open Library Architecture (OLA)"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1585778400 {#7292
      date: 2020-04-02 00:00:00.0 Europe/Paris (+02:00)
    }
    -author: ""
    -publishedAt: DateTime @1268262000 {#7318
      date: 2010-03-11 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1481"
    -bookCollection: ""
    -pageCount: 658
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +label: "Historical"
  +icon: "historical"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductState App\Twig\Components\ProductState 202.0 MiB 0.25 ms
Input props
[
  "product" => App\Entity\Product\Product {#106876
    #id: 9382
    #code: "IEEE00002200"
    #attributes: Doctrine\ORM\PersistentCollection {#106859 …}
    #variants: Doctrine\ORM\PersistentCollection {#106856 …}
    #options: Doctrine\ORM\PersistentCollection {#106852 …}
    #associations: Doctrine\ORM\PersistentCollection {#106854 …}
    #createdAt: DateTime @1751038218 {#106884
      date: 2025-06-27 17:30:18.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969444 {#106857
      date: 2025-07-31 15:44:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106870 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#106909
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106876}
        #id: 32537
        #name: "IEEE 1481:1999"
        #slug: "ieee-1481-1999-ieee00002200-241034"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          Ways for integrated circuit designers to analyze chip timing and power consistently across a broad set of electric design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, this standard covers means by which EDA vendors can meet their application performance and capacity needs.<br />\n
          \t\t\t\t<br />\n
          The scope of the DPCS standard is to make it possible for integrated circuit designers to analyze chip timing and power consistently across a broad set of EDA applications, for integrated circuit vendors to express timing and power information once (for a given technology), and for EDA vendors to meet their application performance and capacity needs. The intended use for this standard is IC timing and power. This standard may be applied to both unit logic cells supplied by the IC vendor and logical macros defined by the IC designer. Although this standard is written toward the integrated circuit supplier and EDA developer, its application applies equally well to representation of timing and power for designer-defined macros (or hierarchical design elements).<br />\n
          As feature sizes for chips shrink below 0.5<br />\n
          µ<br />\n
          m, interconnect delay effects outweigh those of the logic cells.<br />\n
          This means placement of cells and wire routing of the interconnects become as important a factor as the type<br />\n
          of cell drivers and receivers on the interconnect. As a result, EDA logic design applications (such as<br />\n
          synthesis) now need to interact closely with physical design applications (such as floorplanning and layout).<br />\n
          Applications that before could consider only simple delay and power models now need to deal with complex delay and power equations. The designer now needs EDA applications that can be directed to specific timing constraints, and provide consistent and accurate characterization of a chip’s timing and power before it is manufactured. Plus, due to the complexities of the delay and power equations, the integrated circuit vendor needs to have control of application calculations and not be restricted by unique characteristics of the broad set of applications demanded by the customers (or designers).
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106867 …}
    #channels: Doctrine\ORM\PersistentCollection {#106861 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106865 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106863 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106877 …}
    -apiLastModifiedAt: DateTime @1743289200 {#106844
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#106883
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @958082400 {#106882
      date: 2000-05-12 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1481"
    -bookCollection: ""
    -pageCount: 400
    -documents: Doctrine\ORM\PersistentCollection {#106874 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106872 …}
  }
  "showFullLabel" => "true"
]
Attributes
[
  "showFullLabel" => "true"
]
Component
App\Twig\Components\ProductState {#106892
  +product: App\Entity\Product\Product {#106876
    #id: 9382
    #code: "IEEE00002200"
    #attributes: Doctrine\ORM\PersistentCollection {#106859 …}
    #variants: Doctrine\ORM\PersistentCollection {#106856 …}
    #options: Doctrine\ORM\PersistentCollection {#106852 …}
    #associations: Doctrine\ORM\PersistentCollection {#106854 …}
    #createdAt: DateTime @1751038218 {#106884
      date: 2025-06-27 17:30:18.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969444 {#106857
      date: 2025-07-31 15:44:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106870 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#106909
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106876}
        #id: 32537
        #name: "IEEE 1481:1999"
        #slug: "ieee-1481-1999-ieee00002200-241034"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          Ways for integrated circuit designers to analyze chip timing and power consistently across a broad set of electric design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, this standard covers means by which EDA vendors can meet their application performance and capacity needs.<br />\n
          \t\t\t\t<br />\n
          The scope of the DPCS standard is to make it possible for integrated circuit designers to analyze chip timing and power consistently across a broad set of EDA applications, for integrated circuit vendors to express timing and power information once (for a given technology), and for EDA vendors to meet their application performance and capacity needs. The intended use for this standard is IC timing and power. This standard may be applied to both unit logic cells supplied by the IC vendor and logical macros defined by the IC designer. Although this standard is written toward the integrated circuit supplier and EDA developer, its application applies equally well to representation of timing and power for designer-defined macros (or hierarchical design elements).<br />\n
          As feature sizes for chips shrink below 0.5<br />\n
          µ<br />\n
          m, interconnect delay effects outweigh those of the logic cells.<br />\n
          This means placement of cells and wire routing of the interconnects become as important a factor as the type<br />\n
          of cell drivers and receivers on the interconnect. As a result, EDA logic design applications (such as<br />\n
          synthesis) now need to interact closely with physical design applications (such as floorplanning and layout).<br />\n
          Applications that before could consider only simple delay and power models now need to deal with complex delay and power equations. The designer now needs EDA applications that can be directed to specific timing constraints, and provide consistent and accurate characterization of a chip’s timing and power before it is manufactured. Plus, due to the complexities of the delay and power equations, the integrated circuit vendor needs to have control of application calculations and not be restricted by unique characteristics of the broad set of applications demanded by the customers (or designers).
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106867 …}
    #channels: Doctrine\ORM\PersistentCollection {#106861 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106865 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106863 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106877 …}
    -apiLastModifiedAt: DateTime @1743289200 {#106844
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#106883
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @958082400 {#106882
      date: 2000-05-12 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1481"
    -bookCollection: ""
    -pageCount: 400
    -documents: Doctrine\ORM\PersistentCollection {#106874 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106872 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductMostRecent App\Twig\Components\ProductMostRecent 202.0 MiB 0.73 ms
Input props
[
  "product" => App\Entity\Product\Product {#106876
    #id: 9382
    #code: "IEEE00002200"
    #attributes: Doctrine\ORM\PersistentCollection {#106859 …}
    #variants: Doctrine\ORM\PersistentCollection {#106856 …}
    #options: Doctrine\ORM\PersistentCollection {#106852 …}
    #associations: Doctrine\ORM\PersistentCollection {#106854 …}
    #createdAt: DateTime @1751038218 {#106884
      date: 2025-06-27 17:30:18.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969444 {#106857
      date: 2025-07-31 15:44:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106870 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#106909
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106876}
        #id: 32537
        #name: "IEEE 1481:1999"
        #slug: "ieee-1481-1999-ieee00002200-241034"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          Ways for integrated circuit designers to analyze chip timing and power consistently across a broad set of electric design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, this standard covers means by which EDA vendors can meet their application performance and capacity needs.<br />\n
          \t\t\t\t<br />\n
          The scope of the DPCS standard is to make it possible for integrated circuit designers to analyze chip timing and power consistently across a broad set of EDA applications, for integrated circuit vendors to express timing and power information once (for a given technology), and for EDA vendors to meet their application performance and capacity needs. The intended use for this standard is IC timing and power. This standard may be applied to both unit logic cells supplied by the IC vendor and logical macros defined by the IC designer. Although this standard is written toward the integrated circuit supplier and EDA developer, its application applies equally well to representation of timing and power for designer-defined macros (or hierarchical design elements).<br />\n
          As feature sizes for chips shrink below 0.5<br />\n
          µ<br />\n
          m, interconnect delay effects outweigh those of the logic cells.<br />\n
          This means placement of cells and wire routing of the interconnects become as important a factor as the type<br />\n
          of cell drivers and receivers on the interconnect. As a result, EDA logic design applications (such as<br />\n
          synthesis) now need to interact closely with physical design applications (such as floorplanning and layout).<br />\n
          Applications that before could consider only simple delay and power models now need to deal with complex delay and power equations. The designer now needs EDA applications that can be directed to specific timing constraints, and provide consistent and accurate characterization of a chip’s timing and power before it is manufactured. Plus, due to the complexities of the delay and power equations, the integrated circuit vendor needs to have control of application calculations and not be restricted by unique characteristics of the broad set of applications demanded by the customers (or designers).
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106867 …}
    #channels: Doctrine\ORM\PersistentCollection {#106861 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106865 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106863 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106877 …}
    -apiLastModifiedAt: DateTime @1743289200 {#106844
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#106883
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @958082400 {#106882
      date: 2000-05-12 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1481"
    -bookCollection: ""
    -pageCount: 400
    -documents: Doctrine\ORM\PersistentCollection {#106874 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106872 …}
  }
]
Attributes
[]
Component
App\Twig\Components\ProductMostRecent {#106991
  +product: App\Entity\Product\Product {#106876
    #id: 9382
    #code: "IEEE00002200"
    #attributes: Doctrine\ORM\PersistentCollection {#106859 …}
    #variants: Doctrine\ORM\PersistentCollection {#106856 …}
    #options: Doctrine\ORM\PersistentCollection {#106852 …}
    #associations: Doctrine\ORM\PersistentCollection {#106854 …}
    #createdAt: DateTime @1751038218 {#106884
      date: 2025-06-27 17:30:18.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969444 {#106857
      date: 2025-07-31 15:44:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106870 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#106909
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106876}
        #id: 32537
        #name: "IEEE 1481:1999"
        #slug: "ieee-1481-1999-ieee00002200-241034"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          Ways for integrated circuit designers to analyze chip timing and power consistently across a broad set of electric design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, this standard covers means by which EDA vendors can meet their application performance and capacity needs.<br />\n
          \t\t\t\t<br />\n
          The scope of the DPCS standard is to make it possible for integrated circuit designers to analyze chip timing and power consistently across a broad set of EDA applications, for integrated circuit vendors to express timing and power information once (for a given technology), and for EDA vendors to meet their application performance and capacity needs. The intended use for this standard is IC timing and power. This standard may be applied to both unit logic cells supplied by the IC vendor and logical macros defined by the IC designer. Although this standard is written toward the integrated circuit supplier and EDA developer, its application applies equally well to representation of timing and power for designer-defined macros (or hierarchical design elements).<br />\n
          As feature sizes for chips shrink below 0.5<br />\n
          µ<br />\n
          m, interconnect delay effects outweigh those of the logic cells.<br />\n
          This means placement of cells and wire routing of the interconnects become as important a factor as the type<br />\n
          of cell drivers and receivers on the interconnect. As a result, EDA logic design applications (such as<br />\n
          synthesis) now need to interact closely with physical design applications (such as floorplanning and layout).<br />\n
          Applications that before could consider only simple delay and power models now need to deal with complex delay and power equations. The designer now needs EDA applications that can be directed to specific timing constraints, and provide consistent and accurate characterization of a chip’s timing and power before it is manufactured. Plus, due to the complexities of the delay and power equations, the integrated circuit vendor needs to have control of application calculations and not be restricted by unique characteristics of the broad set of applications demanded by the customers (or designers).
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106867 …}
    #channels: Doctrine\ORM\PersistentCollection {#106861 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106865 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106863 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106877 …}
    -apiLastModifiedAt: DateTime @1743289200 {#106844
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#106883
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @958082400 {#106882
      date: 2000-05-12 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1481"
    -bookCollection: ""
    -pageCount: 400
    -documents: Doctrine\ORM\PersistentCollection {#106874 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106872 …}
  }
  +label: "Historical"
  +icon: "historical"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductState App\Twig\Components\ProductState 202.0 MiB 0.22 ms
Input props
[
  "product" => App\Entity\Product\Product {#93736
    #id: 12413
    #code: "IEEE00007651"
    #attributes: Doctrine\ORM\PersistentCollection {#93718 …}
    #variants: Doctrine\ORM\PersistentCollection {#93715 …}
    #options: Doctrine\ORM\PersistentCollection {#93711 …}
    #associations: Doctrine\ORM\PersistentCollection {#93713 …}
    #createdAt: DateTime @1751040415 {#93744
      date: 2025-06-27 18:06:55.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754608621 {#93723
      date: 2025-08-08 01:17:01.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#93729 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#93764
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#93736}
        #id: 44661
        #name: "IEEE 1481:2019"
        #slug: "ieee-1481-2019-ieee00007651-244066"
        #description: """
          Revision Standard - Active.<br />\n
          Ways for integrated circuit designers to analyze chip timing and power consistently across a broad set of electric design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, the means by which EDA vendors can meet their application performance and capacity needs are discussed.<br />\n
          \t\t\t\t<br />\n
          The scope of this standard focuses on delay and power calculation for integrated circuit design with support for modeling logical behavior and signal integrity.<br />\n
          To improve the IEEE Std 1481(TM)-1999 system for integrated circuit designers to more accurately and more completely analyze semiconductor designs across EDA applications and for integrated circuit vendors to express logical behavior, signal integrity, delay, and power information only once per technology while enabling sufficient EDA application accuracy.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Integrated Circuit (IC) Open Library Architecture (OLA)"
        -notes: "Active"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#93727 …}
    #channels: Doctrine\ORM\PersistentCollection {#93720 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#93725 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#93722 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#93737 …}
    -apiLastModifiedAt: DateTime @1754517600 {#93707
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1636412400 {#93743
      date: 2021-11-09 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1584054000 {#93742
      date: 2020-03-13 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1481"
    -bookCollection: ""
    -pageCount: 641
    -documents: Doctrine\ORM\PersistentCollection {#93733 …}
    -favorites: Doctrine\ORM\PersistentCollection {#93731 …}
  }
  "showFullLabel" => "true"
]
Attributes
[
  "showFullLabel" => "true"
]
Component
App\Twig\Components\ProductState {#113613
  +product: App\Entity\Product\Product {#93736
    #id: 12413
    #code: "IEEE00007651"
    #attributes: Doctrine\ORM\PersistentCollection {#93718 …}
    #variants: Doctrine\ORM\PersistentCollection {#93715 …}
    #options: Doctrine\ORM\PersistentCollection {#93711 …}
    #associations: Doctrine\ORM\PersistentCollection {#93713 …}
    #createdAt: DateTime @1751040415 {#93744
      date: 2025-06-27 18:06:55.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754608621 {#93723
      date: 2025-08-08 01:17:01.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#93729 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#93764
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#93736}
        #id: 44661
        #name: "IEEE 1481:2019"
        #slug: "ieee-1481-2019-ieee00007651-244066"
        #description: """
          Revision Standard - Active.<br />\n
          Ways for integrated circuit designers to analyze chip timing and power consistently across a broad set of electric design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, the means by which EDA vendors can meet their application performance and capacity needs are discussed.<br />\n
          \t\t\t\t<br />\n
          The scope of this standard focuses on delay and power calculation for integrated circuit design with support for modeling logical behavior and signal integrity.<br />\n
          To improve the IEEE Std 1481(TM)-1999 system for integrated circuit designers to more accurately and more completely analyze semiconductor designs across EDA applications and for integrated circuit vendors to express logical behavior, signal integrity, delay, and power information only once per technology while enabling sufficient EDA application accuracy.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Integrated Circuit (IC) Open Library Architecture (OLA)"
        -notes: "Active"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#93727 …}
    #channels: Doctrine\ORM\PersistentCollection {#93720 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#93725 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#93722 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#93737 …}
    -apiLastModifiedAt: DateTime @1754517600 {#93707
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1636412400 {#93743
      date: 2021-11-09 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1584054000 {#93742
      date: 2020-03-13 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1481"
    -bookCollection: ""
    -pageCount: 641
    -documents: Doctrine\ORM\PersistentCollection {#93733 …}
    -favorites: Doctrine\ORM\PersistentCollection {#93731 …}
  }
  +appearance: "state-active"
  +labels: [
    "Active"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductMostRecent App\Twig\Components\ProductMostRecent 202.0 MiB 0.71 ms
Input props
[
  "product" => App\Entity\Product\Product {#93736
    #id: 12413
    #code: "IEEE00007651"
    #attributes: Doctrine\ORM\PersistentCollection {#93718 …}
    #variants: Doctrine\ORM\PersistentCollection {#93715 …}
    #options: Doctrine\ORM\PersistentCollection {#93711 …}
    #associations: Doctrine\ORM\PersistentCollection {#93713 …}
    #createdAt: DateTime @1751040415 {#93744
      date: 2025-06-27 18:06:55.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754608621 {#93723
      date: 2025-08-08 01:17:01.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#93729 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#93764
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#93736}
        #id: 44661
        #name: "IEEE 1481:2019"
        #slug: "ieee-1481-2019-ieee00007651-244066"
        #description: """
          Revision Standard - Active.<br />\n
          Ways for integrated circuit designers to analyze chip timing and power consistently across a broad set of electric design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, the means by which EDA vendors can meet their application performance and capacity needs are discussed.<br />\n
          \t\t\t\t<br />\n
          The scope of this standard focuses on delay and power calculation for integrated circuit design with support for modeling logical behavior and signal integrity.<br />\n
          To improve the IEEE Std 1481(TM)-1999 system for integrated circuit designers to more accurately and more completely analyze semiconductor designs across EDA applications and for integrated circuit vendors to express logical behavior, signal integrity, delay, and power information only once per technology while enabling sufficient EDA application accuracy.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Integrated Circuit (IC) Open Library Architecture (OLA)"
        -notes: "Active"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#93727 …}
    #channels: Doctrine\ORM\PersistentCollection {#93720 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#93725 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#93722 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#93737 …}
    -apiLastModifiedAt: DateTime @1754517600 {#93707
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1636412400 {#93743
      date: 2021-11-09 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1584054000 {#93742
      date: 2020-03-13 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1481"
    -bookCollection: ""
    -pageCount: 641
    -documents: Doctrine\ORM\PersistentCollection {#93733 …}
    -favorites: Doctrine\ORM\PersistentCollection {#93731 …}
  }
]
Attributes
[]
Component
App\Twig\Components\ProductMostRecent {#113680
  +product: App\Entity\Product\Product {#93736
    #id: 12413
    #code: "IEEE00007651"
    #attributes: Doctrine\ORM\PersistentCollection {#93718 …}
    #variants: Doctrine\ORM\PersistentCollection {#93715 …}
    #options: Doctrine\ORM\PersistentCollection {#93711 …}
    #associations: Doctrine\ORM\PersistentCollection {#93713 …}
    #createdAt: DateTime @1751040415 {#93744
      date: 2025-06-27 18:06:55.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754608621 {#93723
      date: 2025-08-08 01:17:01.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#93729 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#93764
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#93736}
        #id: 44661
        #name: "IEEE 1481:2019"
        #slug: "ieee-1481-2019-ieee00007651-244066"
        #description: """
          Revision Standard - Active.<br />\n
          Ways for integrated circuit designers to analyze chip timing and power consistently across a broad set of electric design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, the means by which EDA vendors can meet their application performance and capacity needs are discussed.<br />\n
          \t\t\t\t<br />\n
          The scope of this standard focuses on delay and power calculation for integrated circuit design with support for modeling logical behavior and signal integrity.<br />\n
          To improve the IEEE Std 1481(TM)-1999 system for integrated circuit designers to more accurately and more completely analyze semiconductor designs across EDA applications and for integrated circuit vendors to express logical behavior, signal integrity, delay, and power information only once per technology while enabling sufficient EDA application accuracy.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Integrated Circuit (IC) Open Library Architecture (OLA)"
        -notes: "Active"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#93727 …}
    #channels: Doctrine\ORM\PersistentCollection {#93720 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#93725 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#93722 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#93737 …}
    -apiLastModifiedAt: DateTime @1754517600 {#93707
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1636412400 {#93743
      date: 2021-11-09 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1584054000 {#93742
      date: 2020-03-13 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1481"
    -bookCollection: ""
    -pageCount: 641
    -documents: Doctrine\ORM\PersistentCollection {#93733 …}
    -favorites: Doctrine\ORM\PersistentCollection {#93731 …}
  }
  +label: "Most Recent"
  +icon: "check-xs"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductState App\Twig\Components\ProductState 202.0 MiB 0.18 ms
Input props
[
  "product" => App\Entity\Product\Product {#7310
    #id: 9957
    #code: "IEEE00003339"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751038699 {#7274
      date: 2025-06-27 17:38:19.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#7322
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 34837
        #name: "IEEE 1481:2009"
        #slug: "ieee-1481-2009-ieee00003339-241609"
        #description: """
          Revision Standard - Superseded.<br />\n
          Ways for integrated circuit designers to analyze chip timing and power consistently across a broad set of electric design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, this standard covers means by which EDA vendors can meet their application performance and capacity needs.<br />\n
          \t\t\t\t<br />\n
          The scope of this standard focuses on delay and power calculation for integrated circuit design with support for modeling logical behavior and signal integrity.<br />\n
          To improve the IEEE 1481-1999 standard system for integrated circuit designers to more accurately and more completely analyze semiconductor designs across EDA applications and for integrated circuit vendors to express logical behavior, signal integrity, delay, and power information only once per technology while<br />\n
          enabling sufficient EDA application accuracy.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Integrated Circuit (IC) Open Library Architecture (OLA)"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1585778400 {#7292
      date: 2020-04-02 00:00:00.0 Europe/Paris (+02:00)
    }
    -author: ""
    -publishedAt: DateTime @1268262000 {#7318
      date: 2010-03-11 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1481"
    -bookCollection: ""
    -pageCount: 658
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  "showFullLabel" => "true"
]
Attributes
[
  "showFullLabel" => "true"
]
Component
App\Twig\Components\ProductState {#113745
  +product: App\Entity\Product\Product {#7310
    #id: 9957
    #code: "IEEE00003339"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751038699 {#7274
      date: 2025-06-27 17:38:19.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#7322
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 34837
        #name: "IEEE 1481:2009"
        #slug: "ieee-1481-2009-ieee00003339-241609"
        #description: """
          Revision Standard - Superseded.<br />\n
          Ways for integrated circuit designers to analyze chip timing and power consistently across a broad set of electric design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, this standard covers means by which EDA vendors can meet their application performance and capacity needs.<br />\n
          \t\t\t\t<br />\n
          The scope of this standard focuses on delay and power calculation for integrated circuit design with support for modeling logical behavior and signal integrity.<br />\n
          To improve the IEEE 1481-1999 standard system for integrated circuit designers to more accurately and more completely analyze semiconductor designs across EDA applications and for integrated circuit vendors to express logical behavior, signal integrity, delay, and power information only once per technology while<br />\n
          enabling sufficient EDA application accuracy.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Integrated Circuit (IC) Open Library Architecture (OLA)"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1585778400 {#7292
      date: 2020-04-02 00:00:00.0 Europe/Paris (+02:00)
    }
    -author: ""
    -publishedAt: DateTime @1268262000 {#7318
      date: 2010-03-11 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1481"
    -bookCollection: ""
    -pageCount: 658
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductMostRecent App\Twig\Components\ProductMostRecent 202.0 MiB 0.61 ms
Input props
[
  "product" => App\Entity\Product\Product {#7310
    #id: 9957
    #code: "IEEE00003339"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751038699 {#7274
      date: 2025-06-27 17:38:19.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#7322
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 34837
        #name: "IEEE 1481:2009"
        #slug: "ieee-1481-2009-ieee00003339-241609"
        #description: """
          Revision Standard - Superseded.<br />\n
          Ways for integrated circuit designers to analyze chip timing and power consistently across a broad set of electric design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, this standard covers means by which EDA vendors can meet their application performance and capacity needs.<br />\n
          \t\t\t\t<br />\n
          The scope of this standard focuses on delay and power calculation for integrated circuit design with support for modeling logical behavior and signal integrity.<br />\n
          To improve the IEEE 1481-1999 standard system for integrated circuit designers to more accurately and more completely analyze semiconductor designs across EDA applications and for integrated circuit vendors to express logical behavior, signal integrity, delay, and power information only once per technology while<br />\n
          enabling sufficient EDA application accuracy.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Integrated Circuit (IC) Open Library Architecture (OLA)"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1585778400 {#7292
      date: 2020-04-02 00:00:00.0 Europe/Paris (+02:00)
    }
    -author: ""
    -publishedAt: DateTime @1268262000 {#7318
      date: 2010-03-11 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1481"
    -bookCollection: ""
    -pageCount: 658
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
]
Attributes
[]
Component
App\Twig\Components\ProductMostRecent {#113772
  +product: App\Entity\Product\Product {#7310
    #id: 9957
    #code: "IEEE00003339"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751038699 {#7274
      date: 2025-06-27 17:38:19.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#7322
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 34837
        #name: "IEEE 1481:2009"
        #slug: "ieee-1481-2009-ieee00003339-241609"
        #description: """
          Revision Standard - Superseded.<br />\n
          Ways for integrated circuit designers to analyze chip timing and power consistently across a broad set of electric design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, this standard covers means by which EDA vendors can meet their application performance and capacity needs.<br />\n
          \t\t\t\t<br />\n
          The scope of this standard focuses on delay and power calculation for integrated circuit design with support for modeling logical behavior and signal integrity.<br />\n
          To improve the IEEE 1481-1999 standard system for integrated circuit designers to more accurately and more completely analyze semiconductor designs across EDA applications and for integrated circuit vendors to express logical behavior, signal integrity, delay, and power information only once per technology while<br />\n
          enabling sufficient EDA application accuracy.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Integrated Circuit (IC) Open Library Architecture (OLA)"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1585778400 {#7292
      date: 2020-04-02 00:00:00.0 Europe/Paris (+02:00)
    }
    -author: ""
    -publishedAt: DateTime @1268262000 {#7318
      date: 2010-03-11 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1481"
    -bookCollection: ""
    -pageCount: 658
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +label: "Historical"
  +icon: "historical"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductState App\Twig\Components\ProductState 202.0 MiB 0.23 ms
Input props
[
  "product" => App\Entity\Product\Product {#106876
    #id: 9382
    #code: "IEEE00002200"
    #attributes: Doctrine\ORM\PersistentCollection {#106859 …}
    #variants: Doctrine\ORM\PersistentCollection {#106856 …}
    #options: Doctrine\ORM\PersistentCollection {#106852 …}
    #associations: Doctrine\ORM\PersistentCollection {#106854 …}
    #createdAt: DateTime @1751038218 {#106884
      date: 2025-06-27 17:30:18.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969444 {#106857
      date: 2025-07-31 15:44:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106870 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#106909
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106876}
        #id: 32537
        #name: "IEEE 1481:1999"
        #slug: "ieee-1481-1999-ieee00002200-241034"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          Ways for integrated circuit designers to analyze chip timing and power consistently across a broad set of electric design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, this standard covers means by which EDA vendors can meet their application performance and capacity needs.<br />\n
          \t\t\t\t<br />\n
          The scope of the DPCS standard is to make it possible for integrated circuit designers to analyze chip timing and power consistently across a broad set of EDA applications, for integrated circuit vendors to express timing and power information once (for a given technology), and for EDA vendors to meet their application performance and capacity needs. The intended use for this standard is IC timing and power. This standard may be applied to both unit logic cells supplied by the IC vendor and logical macros defined by the IC designer. Although this standard is written toward the integrated circuit supplier and EDA developer, its application applies equally well to representation of timing and power for designer-defined macros (or hierarchical design elements).<br />\n
          As feature sizes for chips shrink below 0.5<br />\n
          µ<br />\n
          m, interconnect delay effects outweigh those of the logic cells.<br />\n
          This means placement of cells and wire routing of the interconnects become as important a factor as the type<br />\n
          of cell drivers and receivers on the interconnect. As a result, EDA logic design applications (such as<br />\n
          synthesis) now need to interact closely with physical design applications (such as floorplanning and layout).<br />\n
          Applications that before could consider only simple delay and power models now need to deal with complex delay and power equations. The designer now needs EDA applications that can be directed to specific timing constraints, and provide consistent and accurate characterization of a chip’s timing and power before it is manufactured. Plus, due to the complexities of the delay and power equations, the integrated circuit vendor needs to have control of application calculations and not be restricted by unique characteristics of the broad set of applications demanded by the customers (or designers).
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106867 …}
    #channels: Doctrine\ORM\PersistentCollection {#106861 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106865 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106863 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106877 …}
    -apiLastModifiedAt: DateTime @1743289200 {#106844
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#106883
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @958082400 {#106882
      date: 2000-05-12 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1481"
    -bookCollection: ""
    -pageCount: 400
    -documents: Doctrine\ORM\PersistentCollection {#106874 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106872 …}
  }
  "showFullLabel" => "true"
]
Attributes
[
  "showFullLabel" => "true"
]
Component
App\Twig\Components\ProductState {#113836
  +product: App\Entity\Product\Product {#106876
    #id: 9382
    #code: "IEEE00002200"
    #attributes: Doctrine\ORM\PersistentCollection {#106859 …}
    #variants: Doctrine\ORM\PersistentCollection {#106856 …}
    #options: Doctrine\ORM\PersistentCollection {#106852 …}
    #associations: Doctrine\ORM\PersistentCollection {#106854 …}
    #createdAt: DateTime @1751038218 {#106884
      date: 2025-06-27 17:30:18.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969444 {#106857
      date: 2025-07-31 15:44:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106870 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#106909
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106876}
        #id: 32537
        #name: "IEEE 1481:1999"
        #slug: "ieee-1481-1999-ieee00002200-241034"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          Ways for integrated circuit designers to analyze chip timing and power consistently across a broad set of electric design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, this standard covers means by which EDA vendors can meet their application performance and capacity needs.<br />\n
          \t\t\t\t<br />\n
          The scope of the DPCS standard is to make it possible for integrated circuit designers to analyze chip timing and power consistently across a broad set of EDA applications, for integrated circuit vendors to express timing and power information once (for a given technology), and for EDA vendors to meet their application performance and capacity needs. The intended use for this standard is IC timing and power. This standard may be applied to both unit logic cells supplied by the IC vendor and logical macros defined by the IC designer. Although this standard is written toward the integrated circuit supplier and EDA developer, its application applies equally well to representation of timing and power for designer-defined macros (or hierarchical design elements).<br />\n
          As feature sizes for chips shrink below 0.5<br />\n
          µ<br />\n
          m, interconnect delay effects outweigh those of the logic cells.<br />\n
          This means placement of cells and wire routing of the interconnects become as important a factor as the type<br />\n
          of cell drivers and receivers on the interconnect. As a result, EDA logic design applications (such as<br />\n
          synthesis) now need to interact closely with physical design applications (such as floorplanning and layout).<br />\n
          Applications that before could consider only simple delay and power models now need to deal with complex delay and power equations. The designer now needs EDA applications that can be directed to specific timing constraints, and provide consistent and accurate characterization of a chip’s timing and power before it is manufactured. Plus, due to the complexities of the delay and power equations, the integrated circuit vendor needs to have control of application calculations and not be restricted by unique characteristics of the broad set of applications demanded by the customers (or designers).
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106867 …}
    #channels: Doctrine\ORM\PersistentCollection {#106861 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106865 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106863 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106877 …}
    -apiLastModifiedAt: DateTime @1743289200 {#106844
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#106883
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @958082400 {#106882
      date: 2000-05-12 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1481"
    -bookCollection: ""
    -pageCount: 400
    -documents: Doctrine\ORM\PersistentCollection {#106874 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106872 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductMostRecent App\Twig\Components\ProductMostRecent 202.0 MiB 0.62 ms
Input props
[
  "product" => App\Entity\Product\Product {#106876
    #id: 9382
    #code: "IEEE00002200"
    #attributes: Doctrine\ORM\PersistentCollection {#106859 …}
    #variants: Doctrine\ORM\PersistentCollection {#106856 …}
    #options: Doctrine\ORM\PersistentCollection {#106852 …}
    #associations: Doctrine\ORM\PersistentCollection {#106854 …}
    #createdAt: DateTime @1751038218 {#106884
      date: 2025-06-27 17:30:18.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969444 {#106857
      date: 2025-07-31 15:44:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106870 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#106909
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106876}
        #id: 32537
        #name: "IEEE 1481:1999"
        #slug: "ieee-1481-1999-ieee00002200-241034"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          Ways for integrated circuit designers to analyze chip timing and power consistently across a broad set of electric design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, this standard covers means by which EDA vendors can meet their application performance and capacity needs.<br />\n
          \t\t\t\t<br />\n
          The scope of the DPCS standard is to make it possible for integrated circuit designers to analyze chip timing and power consistently across a broad set of EDA applications, for integrated circuit vendors to express timing and power information once (for a given technology), and for EDA vendors to meet their application performance and capacity needs. The intended use for this standard is IC timing and power. This standard may be applied to both unit logic cells supplied by the IC vendor and logical macros defined by the IC designer. Although this standard is written toward the integrated circuit supplier and EDA developer, its application applies equally well to representation of timing and power for designer-defined macros (or hierarchical design elements).<br />\n
          As feature sizes for chips shrink below 0.5<br />\n
          µ<br />\n
          m, interconnect delay effects outweigh those of the logic cells.<br />\n
          This means placement of cells and wire routing of the interconnects become as important a factor as the type<br />\n
          of cell drivers and receivers on the interconnect. As a result, EDA logic design applications (such as<br />\n
          synthesis) now need to interact closely with physical design applications (such as floorplanning and layout).<br />\n
          Applications that before could consider only simple delay and power models now need to deal with complex delay and power equations. The designer now needs EDA applications that can be directed to specific timing constraints, and provide consistent and accurate characterization of a chip’s timing and power before it is manufactured. Plus, due to the complexities of the delay and power equations, the integrated circuit vendor needs to have control of application calculations and not be restricted by unique characteristics of the broad set of applications demanded by the customers (or designers).
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106867 …}
    #channels: Doctrine\ORM\PersistentCollection {#106861 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106865 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106863 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106877 …}
    -apiLastModifiedAt: DateTime @1743289200 {#106844
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#106883
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @958082400 {#106882
      date: 2000-05-12 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1481"
    -bookCollection: ""
    -pageCount: 400
    -documents: Doctrine\ORM\PersistentCollection {#106874 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106872 …}
  }
]
Attributes
[]
Component
App\Twig\Components\ProductMostRecent {#113863
  +product: App\Entity\Product\Product {#106876
    #id: 9382
    #code: "IEEE00002200"
    #attributes: Doctrine\ORM\PersistentCollection {#106859 …}
    #variants: Doctrine\ORM\PersistentCollection {#106856 …}
    #options: Doctrine\ORM\PersistentCollection {#106852 …}
    #associations: Doctrine\ORM\PersistentCollection {#106854 …}
    #createdAt: DateTime @1751038218 {#106884
      date: 2025-06-27 17:30:18.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969444 {#106857
      date: 2025-07-31 15:44:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106870 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#106909
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106876}
        #id: 32537
        #name: "IEEE 1481:1999"
        #slug: "ieee-1481-1999-ieee00002200-241034"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          Ways for integrated circuit designers to analyze chip timing and power consistently across a broad set of electric design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, this standard covers means by which EDA vendors can meet their application performance and capacity needs.<br />\n
          \t\t\t\t<br />\n
          The scope of the DPCS standard is to make it possible for integrated circuit designers to analyze chip timing and power consistently across a broad set of EDA applications, for integrated circuit vendors to express timing and power information once (for a given technology), and for EDA vendors to meet their application performance and capacity needs. The intended use for this standard is IC timing and power. This standard may be applied to both unit logic cells supplied by the IC vendor and logical macros defined by the IC designer. Although this standard is written toward the integrated circuit supplier and EDA developer, its application applies equally well to representation of timing and power for designer-defined macros (or hierarchical design elements).<br />\n
          As feature sizes for chips shrink below 0.5<br />\n
          µ<br />\n
          m, interconnect delay effects outweigh those of the logic cells.<br />\n
          This means placement of cells and wire routing of the interconnects become as important a factor as the type<br />\n
          of cell drivers and receivers on the interconnect. As a result, EDA logic design applications (such as<br />\n
          synthesis) now need to interact closely with physical design applications (such as floorplanning and layout).<br />\n
          Applications that before could consider only simple delay and power models now need to deal with complex delay and power equations. The designer now needs EDA applications that can be directed to specific timing constraints, and provide consistent and accurate characterization of a chip’s timing and power before it is manufactured. Plus, due to the complexities of the delay and power equations, the integrated circuit vendor needs to have control of application calculations and not be restricted by unique characteristics of the broad set of applications demanded by the customers (or designers).
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106867 …}
    #channels: Doctrine\ORM\PersistentCollection {#106861 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106865 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106863 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106877 …}
    -apiLastModifiedAt: DateTime @1743289200 {#106844
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#106883
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @958082400 {#106882
      date: 2000-05-12 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1481"
    -bookCollection: ""
    -pageCount: 400
    -documents: Doctrine\ORM\PersistentCollection {#106874 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106872 …}
  }
  +label: "Historical"
  +icon: "historical"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}