GET https://dev.normadoc.fr/products/ieee-1076-4-2000-ieee00001616-240750

Components

3 Twig Components
9 Render Count
4 ms Render Time
80.0 MiB Memory Usage

Components

Name Metadata Render Count Render Time
ProductState
"App\Twig\Components\ProductState"
components/ProductState.html.twig
4 0.86ms
ProductMostRecent
"App\Twig\Components\ProductMostRecent"
components/ProductMostRecent.html.twig
4 2.72ms
ProductType
"App\Twig\Components\ProductType"
components/ProductType.html.twig
1 0.22ms

Render calls

ProductState App\Twig\Components\ProductState 68.0 MiB 0.30 ms
Input props
[
  "product" => App\Entity\Product\Product {#7311
    #id: 9098
    #code: "IEEE00001616"
    #attributes: Doctrine\ORM\PersistentCollection {#7701 …}
    #variants: Doctrine\ORM\PersistentCollection {#7744 …}
    #options: Doctrine\ORM\PersistentCollection {#7916 …}
    #associations: Doctrine\ORM\PersistentCollection {#7900 …}
    #createdAt: DateTime @1751037969 {#7274
      date: 2025-06-27 17:26:09.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754606304 {#7322
      date: 2025-08-08 00:38:24.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7922 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7921
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7311}
        #id: 31401
        #name: "IEEE 1076.4:2000"
        #slug: "ieee-1076-4-2000-ieee00001616-240750"
        #description: """
          Revision Standard - Inactive-Withdrawn.<br />\n
          The VITAL (VHDL Initiative Towards ASIC Libraries)ASIC Modeling Specification is defined in this standard.This modeling specification defines a methodology which promotes the development of highly accurate, efficient simulation models for ASIC (Application-Specific Integrated Circuit)components in VHDL.<br />\n
          \t\t\t\t<br />\n
          To provide a standard method of modeling ASICs in VHDL. This method is aimed at providing efficient, accurate, and tool independent simulation suitable for large chip-level designs typical of those which are based on ASICs.<br />\n
          Current industry methods for designing complex chip-level designs rely on proprietary solutions which are based on specific commercial tools. This standard provides an effective means of performing those designs in a standard, non-proprietary manner that is independent of specific tools. This promotes cost effective design flows and promotes healthy levels of competition in the electronic design industry. This standard builds on the work of IEEE 1076 VHDL which is a standard hardware description language designed to allow such tool independent electronic design.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification"
        -notes: "Inactive-Withdrawn"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …}
    #channels: Doctrine\ORM\PersistentCollection {#7628 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7613 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7645 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1001628000 {#7318
      date: 2001-09-28 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: DateTime @1232924400 {#7316
      date: 2009-01-26 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1076.4"
    -bookCollection: ""
    -pageCount: 448
    -documents: Doctrine\ORM\PersistentCollection {#7465 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7500 …}
  }
  "showFullLabel" => "true"
]
Attributes
[
  "showFullLabel" => "true"
]
Component
App\Twig\Components\ProductState {#93008
  +product: App\Entity\Product\Product {#7311
    #id: 9098
    #code: "IEEE00001616"
    #attributes: Doctrine\ORM\PersistentCollection {#7701 …}
    #variants: Doctrine\ORM\PersistentCollection {#7744 …}
    #options: Doctrine\ORM\PersistentCollection {#7916 …}
    #associations: Doctrine\ORM\PersistentCollection {#7900 …}
    #createdAt: DateTime @1751037969 {#7274
      date: 2025-06-27 17:26:09.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754606304 {#7322
      date: 2025-08-08 00:38:24.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7922 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7921
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7311}
        #id: 31401
        #name: "IEEE 1076.4:2000"
        #slug: "ieee-1076-4-2000-ieee00001616-240750"
        #description: """
          Revision Standard - Inactive-Withdrawn.<br />\n
          The VITAL (VHDL Initiative Towards ASIC Libraries)ASIC Modeling Specification is defined in this standard.This modeling specification defines a methodology which promotes the development of highly accurate, efficient simulation models for ASIC (Application-Specific Integrated Circuit)components in VHDL.<br />\n
          \t\t\t\t<br />\n
          To provide a standard method of modeling ASICs in VHDL. This method is aimed at providing efficient, accurate, and tool independent simulation suitable for large chip-level designs typical of those which are based on ASICs.<br />\n
          Current industry methods for designing complex chip-level designs rely on proprietary solutions which are based on specific commercial tools. This standard provides an effective means of performing those designs in a standard, non-proprietary manner that is independent of specific tools. This promotes cost effective design flows and promotes healthy levels of competition in the electronic design industry. This standard builds on the work of IEEE 1076 VHDL which is a standard hardware description language designed to allow such tool independent electronic design.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification"
        -notes: "Inactive-Withdrawn"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …}
    #channels: Doctrine\ORM\PersistentCollection {#7628 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7613 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7645 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1001628000 {#7318
      date: 2001-09-28 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: DateTime @1232924400 {#7316
      date: 2009-01-26 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1076.4"
    -bookCollection: ""
    -pageCount: 448
    -documents: Doctrine\ORM\PersistentCollection {#7465 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7500 …}
  }
  +appearance: "state-withdrawn"
  +labels: [
    "Withdrawn"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductType App\Twig\Components\ProductType 68.0 MiB 0.22 ms
Input props
[
  "product" => App\Entity\Product\Product {#7311
    #id: 9098
    #code: "IEEE00001616"
    #attributes: Doctrine\ORM\PersistentCollection {#7701 …}
    #variants: Doctrine\ORM\PersistentCollection {#7744 …}
    #options: Doctrine\ORM\PersistentCollection {#7916 …}
    #associations: Doctrine\ORM\PersistentCollection {#7900 …}
    #createdAt: DateTime @1751037969 {#7274
      date: 2025-06-27 17:26:09.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754606304 {#7322
      date: 2025-08-08 00:38:24.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7922 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7921
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7311}
        #id: 31401
        #name: "IEEE 1076.4:2000"
        #slug: "ieee-1076-4-2000-ieee00001616-240750"
        #description: """
          Revision Standard - Inactive-Withdrawn.<br />\n
          The VITAL (VHDL Initiative Towards ASIC Libraries)ASIC Modeling Specification is defined in this standard.This modeling specification defines a methodology which promotes the development of highly accurate, efficient simulation models for ASIC (Application-Specific Integrated Circuit)components in VHDL.<br />\n
          \t\t\t\t<br />\n
          To provide a standard method of modeling ASICs in VHDL. This method is aimed at providing efficient, accurate, and tool independent simulation suitable for large chip-level designs typical of those which are based on ASICs.<br />\n
          Current industry methods for designing complex chip-level designs rely on proprietary solutions which are based on specific commercial tools. This standard provides an effective means of performing those designs in a standard, non-proprietary manner that is independent of specific tools. This promotes cost effective design flows and promotes healthy levels of competition in the electronic design industry. This standard builds on the work of IEEE 1076 VHDL which is a standard hardware description language designed to allow such tool independent electronic design.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification"
        -notes: "Inactive-Withdrawn"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …}
    #channels: Doctrine\ORM\PersistentCollection {#7628 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7613 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7645 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1001628000 {#7318
      date: 2001-09-28 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: DateTime @1232924400 {#7316
      date: 2009-01-26 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1076.4"
    -bookCollection: ""
    -pageCount: 448
    -documents: Doctrine\ORM\PersistentCollection {#7465 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7500 …}
  }
]
Attributes
[]
Component
App\Twig\Components\ProductType {#93188
  +product: App\Entity\Product\Product {#7311
    #id: 9098
    #code: "IEEE00001616"
    #attributes: Doctrine\ORM\PersistentCollection {#7701 …}
    #variants: Doctrine\ORM\PersistentCollection {#7744 …}
    #options: Doctrine\ORM\PersistentCollection {#7916 …}
    #associations: Doctrine\ORM\PersistentCollection {#7900 …}
    #createdAt: DateTime @1751037969 {#7274
      date: 2025-06-27 17:26:09.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754606304 {#7322
      date: 2025-08-08 00:38:24.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7922 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7921
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7311}
        #id: 31401
        #name: "IEEE 1076.4:2000"
        #slug: "ieee-1076-4-2000-ieee00001616-240750"
        #description: """
          Revision Standard - Inactive-Withdrawn.<br />\n
          The VITAL (VHDL Initiative Towards ASIC Libraries)ASIC Modeling Specification is defined in this standard.This modeling specification defines a methodology which promotes the development of highly accurate, efficient simulation models for ASIC (Application-Specific Integrated Circuit)components in VHDL.<br />\n
          \t\t\t\t<br />\n
          To provide a standard method of modeling ASICs in VHDL. This method is aimed at providing efficient, accurate, and tool independent simulation suitable for large chip-level designs typical of those which are based on ASICs.<br />\n
          Current industry methods for designing complex chip-level designs rely on proprietary solutions which are based on specific commercial tools. This standard provides an effective means of performing those designs in a standard, non-proprietary manner that is independent of specific tools. This promotes cost effective design flows and promotes healthy levels of competition in the electronic design industry. This standard builds on the work of IEEE 1076 VHDL which is a standard hardware description language designed to allow such tool independent electronic design.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification"
        -notes: "Inactive-Withdrawn"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …}
    #channels: Doctrine\ORM\PersistentCollection {#7628 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7613 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7645 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1001628000 {#7318
      date: 2001-09-28 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: DateTime @1232924400 {#7316
      date: 2009-01-26 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1076.4"
    -bookCollection: ""
    -pageCount: 448
    -documents: Doctrine\ORM\PersistentCollection {#7465 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7500 …}
  }
  +label: "Standard"
  -typeAttributeCode: "type"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductMostRecent App\Twig\Components\ProductMostRecent 68.0 MiB 0.65 ms
Input props
[
  "product" => App\Entity\Product\Product {#7311
    #id: 9098
    #code: "IEEE00001616"
    #attributes: Doctrine\ORM\PersistentCollection {#7701 …}
    #variants: Doctrine\ORM\PersistentCollection {#7744 …}
    #options: Doctrine\ORM\PersistentCollection {#7916 …}
    #associations: Doctrine\ORM\PersistentCollection {#7900 …}
    #createdAt: DateTime @1751037969 {#7274
      date: 2025-06-27 17:26:09.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754606304 {#7322
      date: 2025-08-08 00:38:24.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7922 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7921
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7311}
        #id: 31401
        #name: "IEEE 1076.4:2000"
        #slug: "ieee-1076-4-2000-ieee00001616-240750"
        #description: """
          Revision Standard - Inactive-Withdrawn.<br />\n
          The VITAL (VHDL Initiative Towards ASIC Libraries)ASIC Modeling Specification is defined in this standard.This modeling specification defines a methodology which promotes the development of highly accurate, efficient simulation models for ASIC (Application-Specific Integrated Circuit)components in VHDL.<br />\n
          \t\t\t\t<br />\n
          To provide a standard method of modeling ASICs in VHDL. This method is aimed at providing efficient, accurate, and tool independent simulation suitable for large chip-level designs typical of those which are based on ASICs.<br />\n
          Current industry methods for designing complex chip-level designs rely on proprietary solutions which are based on specific commercial tools. This standard provides an effective means of performing those designs in a standard, non-proprietary manner that is independent of specific tools. This promotes cost effective design flows and promotes healthy levels of competition in the electronic design industry. This standard builds on the work of IEEE 1076 VHDL which is a standard hardware description language designed to allow such tool independent electronic design.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification"
        -notes: "Inactive-Withdrawn"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …}
    #channels: Doctrine\ORM\PersistentCollection {#7628 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7613 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7645 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1001628000 {#7318
      date: 2001-09-28 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: DateTime @1232924400 {#7316
      date: 2009-01-26 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1076.4"
    -bookCollection: ""
    -pageCount: 448
    -documents: Doctrine\ORM\PersistentCollection {#7465 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7500 …}
  }
]
Attributes
[]
Component
App\Twig\Components\ProductMostRecent {#93263
  +product: App\Entity\Product\Product {#7311
    #id: 9098
    #code: "IEEE00001616"
    #attributes: Doctrine\ORM\PersistentCollection {#7701 …}
    #variants: Doctrine\ORM\PersistentCollection {#7744 …}
    #options: Doctrine\ORM\PersistentCollection {#7916 …}
    #associations: Doctrine\ORM\PersistentCollection {#7900 …}
    #createdAt: DateTime @1751037969 {#7274
      date: 2025-06-27 17:26:09.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754606304 {#7322
      date: 2025-08-08 00:38:24.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7922 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7921
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7311}
        #id: 31401
        #name: "IEEE 1076.4:2000"
        #slug: "ieee-1076-4-2000-ieee00001616-240750"
        #description: """
          Revision Standard - Inactive-Withdrawn.<br />\n
          The VITAL (VHDL Initiative Towards ASIC Libraries)ASIC Modeling Specification is defined in this standard.This modeling specification defines a methodology which promotes the development of highly accurate, efficient simulation models for ASIC (Application-Specific Integrated Circuit)components in VHDL.<br />\n
          \t\t\t\t<br />\n
          To provide a standard method of modeling ASICs in VHDL. This method is aimed at providing efficient, accurate, and tool independent simulation suitable for large chip-level designs typical of those which are based on ASICs.<br />\n
          Current industry methods for designing complex chip-level designs rely on proprietary solutions which are based on specific commercial tools. This standard provides an effective means of performing those designs in a standard, non-proprietary manner that is independent of specific tools. This promotes cost effective design flows and promotes healthy levels of competition in the electronic design industry. This standard builds on the work of IEEE 1076 VHDL which is a standard hardware description language designed to allow such tool independent electronic design.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification"
        -notes: "Inactive-Withdrawn"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …}
    #channels: Doctrine\ORM\PersistentCollection {#7628 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7613 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7645 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1001628000 {#7318
      date: 2001-09-28 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: DateTime @1232924400 {#7316
      date: 2009-01-26 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1076.4"
    -bookCollection: ""
    -pageCount: 448
    -documents: Doctrine\ORM\PersistentCollection {#7465 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7500 …}
  }
  +label: "Most Recent"
  +icon: "check-xs"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductState App\Twig\Components\ProductState 74.0 MiB 0.20 ms
Input props
[
  "product" => App\Entity\Product\Product {#100253
    #id: 9099
    #code: "IEEE00001617"
    #attributes: Doctrine\ORM\PersistentCollection {#100236 …}
    #variants: Doctrine\ORM\PersistentCollection {#100233 …}
    #options: Doctrine\ORM\PersistentCollection {#100229 …}
    #associations: Doctrine\ORM\PersistentCollection {#100231 …}
    #createdAt: DateTime @1751037970 {#100261
      date: 2025-06-27 17:26:10.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#100234
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#100247 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#100271
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#100253}
        #id: 31405
        #name: "IEEE 1076.4:1995"
        #slug: "ieee-1076-4-1995-ieee00001617-240751"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          Superseded by 1076.4-2000. The VITAL (VHDL Initiative Towards ASIC Libraries) ASIC Modeling Specification is defined. It creates a methodology that promotes the development of highly accurate, efficient simulation models for ASIC (Application-Specific Integrated Circuit) components in VHDL.<br />\n
          \t\t\t\t<br />\n
          To provide a standard method for modeling ASICs in VHDL. This method is aimed at providing efficient, accurate, and tool independent simulation suitable for large chip-level designs typical of those which are based on ASICs.<br />\n
          Current industry methods for designing complex chip-level designs rely on proprietary solutions which are based on specific commercial tools. This standard provides an effective means of performing those designs in a standard, non-proprietary manner that is independent of specific tools. This promotes cost effective design flows and promotes healthy levels of competition in the electronic design industry. This standard builds on the work of IEEE 1076 VHDL, which is a standard hardware description language designed to allow such tool independent electronic design.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard VITAL Application-Specific Integrated Circuit (ASIC) Modeling Specification"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#100244 …}
    #channels: Doctrine\ORM\PersistentCollection {#100238 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …}
    #reviews: Doctrine\ORM\PersistentCollection {#100242 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#100240 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#100254 …}
    -apiLastModifiedAt: DateTime @1754517600 {#100221
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#100260
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @832284000 {#100259
      date: 1996-05-17 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1076.4"
    -bookCollection: ""
    -pageCount: 96
    -documents: Doctrine\ORM\PersistentCollection {#100251 …}
    -favorites: Doctrine\ORM\PersistentCollection {#100249 …}
  }
  "showFullLabel" => "true"
]
Attributes
[
  "showFullLabel" => "true"
]
Component
App\Twig\Components\ProductState {#100307
  +product: App\Entity\Product\Product {#100253
    #id: 9099
    #code: "IEEE00001617"
    #attributes: Doctrine\ORM\PersistentCollection {#100236 …}
    #variants: Doctrine\ORM\PersistentCollection {#100233 …}
    #options: Doctrine\ORM\PersistentCollection {#100229 …}
    #associations: Doctrine\ORM\PersistentCollection {#100231 …}
    #createdAt: DateTime @1751037970 {#100261
      date: 2025-06-27 17:26:10.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#100234
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#100247 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#100271
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#100253}
        #id: 31405
        #name: "IEEE 1076.4:1995"
        #slug: "ieee-1076-4-1995-ieee00001617-240751"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          Superseded by 1076.4-2000. The VITAL (VHDL Initiative Towards ASIC Libraries) ASIC Modeling Specification is defined. It creates a methodology that promotes the development of highly accurate, efficient simulation models for ASIC (Application-Specific Integrated Circuit) components in VHDL.<br />\n
          \t\t\t\t<br />\n
          To provide a standard method for modeling ASICs in VHDL. This method is aimed at providing efficient, accurate, and tool independent simulation suitable for large chip-level designs typical of those which are based on ASICs.<br />\n
          Current industry methods for designing complex chip-level designs rely on proprietary solutions which are based on specific commercial tools. This standard provides an effective means of performing those designs in a standard, non-proprietary manner that is independent of specific tools. This promotes cost effective design flows and promotes healthy levels of competition in the electronic design industry. This standard builds on the work of IEEE 1076 VHDL, which is a standard hardware description language designed to allow such tool independent electronic design.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard VITAL Application-Specific Integrated Circuit (ASIC) Modeling Specification"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#100244 …}
    #channels: Doctrine\ORM\PersistentCollection {#100238 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …}
    #reviews: Doctrine\ORM\PersistentCollection {#100242 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#100240 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#100254 …}
    -apiLastModifiedAt: DateTime @1754517600 {#100221
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#100260
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @832284000 {#100259
      date: 1996-05-17 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1076.4"
    -bookCollection: ""
    -pageCount: 96
    -documents: Doctrine\ORM\PersistentCollection {#100251 …}
    -favorites: Doctrine\ORM\PersistentCollection {#100249 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductMostRecent App\Twig\Components\ProductMostRecent 74.0 MiB 0.75 ms
Input props
[
  "product" => App\Entity\Product\Product {#100253
    #id: 9099
    #code: "IEEE00001617"
    #attributes: Doctrine\ORM\PersistentCollection {#100236 …}
    #variants: Doctrine\ORM\PersistentCollection {#100233 …}
    #options: Doctrine\ORM\PersistentCollection {#100229 …}
    #associations: Doctrine\ORM\PersistentCollection {#100231 …}
    #createdAt: DateTime @1751037970 {#100261
      date: 2025-06-27 17:26:10.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#100234
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#100247 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#100271
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#100253}
        #id: 31405
        #name: "IEEE 1076.4:1995"
        #slug: "ieee-1076-4-1995-ieee00001617-240751"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          Superseded by 1076.4-2000. The VITAL (VHDL Initiative Towards ASIC Libraries) ASIC Modeling Specification is defined. It creates a methodology that promotes the development of highly accurate, efficient simulation models for ASIC (Application-Specific Integrated Circuit) components in VHDL.<br />\n
          \t\t\t\t<br />\n
          To provide a standard method for modeling ASICs in VHDL. This method is aimed at providing efficient, accurate, and tool independent simulation suitable for large chip-level designs typical of those which are based on ASICs.<br />\n
          Current industry methods for designing complex chip-level designs rely on proprietary solutions which are based on specific commercial tools. This standard provides an effective means of performing those designs in a standard, non-proprietary manner that is independent of specific tools. This promotes cost effective design flows and promotes healthy levels of competition in the electronic design industry. This standard builds on the work of IEEE 1076 VHDL, which is a standard hardware description language designed to allow such tool independent electronic design.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard VITAL Application-Specific Integrated Circuit (ASIC) Modeling Specification"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#100244 …}
    #channels: Doctrine\ORM\PersistentCollection {#100238 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …}
    #reviews: Doctrine\ORM\PersistentCollection {#100242 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#100240 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#100254 …}
    -apiLastModifiedAt: DateTime @1754517600 {#100221
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#100260
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @832284000 {#100259
      date: 1996-05-17 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1076.4"
    -bookCollection: ""
    -pageCount: 96
    -documents: Doctrine\ORM\PersistentCollection {#100251 …}
    -favorites: Doctrine\ORM\PersistentCollection {#100249 …}
  }
]
Attributes
[]
Component
App\Twig\Components\ProductMostRecent {#100374
  +product: App\Entity\Product\Product {#100253
    #id: 9099
    #code: "IEEE00001617"
    #attributes: Doctrine\ORM\PersistentCollection {#100236 …}
    #variants: Doctrine\ORM\PersistentCollection {#100233 …}
    #options: Doctrine\ORM\PersistentCollection {#100229 …}
    #associations: Doctrine\ORM\PersistentCollection {#100231 …}
    #createdAt: DateTime @1751037970 {#100261
      date: 2025-06-27 17:26:10.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#100234
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#100247 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#100271
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#100253}
        #id: 31405
        #name: "IEEE 1076.4:1995"
        #slug: "ieee-1076-4-1995-ieee00001617-240751"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          Superseded by 1076.4-2000. The VITAL (VHDL Initiative Towards ASIC Libraries) ASIC Modeling Specification is defined. It creates a methodology that promotes the development of highly accurate, efficient simulation models for ASIC (Application-Specific Integrated Circuit) components in VHDL.<br />\n
          \t\t\t\t<br />\n
          To provide a standard method for modeling ASICs in VHDL. This method is aimed at providing efficient, accurate, and tool independent simulation suitable for large chip-level designs typical of those which are based on ASICs.<br />\n
          Current industry methods for designing complex chip-level designs rely on proprietary solutions which are based on specific commercial tools. This standard provides an effective means of performing those designs in a standard, non-proprietary manner that is independent of specific tools. This promotes cost effective design flows and promotes healthy levels of competition in the electronic design industry. This standard builds on the work of IEEE 1076 VHDL, which is a standard hardware description language designed to allow such tool independent electronic design.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard VITAL Application-Specific Integrated Circuit (ASIC) Modeling Specification"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#100244 …}
    #channels: Doctrine\ORM\PersistentCollection {#100238 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …}
    #reviews: Doctrine\ORM\PersistentCollection {#100242 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#100240 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#100254 …}
    -apiLastModifiedAt: DateTime @1754517600 {#100221
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#100260
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @832284000 {#100259
      date: 1996-05-17 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1076.4"
    -bookCollection: ""
    -pageCount: 96
    -documents: Doctrine\ORM\PersistentCollection {#100251 …}
    -favorites: Doctrine\ORM\PersistentCollection {#100249 …}
  }
  +label: "Historical"
  +icon: "historical"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductState App\Twig\Components\ProductState 80.0 MiB 0.18 ms
Input props
[
  "product" => App\Entity\Product\Product {#7311
    #id: 9098
    #code: "IEEE00001616"
    #attributes: Doctrine\ORM\PersistentCollection {#7701 …}
    #variants: Doctrine\ORM\PersistentCollection {#7744 …}
    #options: Doctrine\ORM\PersistentCollection {#7916 …}
    #associations: Doctrine\ORM\PersistentCollection {#7900 …}
    #createdAt: DateTime @1751037969 {#7274
      date: 2025-06-27 17:26:09.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754606304 {#7322
      date: 2025-08-08 00:38:24.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7922 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7921
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7311}
        #id: 31401
        #name: "IEEE 1076.4:2000"
        #slug: "ieee-1076-4-2000-ieee00001616-240750"
        #description: """
          Revision Standard - Inactive-Withdrawn.<br />\n
          The VITAL (VHDL Initiative Towards ASIC Libraries)ASIC Modeling Specification is defined in this standard.This modeling specification defines a methodology which promotes the development of highly accurate, efficient simulation models for ASIC (Application-Specific Integrated Circuit)components in VHDL.<br />\n
          \t\t\t\t<br />\n
          To provide a standard method of modeling ASICs in VHDL. This method is aimed at providing efficient, accurate, and tool independent simulation suitable for large chip-level designs typical of those which are based on ASICs.<br />\n
          Current industry methods for designing complex chip-level designs rely on proprietary solutions which are based on specific commercial tools. This standard provides an effective means of performing those designs in a standard, non-proprietary manner that is independent of specific tools. This promotes cost effective design flows and promotes healthy levels of competition in the electronic design industry. This standard builds on the work of IEEE 1076 VHDL which is a standard hardware description language designed to allow such tool independent electronic design.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification"
        -notes: "Inactive-Withdrawn"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …}
    #channels: Doctrine\ORM\PersistentCollection {#7628 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7613 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7645 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1001628000 {#7318
      date: 2001-09-28 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: DateTime @1232924400 {#7316
      date: 2009-01-26 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1076.4"
    -bookCollection: ""
    -pageCount: 448
    -documents: Doctrine\ORM\PersistentCollection {#7465 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7500 …}
  }
  "showFullLabel" => "true"
]
Attributes
[
  "showFullLabel" => "true"
]
Component
App\Twig\Components\ProductState {#106955
  +product: App\Entity\Product\Product {#7311
    #id: 9098
    #code: "IEEE00001616"
    #attributes: Doctrine\ORM\PersistentCollection {#7701 …}
    #variants: Doctrine\ORM\PersistentCollection {#7744 …}
    #options: Doctrine\ORM\PersistentCollection {#7916 …}
    #associations: Doctrine\ORM\PersistentCollection {#7900 …}
    #createdAt: DateTime @1751037969 {#7274
      date: 2025-06-27 17:26:09.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754606304 {#7322
      date: 2025-08-08 00:38:24.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7922 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7921
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7311}
        #id: 31401
        #name: "IEEE 1076.4:2000"
        #slug: "ieee-1076-4-2000-ieee00001616-240750"
        #description: """
          Revision Standard - Inactive-Withdrawn.<br />\n
          The VITAL (VHDL Initiative Towards ASIC Libraries)ASIC Modeling Specification is defined in this standard.This modeling specification defines a methodology which promotes the development of highly accurate, efficient simulation models for ASIC (Application-Specific Integrated Circuit)components in VHDL.<br />\n
          \t\t\t\t<br />\n
          To provide a standard method of modeling ASICs in VHDL. This method is aimed at providing efficient, accurate, and tool independent simulation suitable for large chip-level designs typical of those which are based on ASICs.<br />\n
          Current industry methods for designing complex chip-level designs rely on proprietary solutions which are based on specific commercial tools. This standard provides an effective means of performing those designs in a standard, non-proprietary manner that is independent of specific tools. This promotes cost effective design flows and promotes healthy levels of competition in the electronic design industry. This standard builds on the work of IEEE 1076 VHDL which is a standard hardware description language designed to allow such tool independent electronic design.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification"
        -notes: "Inactive-Withdrawn"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …}
    #channels: Doctrine\ORM\PersistentCollection {#7628 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7613 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7645 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1001628000 {#7318
      date: 2001-09-28 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: DateTime @1232924400 {#7316
      date: 2009-01-26 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1076.4"
    -bookCollection: ""
    -pageCount: 448
    -documents: Doctrine\ORM\PersistentCollection {#7465 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7500 …}
  }
  +appearance: "state-withdrawn"
  +labels: [
    "Withdrawn"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductMostRecent App\Twig\Components\ProductMostRecent 80.0 MiB 0.71 ms
Input props
[
  "product" => App\Entity\Product\Product {#7311
    #id: 9098
    #code: "IEEE00001616"
    #attributes: Doctrine\ORM\PersistentCollection {#7701 …}
    #variants: Doctrine\ORM\PersistentCollection {#7744 …}
    #options: Doctrine\ORM\PersistentCollection {#7916 …}
    #associations: Doctrine\ORM\PersistentCollection {#7900 …}
    #createdAt: DateTime @1751037969 {#7274
      date: 2025-06-27 17:26:09.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754606304 {#7322
      date: 2025-08-08 00:38:24.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7922 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7921
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7311}
        #id: 31401
        #name: "IEEE 1076.4:2000"
        #slug: "ieee-1076-4-2000-ieee00001616-240750"
        #description: """
          Revision Standard - Inactive-Withdrawn.<br />\n
          The VITAL (VHDL Initiative Towards ASIC Libraries)ASIC Modeling Specification is defined in this standard.This modeling specification defines a methodology which promotes the development of highly accurate, efficient simulation models for ASIC (Application-Specific Integrated Circuit)components in VHDL.<br />\n
          \t\t\t\t<br />\n
          To provide a standard method of modeling ASICs in VHDL. This method is aimed at providing efficient, accurate, and tool independent simulation suitable for large chip-level designs typical of those which are based on ASICs.<br />\n
          Current industry methods for designing complex chip-level designs rely on proprietary solutions which are based on specific commercial tools. This standard provides an effective means of performing those designs in a standard, non-proprietary manner that is independent of specific tools. This promotes cost effective design flows and promotes healthy levels of competition in the electronic design industry. This standard builds on the work of IEEE 1076 VHDL which is a standard hardware description language designed to allow such tool independent electronic design.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification"
        -notes: "Inactive-Withdrawn"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …}
    #channels: Doctrine\ORM\PersistentCollection {#7628 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7613 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7645 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1001628000 {#7318
      date: 2001-09-28 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: DateTime @1232924400 {#7316
      date: 2009-01-26 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1076.4"
    -bookCollection: ""
    -pageCount: 448
    -documents: Doctrine\ORM\PersistentCollection {#7465 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7500 …}
  }
]
Attributes
[]
Component
App\Twig\Components\ProductMostRecent {#106997
  +product: App\Entity\Product\Product {#7311
    #id: 9098
    #code: "IEEE00001616"
    #attributes: Doctrine\ORM\PersistentCollection {#7701 …}
    #variants: Doctrine\ORM\PersistentCollection {#7744 …}
    #options: Doctrine\ORM\PersistentCollection {#7916 …}
    #associations: Doctrine\ORM\PersistentCollection {#7900 …}
    #createdAt: DateTime @1751037969 {#7274
      date: 2025-06-27 17:26:09.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754606304 {#7322
      date: 2025-08-08 00:38:24.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7922 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7921
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7311}
        #id: 31401
        #name: "IEEE 1076.4:2000"
        #slug: "ieee-1076-4-2000-ieee00001616-240750"
        #description: """
          Revision Standard - Inactive-Withdrawn.<br />\n
          The VITAL (VHDL Initiative Towards ASIC Libraries)ASIC Modeling Specification is defined in this standard.This modeling specification defines a methodology which promotes the development of highly accurate, efficient simulation models for ASIC (Application-Specific Integrated Circuit)components in VHDL.<br />\n
          \t\t\t\t<br />\n
          To provide a standard method of modeling ASICs in VHDL. This method is aimed at providing efficient, accurate, and tool independent simulation suitable for large chip-level designs typical of those which are based on ASICs.<br />\n
          Current industry methods for designing complex chip-level designs rely on proprietary solutions which are based on specific commercial tools. This standard provides an effective means of performing those designs in a standard, non-proprietary manner that is independent of specific tools. This promotes cost effective design flows and promotes healthy levels of competition in the electronic design industry. This standard builds on the work of IEEE 1076 VHDL which is a standard hardware description language designed to allow such tool independent electronic design.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification"
        -notes: "Inactive-Withdrawn"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …}
    #channels: Doctrine\ORM\PersistentCollection {#7628 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7613 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7645 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1001628000 {#7318
      date: 2001-09-28 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: DateTime @1232924400 {#7316
      date: 2009-01-26 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1076.4"
    -bookCollection: ""
    -pageCount: 448
    -documents: Doctrine\ORM\PersistentCollection {#7465 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7500 …}
  }
  +label: "Most Recent"
  +icon: "check-xs"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductState App\Twig\Components\ProductState 80.0 MiB 0.17 ms
Input props
[
  "product" => App\Entity\Product\Product {#100253
    #id: 9099
    #code: "IEEE00001617"
    #attributes: Doctrine\ORM\PersistentCollection {#100236 …}
    #variants: Doctrine\ORM\PersistentCollection {#100233 …}
    #options: Doctrine\ORM\PersistentCollection {#100229 …}
    #associations: Doctrine\ORM\PersistentCollection {#100231 …}
    #createdAt: DateTime @1751037970 {#100261
      date: 2025-06-27 17:26:10.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#100234
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#100247 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#100271
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#100253}
        #id: 31405
        #name: "IEEE 1076.4:1995"
        #slug: "ieee-1076-4-1995-ieee00001617-240751"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          Superseded by 1076.4-2000. The VITAL (VHDL Initiative Towards ASIC Libraries) ASIC Modeling Specification is defined. It creates a methodology that promotes the development of highly accurate, efficient simulation models for ASIC (Application-Specific Integrated Circuit) components in VHDL.<br />\n
          \t\t\t\t<br />\n
          To provide a standard method for modeling ASICs in VHDL. This method is aimed at providing efficient, accurate, and tool independent simulation suitable for large chip-level designs typical of those which are based on ASICs.<br />\n
          Current industry methods for designing complex chip-level designs rely on proprietary solutions which are based on specific commercial tools. This standard provides an effective means of performing those designs in a standard, non-proprietary manner that is independent of specific tools. This promotes cost effective design flows and promotes healthy levels of competition in the electronic design industry. This standard builds on the work of IEEE 1076 VHDL, which is a standard hardware description language designed to allow such tool independent electronic design.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard VITAL Application-Specific Integrated Circuit (ASIC) Modeling Specification"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#100244 …}
    #channels: Doctrine\ORM\PersistentCollection {#100238 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …}
    #reviews: Doctrine\ORM\PersistentCollection {#100242 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#100240 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#100254 …}
    -apiLastModifiedAt: DateTime @1754517600 {#100221
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#100260
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @832284000 {#100259
      date: 1996-05-17 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1076.4"
    -bookCollection: ""
    -pageCount: 96
    -documents: Doctrine\ORM\PersistentCollection {#100251 …}
    -favorites: Doctrine\ORM\PersistentCollection {#100249 …}
  }
  "showFullLabel" => "true"
]
Attributes
[
  "showFullLabel" => "true"
]
Component
App\Twig\Components\ProductState {#107062
  +product: App\Entity\Product\Product {#100253
    #id: 9099
    #code: "IEEE00001617"
    #attributes: Doctrine\ORM\PersistentCollection {#100236 …}
    #variants: Doctrine\ORM\PersistentCollection {#100233 …}
    #options: Doctrine\ORM\PersistentCollection {#100229 …}
    #associations: Doctrine\ORM\PersistentCollection {#100231 …}
    #createdAt: DateTime @1751037970 {#100261
      date: 2025-06-27 17:26:10.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#100234
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#100247 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#100271
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#100253}
        #id: 31405
        #name: "IEEE 1076.4:1995"
        #slug: "ieee-1076-4-1995-ieee00001617-240751"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          Superseded by 1076.4-2000. The VITAL (VHDL Initiative Towards ASIC Libraries) ASIC Modeling Specification is defined. It creates a methodology that promotes the development of highly accurate, efficient simulation models for ASIC (Application-Specific Integrated Circuit) components in VHDL.<br />\n
          \t\t\t\t<br />\n
          To provide a standard method for modeling ASICs in VHDL. This method is aimed at providing efficient, accurate, and tool independent simulation suitable for large chip-level designs typical of those which are based on ASICs.<br />\n
          Current industry methods for designing complex chip-level designs rely on proprietary solutions which are based on specific commercial tools. This standard provides an effective means of performing those designs in a standard, non-proprietary manner that is independent of specific tools. This promotes cost effective design flows and promotes healthy levels of competition in the electronic design industry. This standard builds on the work of IEEE 1076 VHDL, which is a standard hardware description language designed to allow such tool independent electronic design.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard VITAL Application-Specific Integrated Circuit (ASIC) Modeling Specification"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#100244 …}
    #channels: Doctrine\ORM\PersistentCollection {#100238 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …}
    #reviews: Doctrine\ORM\PersistentCollection {#100242 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#100240 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#100254 …}
    -apiLastModifiedAt: DateTime @1754517600 {#100221
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#100260
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @832284000 {#100259
      date: 1996-05-17 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1076.4"
    -bookCollection: ""
    -pageCount: 96
    -documents: Doctrine\ORM\PersistentCollection {#100251 …}
    -favorites: Doctrine\ORM\PersistentCollection {#100249 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductMostRecent App\Twig\Components\ProductMostRecent 80.0 MiB 0.61 ms
Input props
[
  "product" => App\Entity\Product\Product {#100253
    #id: 9099
    #code: "IEEE00001617"
    #attributes: Doctrine\ORM\PersistentCollection {#100236 …}
    #variants: Doctrine\ORM\PersistentCollection {#100233 …}
    #options: Doctrine\ORM\PersistentCollection {#100229 …}
    #associations: Doctrine\ORM\PersistentCollection {#100231 …}
    #createdAt: DateTime @1751037970 {#100261
      date: 2025-06-27 17:26:10.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#100234
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#100247 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#100271
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#100253}
        #id: 31405
        #name: "IEEE 1076.4:1995"
        #slug: "ieee-1076-4-1995-ieee00001617-240751"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          Superseded by 1076.4-2000. The VITAL (VHDL Initiative Towards ASIC Libraries) ASIC Modeling Specification is defined. It creates a methodology that promotes the development of highly accurate, efficient simulation models for ASIC (Application-Specific Integrated Circuit) components in VHDL.<br />\n
          \t\t\t\t<br />\n
          To provide a standard method for modeling ASICs in VHDL. This method is aimed at providing efficient, accurate, and tool independent simulation suitable for large chip-level designs typical of those which are based on ASICs.<br />\n
          Current industry methods for designing complex chip-level designs rely on proprietary solutions which are based on specific commercial tools. This standard provides an effective means of performing those designs in a standard, non-proprietary manner that is independent of specific tools. This promotes cost effective design flows and promotes healthy levels of competition in the electronic design industry. This standard builds on the work of IEEE 1076 VHDL, which is a standard hardware description language designed to allow such tool independent electronic design.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard VITAL Application-Specific Integrated Circuit (ASIC) Modeling Specification"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#100244 …}
    #channels: Doctrine\ORM\PersistentCollection {#100238 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …}
    #reviews: Doctrine\ORM\PersistentCollection {#100242 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#100240 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#100254 …}
    -apiLastModifiedAt: DateTime @1754517600 {#100221
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#100260
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @832284000 {#100259
      date: 1996-05-17 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1076.4"
    -bookCollection: ""
    -pageCount: 96
    -documents: Doctrine\ORM\PersistentCollection {#100251 …}
    -favorites: Doctrine\ORM\PersistentCollection {#100249 …}
  }
]
Attributes
[]
Component
App\Twig\Components\ProductMostRecent {#107089
  +product: App\Entity\Product\Product {#100253
    #id: 9099
    #code: "IEEE00001617"
    #attributes: Doctrine\ORM\PersistentCollection {#100236 …}
    #variants: Doctrine\ORM\PersistentCollection {#100233 …}
    #options: Doctrine\ORM\PersistentCollection {#100229 …}
    #associations: Doctrine\ORM\PersistentCollection {#100231 …}
    #createdAt: DateTime @1751037970 {#100261
      date: 2025-06-27 17:26:10.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#100234
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#100247 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#100271
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#100253}
        #id: 31405
        #name: "IEEE 1076.4:1995"
        #slug: "ieee-1076-4-1995-ieee00001617-240751"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          Superseded by 1076.4-2000. The VITAL (VHDL Initiative Towards ASIC Libraries) ASIC Modeling Specification is defined. It creates a methodology that promotes the development of highly accurate, efficient simulation models for ASIC (Application-Specific Integrated Circuit) components in VHDL.<br />\n
          \t\t\t\t<br />\n
          To provide a standard method for modeling ASICs in VHDL. This method is aimed at providing efficient, accurate, and tool independent simulation suitable for large chip-level designs typical of those which are based on ASICs.<br />\n
          Current industry methods for designing complex chip-level designs rely on proprietary solutions which are based on specific commercial tools. This standard provides an effective means of performing those designs in a standard, non-proprietary manner that is independent of specific tools. This promotes cost effective design flows and promotes healthy levels of competition in the electronic design industry. This standard builds on the work of IEEE 1076 VHDL, which is a standard hardware description language designed to allow such tool independent electronic design.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard VITAL Application-Specific Integrated Circuit (ASIC) Modeling Specification"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#100244 …}
    #channels: Doctrine\ORM\PersistentCollection {#100238 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …}
    #reviews: Doctrine\ORM\PersistentCollection {#100242 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#100240 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#100254 …}
    -apiLastModifiedAt: DateTime @1754517600 {#100221
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#100260
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @832284000 {#100259
      date: 1996-05-17 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1076.4"
    -bookCollection: ""
    -pageCount: 96
    -documents: Doctrine\ORM\PersistentCollection {#100251 …}
    -favorites: Doctrine\ORM\PersistentCollection {#100249 …}
  }
  +label: "Historical"
  +icon: "historical"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}