Components

3 Twig Components
5 Render Count
2 ms Render Time
134.0 MiB Memory Usage

Components

Name Metadata Render Count Render Time
ProductState
"App\Twig\Components\ProductState"
components/ProductState.html.twig
2 0.49ms
ProductMostRecent
"App\Twig\Components\ProductMostRecent"
components/ProductMostRecent.html.twig
2 1.37ms
ProductType
"App\Twig\Components\ProductType"
components/ProductType.html.twig
1 0.25ms

Render calls

ProductState App\Twig\Components\ProductState 134.0 MiB 0.30 ms
Input props
[
  "product" => App\Entity\Product\Product {#7311
    #id: 9319
    #code: "IEEE00002053"
    #attributes: Doctrine\ORM\PersistentCollection {#7701 …}
    #variants: Doctrine\ORM\PersistentCollection {#7744 …}
    #options: Doctrine\ORM\PersistentCollection {#7916 …}
    #associations: Doctrine\ORM\PersistentCollection {#7900 …}
    #createdAt: DateTime @1751038165 {#7274
      date: 2025-06-27 17:29:25.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#7322
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7922 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7921
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7311}
        #id: 32285
        #name: "IEEE 1364.1:2002"
        #slug: "ieee-1364-1-2002-ieee00002053-240971"
        #description: """
          New IEEE Standard - Inactive-Withdrawn.<br />\n
          Superseded by IEC/IEEE 62142-2005. To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standard IEEE 1364. To define syntax and semantics which can be used in common by all compliant RTL synthesis tools to achieve uniformity of results in a similar manner to which simulation tools currently use the IEEE 1364 standard. This will allow users of synthesis tools to produce well-defined designs whose functional characteristics are independent of any particular synthesis implementation by making their design compliant with this developed standard. Standard syntax and semantics for Verilog ® HDL-based RTL synthesis are described inthis standard.<br />\n
          \t\t\t\t<br />\n
          To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standard IEEE 1364.<br />\n
          To define syntax and semantics which can be used in common by all compliant RTL synthesis tools to achieve uniformity of results in a similar manner to which simulation tools currently use the IEEE 1364 standard. This will allow users of synthesis tools to produce well-defined designs whose functional characteristics are independent of any particular synthesis implementation by making their design compliant with this developed standard.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Verilog Register Transfer Level Synthesis"
        -notes: "Inactive-Withdrawn"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …}
    #channels: Doctrine\ORM\PersistentCollection {#7628 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7613 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7645 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1040166000 {#7318
      date: 2002-12-18 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: DateTime @1262991600 {#7316
      date: 2010-01-09 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1364.1"
    -bookCollection: ""
    -pageCount: 108
    -documents: Doctrine\ORM\PersistentCollection {#7465 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7500 …}
  }
  "showFullLabel" => "true"
]
Attributes
[
  "showFullLabel" => "true"
]
Component
App\Twig\Components\ProductState {#93008
  +product: App\Entity\Product\Product {#7311
    #id: 9319
    #code: "IEEE00002053"
    #attributes: Doctrine\ORM\PersistentCollection {#7701 …}
    #variants: Doctrine\ORM\PersistentCollection {#7744 …}
    #options: Doctrine\ORM\PersistentCollection {#7916 …}
    #associations: Doctrine\ORM\PersistentCollection {#7900 …}
    #createdAt: DateTime @1751038165 {#7274
      date: 2025-06-27 17:29:25.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#7322
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7922 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7921
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7311}
        #id: 32285
        #name: "IEEE 1364.1:2002"
        #slug: "ieee-1364-1-2002-ieee00002053-240971"
        #description: """
          New IEEE Standard - Inactive-Withdrawn.<br />\n
          Superseded by IEC/IEEE 62142-2005. To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standard IEEE 1364. To define syntax and semantics which can be used in common by all compliant RTL synthesis tools to achieve uniformity of results in a similar manner to which simulation tools currently use the IEEE 1364 standard. This will allow users of synthesis tools to produce well-defined designs whose functional characteristics are independent of any particular synthesis implementation by making their design compliant with this developed standard. Standard syntax and semantics for Verilog ® HDL-based RTL synthesis are described inthis standard.<br />\n
          \t\t\t\t<br />\n
          To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standard IEEE 1364.<br />\n
          To define syntax and semantics which can be used in common by all compliant RTL synthesis tools to achieve uniformity of results in a similar manner to which simulation tools currently use the IEEE 1364 standard. This will allow users of synthesis tools to produce well-defined designs whose functional characteristics are independent of any particular synthesis implementation by making their design compliant with this developed standard.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Verilog Register Transfer Level Synthesis"
        -notes: "Inactive-Withdrawn"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …}
    #channels: Doctrine\ORM\PersistentCollection {#7628 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7613 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7645 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1040166000 {#7318
      date: 2002-12-18 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: DateTime @1262991600 {#7316
      date: 2010-01-09 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1364.1"
    -bookCollection: ""
    -pageCount: 108
    -documents: Doctrine\ORM\PersistentCollection {#7465 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7500 …}
  }
  +appearance: "state-withdrawn"
  +labels: [
    "Withdrawn"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductType App\Twig\Components\ProductType 134.0 MiB 0.25 ms
Input props
[
  "product" => App\Entity\Product\Product {#7311
    #id: 9319
    #code: "IEEE00002053"
    #attributes: Doctrine\ORM\PersistentCollection {#7701 …}
    #variants: Doctrine\ORM\PersistentCollection {#7744 …}
    #options: Doctrine\ORM\PersistentCollection {#7916 …}
    #associations: Doctrine\ORM\PersistentCollection {#7900 …}
    #createdAt: DateTime @1751038165 {#7274
      date: 2025-06-27 17:29:25.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#7322
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7922 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7921
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7311}
        #id: 32285
        #name: "IEEE 1364.1:2002"
        #slug: "ieee-1364-1-2002-ieee00002053-240971"
        #description: """
          New IEEE Standard - Inactive-Withdrawn.<br />\n
          Superseded by IEC/IEEE 62142-2005. To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standard IEEE 1364. To define syntax and semantics which can be used in common by all compliant RTL synthesis tools to achieve uniformity of results in a similar manner to which simulation tools currently use the IEEE 1364 standard. This will allow users of synthesis tools to produce well-defined designs whose functional characteristics are independent of any particular synthesis implementation by making their design compliant with this developed standard. Standard syntax and semantics for Verilog ® HDL-based RTL synthesis are described inthis standard.<br />\n
          \t\t\t\t<br />\n
          To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standard IEEE 1364.<br />\n
          To define syntax and semantics which can be used in common by all compliant RTL synthesis tools to achieve uniformity of results in a similar manner to which simulation tools currently use the IEEE 1364 standard. This will allow users of synthesis tools to produce well-defined designs whose functional characteristics are independent of any particular synthesis implementation by making their design compliant with this developed standard.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Verilog Register Transfer Level Synthesis"
        -notes: "Inactive-Withdrawn"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …}
    #channels: Doctrine\ORM\PersistentCollection {#7628 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7613 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7645 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1040166000 {#7318
      date: 2002-12-18 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: DateTime @1262991600 {#7316
      date: 2010-01-09 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1364.1"
    -bookCollection: ""
    -pageCount: 108
    -documents: Doctrine\ORM\PersistentCollection {#7465 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7500 …}
  }
]
Attributes
[]
Component
App\Twig\Components\ProductType {#93188
  +product: App\Entity\Product\Product {#7311
    #id: 9319
    #code: "IEEE00002053"
    #attributes: Doctrine\ORM\PersistentCollection {#7701 …}
    #variants: Doctrine\ORM\PersistentCollection {#7744 …}
    #options: Doctrine\ORM\PersistentCollection {#7916 …}
    #associations: Doctrine\ORM\PersistentCollection {#7900 …}
    #createdAt: DateTime @1751038165 {#7274
      date: 2025-06-27 17:29:25.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#7322
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7922 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7921
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7311}
        #id: 32285
        #name: "IEEE 1364.1:2002"
        #slug: "ieee-1364-1-2002-ieee00002053-240971"
        #description: """
          New IEEE Standard - Inactive-Withdrawn.<br />\n
          Superseded by IEC/IEEE 62142-2005. To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standard IEEE 1364. To define syntax and semantics which can be used in common by all compliant RTL synthesis tools to achieve uniformity of results in a similar manner to which simulation tools currently use the IEEE 1364 standard. This will allow users of synthesis tools to produce well-defined designs whose functional characteristics are independent of any particular synthesis implementation by making their design compliant with this developed standard. Standard syntax and semantics for Verilog ® HDL-based RTL synthesis are described inthis standard.<br />\n
          \t\t\t\t<br />\n
          To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standard IEEE 1364.<br />\n
          To define syntax and semantics which can be used in common by all compliant RTL synthesis tools to achieve uniformity of results in a similar manner to which simulation tools currently use the IEEE 1364 standard. This will allow users of synthesis tools to produce well-defined designs whose functional characteristics are independent of any particular synthesis implementation by making their design compliant with this developed standard.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Verilog Register Transfer Level Synthesis"
        -notes: "Inactive-Withdrawn"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …}
    #channels: Doctrine\ORM\PersistentCollection {#7628 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7613 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7645 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1040166000 {#7318
      date: 2002-12-18 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: DateTime @1262991600 {#7316
      date: 2010-01-09 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1364.1"
    -bookCollection: ""
    -pageCount: 108
    -documents: Doctrine\ORM\PersistentCollection {#7465 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7500 …}
  }
  +label: "Standard"
  -typeAttributeCode: "type"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductMostRecent App\Twig\Components\ProductMostRecent 134.0 MiB 0.67 ms
Input props
[
  "product" => App\Entity\Product\Product {#7311
    #id: 9319
    #code: "IEEE00002053"
    #attributes: Doctrine\ORM\PersistentCollection {#7701 …}
    #variants: Doctrine\ORM\PersistentCollection {#7744 …}
    #options: Doctrine\ORM\PersistentCollection {#7916 …}
    #associations: Doctrine\ORM\PersistentCollection {#7900 …}
    #createdAt: DateTime @1751038165 {#7274
      date: 2025-06-27 17:29:25.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#7322
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7922 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7921
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7311}
        #id: 32285
        #name: "IEEE 1364.1:2002"
        #slug: "ieee-1364-1-2002-ieee00002053-240971"
        #description: """
          New IEEE Standard - Inactive-Withdrawn.<br />\n
          Superseded by IEC/IEEE 62142-2005. To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standard IEEE 1364. To define syntax and semantics which can be used in common by all compliant RTL synthesis tools to achieve uniformity of results in a similar manner to which simulation tools currently use the IEEE 1364 standard. This will allow users of synthesis tools to produce well-defined designs whose functional characteristics are independent of any particular synthesis implementation by making their design compliant with this developed standard. Standard syntax and semantics for Verilog ® HDL-based RTL synthesis are described inthis standard.<br />\n
          \t\t\t\t<br />\n
          To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standard IEEE 1364.<br />\n
          To define syntax and semantics which can be used in common by all compliant RTL synthesis tools to achieve uniformity of results in a similar manner to which simulation tools currently use the IEEE 1364 standard. This will allow users of synthesis tools to produce well-defined designs whose functional characteristics are independent of any particular synthesis implementation by making their design compliant with this developed standard.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Verilog Register Transfer Level Synthesis"
        -notes: "Inactive-Withdrawn"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …}
    #channels: Doctrine\ORM\PersistentCollection {#7628 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7613 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7645 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1040166000 {#7318
      date: 2002-12-18 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: DateTime @1262991600 {#7316
      date: 2010-01-09 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1364.1"
    -bookCollection: ""
    -pageCount: 108
    -documents: Doctrine\ORM\PersistentCollection {#7465 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7500 …}
  }
]
Attributes
[]
Component
App\Twig\Components\ProductMostRecent {#93263
  +product: App\Entity\Product\Product {#7311
    #id: 9319
    #code: "IEEE00002053"
    #attributes: Doctrine\ORM\PersistentCollection {#7701 …}
    #variants: Doctrine\ORM\PersistentCollection {#7744 …}
    #options: Doctrine\ORM\PersistentCollection {#7916 …}
    #associations: Doctrine\ORM\PersistentCollection {#7900 …}
    #createdAt: DateTime @1751038165 {#7274
      date: 2025-06-27 17:29:25.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#7322
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7922 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7921
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7311}
        #id: 32285
        #name: "IEEE 1364.1:2002"
        #slug: "ieee-1364-1-2002-ieee00002053-240971"
        #description: """
          New IEEE Standard - Inactive-Withdrawn.<br />\n
          Superseded by IEC/IEEE 62142-2005. To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standard IEEE 1364. To define syntax and semantics which can be used in common by all compliant RTL synthesis tools to achieve uniformity of results in a similar manner to which simulation tools currently use the IEEE 1364 standard. This will allow users of synthesis tools to produce well-defined designs whose functional characteristics are independent of any particular synthesis implementation by making their design compliant with this developed standard. Standard syntax and semantics for Verilog ® HDL-based RTL synthesis are described inthis standard.<br />\n
          \t\t\t\t<br />\n
          To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standard IEEE 1364.<br />\n
          To define syntax and semantics which can be used in common by all compliant RTL synthesis tools to achieve uniformity of results in a similar manner to which simulation tools currently use the IEEE 1364 standard. This will allow users of synthesis tools to produce well-defined designs whose functional characteristics are independent of any particular synthesis implementation by making their design compliant with this developed standard.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Verilog Register Transfer Level Synthesis"
        -notes: "Inactive-Withdrawn"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …}
    #channels: Doctrine\ORM\PersistentCollection {#7628 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7613 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7645 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1040166000 {#7318
      date: 2002-12-18 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: DateTime @1262991600 {#7316
      date: 2010-01-09 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1364.1"
    -bookCollection: ""
    -pageCount: 108
    -documents: Doctrine\ORM\PersistentCollection {#7465 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7500 …}
  }
  +label: "Most Recent"
  +icon: "check-xs"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductState App\Twig\Components\ProductState 134.0 MiB 0.19 ms
Input props
[
  "product" => App\Entity\Product\Product {#7311
    #id: 9319
    #code: "IEEE00002053"
    #attributes: Doctrine\ORM\PersistentCollection {#7701 …}
    #variants: Doctrine\ORM\PersistentCollection {#7744 …}
    #options: Doctrine\ORM\PersistentCollection {#7916 …}
    #associations: Doctrine\ORM\PersistentCollection {#7900 …}
    #createdAt: DateTime @1751038165 {#7274
      date: 2025-06-27 17:29:25.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#7322
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7922 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7921
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7311}
        #id: 32285
        #name: "IEEE 1364.1:2002"
        #slug: "ieee-1364-1-2002-ieee00002053-240971"
        #description: """
          New IEEE Standard - Inactive-Withdrawn.<br />\n
          Superseded by IEC/IEEE 62142-2005. To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standard IEEE 1364. To define syntax and semantics which can be used in common by all compliant RTL synthesis tools to achieve uniformity of results in a similar manner to which simulation tools currently use the IEEE 1364 standard. This will allow users of synthesis tools to produce well-defined designs whose functional characteristics are independent of any particular synthesis implementation by making their design compliant with this developed standard. Standard syntax and semantics for Verilog ® HDL-based RTL synthesis are described inthis standard.<br />\n
          \t\t\t\t<br />\n
          To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standard IEEE 1364.<br />\n
          To define syntax and semantics which can be used in common by all compliant RTL synthesis tools to achieve uniformity of results in a similar manner to which simulation tools currently use the IEEE 1364 standard. This will allow users of synthesis tools to produce well-defined designs whose functional characteristics are independent of any particular synthesis implementation by making their design compliant with this developed standard.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Verilog Register Transfer Level Synthesis"
        -notes: "Inactive-Withdrawn"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …}
    #channels: Doctrine\ORM\PersistentCollection {#7628 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7613 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7645 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1040166000 {#7318
      date: 2002-12-18 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: DateTime @1262991600 {#7316
      date: 2010-01-09 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1364.1"
    -bookCollection: ""
    -pageCount: 108
    -documents: Doctrine\ORM\PersistentCollection {#7465 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7500 …}
  }
  "showFullLabel" => "true"
]
Attributes
[
  "showFullLabel" => "true"
]
Component
App\Twig\Components\ProductState {#100202
  +product: App\Entity\Product\Product {#7311
    #id: 9319
    #code: "IEEE00002053"
    #attributes: Doctrine\ORM\PersistentCollection {#7701 …}
    #variants: Doctrine\ORM\PersistentCollection {#7744 …}
    #options: Doctrine\ORM\PersistentCollection {#7916 …}
    #associations: Doctrine\ORM\PersistentCollection {#7900 …}
    #createdAt: DateTime @1751038165 {#7274
      date: 2025-06-27 17:29:25.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#7322
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7922 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7921
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7311}
        #id: 32285
        #name: "IEEE 1364.1:2002"
        #slug: "ieee-1364-1-2002-ieee00002053-240971"
        #description: """
          New IEEE Standard - Inactive-Withdrawn.<br />\n
          Superseded by IEC/IEEE 62142-2005. To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standard IEEE 1364. To define syntax and semantics which can be used in common by all compliant RTL synthesis tools to achieve uniformity of results in a similar manner to which simulation tools currently use the IEEE 1364 standard. This will allow users of synthesis tools to produce well-defined designs whose functional characteristics are independent of any particular synthesis implementation by making their design compliant with this developed standard. Standard syntax and semantics for Verilog ® HDL-based RTL synthesis are described inthis standard.<br />\n
          \t\t\t\t<br />\n
          To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standard IEEE 1364.<br />\n
          To define syntax and semantics which can be used in common by all compliant RTL synthesis tools to achieve uniformity of results in a similar manner to which simulation tools currently use the IEEE 1364 standard. This will allow users of synthesis tools to produce well-defined designs whose functional characteristics are independent of any particular synthesis implementation by making their design compliant with this developed standard.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Verilog Register Transfer Level Synthesis"
        -notes: "Inactive-Withdrawn"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …}
    #channels: Doctrine\ORM\PersistentCollection {#7628 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7613 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7645 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1040166000 {#7318
      date: 2002-12-18 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: DateTime @1262991600 {#7316
      date: 2010-01-09 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1364.1"
    -bookCollection: ""
    -pageCount: 108
    -documents: Doctrine\ORM\PersistentCollection {#7465 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7500 …}
  }
  +appearance: "state-withdrawn"
  +labels: [
    "Withdrawn"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductMostRecent App\Twig\Components\ProductMostRecent 134.0 MiB 0.71 ms
Input props
[
  "product" => App\Entity\Product\Product {#7311
    #id: 9319
    #code: "IEEE00002053"
    #attributes: Doctrine\ORM\PersistentCollection {#7701 …}
    #variants: Doctrine\ORM\PersistentCollection {#7744 …}
    #options: Doctrine\ORM\PersistentCollection {#7916 …}
    #associations: Doctrine\ORM\PersistentCollection {#7900 …}
    #createdAt: DateTime @1751038165 {#7274
      date: 2025-06-27 17:29:25.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#7322
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7922 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7921
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7311}
        #id: 32285
        #name: "IEEE 1364.1:2002"
        #slug: "ieee-1364-1-2002-ieee00002053-240971"
        #description: """
          New IEEE Standard - Inactive-Withdrawn.<br />\n
          Superseded by IEC/IEEE 62142-2005. To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standard IEEE 1364. To define syntax and semantics which can be used in common by all compliant RTL synthesis tools to achieve uniformity of results in a similar manner to which simulation tools currently use the IEEE 1364 standard. This will allow users of synthesis tools to produce well-defined designs whose functional characteristics are independent of any particular synthesis implementation by making their design compliant with this developed standard. Standard syntax and semantics for Verilog ® HDL-based RTL synthesis are described inthis standard.<br />\n
          \t\t\t\t<br />\n
          To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standard IEEE 1364.<br />\n
          To define syntax and semantics which can be used in common by all compliant RTL synthesis tools to achieve uniformity of results in a similar manner to which simulation tools currently use the IEEE 1364 standard. This will allow users of synthesis tools to produce well-defined designs whose functional characteristics are independent of any particular synthesis implementation by making their design compliant with this developed standard.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Verilog Register Transfer Level Synthesis"
        -notes: "Inactive-Withdrawn"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …}
    #channels: Doctrine\ORM\PersistentCollection {#7628 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7613 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7645 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1040166000 {#7318
      date: 2002-12-18 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: DateTime @1262991600 {#7316
      date: 2010-01-09 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1364.1"
    -bookCollection: ""
    -pageCount: 108
    -documents: Doctrine\ORM\PersistentCollection {#7465 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7500 …}
  }
]
Attributes
[]
Component
App\Twig\Components\ProductMostRecent {#100286
  +product: App\Entity\Product\Product {#7311
    #id: 9319
    #code: "IEEE00002053"
    #attributes: Doctrine\ORM\PersistentCollection {#7701 …}
    #variants: Doctrine\ORM\PersistentCollection {#7744 …}
    #options: Doctrine\ORM\PersistentCollection {#7916 …}
    #associations: Doctrine\ORM\PersistentCollection {#7900 …}
    #createdAt: DateTime @1751038165 {#7274
      date: 2025-06-27 17:29:25.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#7322
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7922 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7921
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7311}
        #id: 32285
        #name: "IEEE 1364.1:2002"
        #slug: "ieee-1364-1-2002-ieee00002053-240971"
        #description: """
          New IEEE Standard - Inactive-Withdrawn.<br />\n
          Superseded by IEC/IEEE 62142-2005. To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standard IEEE 1364. To define syntax and semantics which can be used in common by all compliant RTL synthesis tools to achieve uniformity of results in a similar manner to which simulation tools currently use the IEEE 1364 standard. This will allow users of synthesis tools to produce well-defined designs whose functional characteristics are independent of any particular synthesis implementation by making their design compliant with this developed standard. Standard syntax and semantics for Verilog ® HDL-based RTL synthesis are described inthis standard.<br />\n
          \t\t\t\t<br />\n
          To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standard IEEE 1364.<br />\n
          To define syntax and semantics which can be used in common by all compliant RTL synthesis tools to achieve uniformity of results in a similar manner to which simulation tools currently use the IEEE 1364 standard. This will allow users of synthesis tools to produce well-defined designs whose functional characteristics are independent of any particular synthesis implementation by making their design compliant with this developed standard.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Verilog Register Transfer Level Synthesis"
        -notes: "Inactive-Withdrawn"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …}
    #channels: Doctrine\ORM\PersistentCollection {#7628 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7613 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7645 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1040166000 {#7318
      date: 2002-12-18 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: DateTime @1262991600 {#7316
      date: 2010-01-09 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1364.1"
    -bookCollection: ""
    -pageCount: 108
    -documents: Doctrine\ORM\PersistentCollection {#7465 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7500 …}
  }
  +label: "Most Recent"
  +icon: "check-xs"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}