Symfony Profiler

[
  "product" => App\Entity\Product\Product {#7310
    #id: 9318
    #code: "IEEE00002052"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751038164 {#7274
      date: 2025-06-27 17:29:24.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969444 {#7322
      date: 2025-07-31 15:44:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 32281
        #name: "IEEE 1364:2001"
        #slug: "ieee-1364-2001-ieee00002052-240970"
        #description: """
          Revision Standard - Superseded.<br />\n
          Supersedes 1364-1995. The Verilog(R) Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable,it supports the development,verification, synthesis,and testing of hardware designs; the communication of hardware design data; and the maintenance,modification,and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.<br />\n
          \t\t\t\t<br />\n
          Verilog is a Hardware Description Language which was standardized as IEEE 1364-1995. It is currently used by integrated circuit designers to specify their designs at the switch, gate and RTL levels. The proposed project will revise Verilog 1364 to include new constructs which improve the utility of the language both at the detailed physical level and at high levels of abstraction to meet industry needs for improved design technology.<br />\n
          To provide an industry standard based on the Verilog Hardware Description Language.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Verilog Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1743289200 {#7317
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1001628000 {#7318
      date: 2001-09-28 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 792
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  "showFullLabel" => "true"
]

[
  "showFullLabel" => "true"
]

App\Twig\Components\ProductState {#93007
  +product: App\Entity\Product\Product {#7310
    #id: 9318
    #code: "IEEE00002052"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751038164 {#7274
      date: 2025-06-27 17:29:24.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969444 {#7322
      date: 2025-07-31 15:44:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 32281
        #name: "IEEE 1364:2001"
        #slug: "ieee-1364-2001-ieee00002052-240970"
        #description: """
          Revision Standard - Superseded.<br />\n
          Supersedes 1364-1995. The Verilog(R) Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable,it supports the development,verification, synthesis,and testing of hardware designs; the communication of hardware design data; and the maintenance,modification,and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.<br />\n
          \t\t\t\t<br />\n
          Verilog is a Hardware Description Language which was standardized as IEEE 1364-1995. It is currently used by integrated circuit designers to specify their designs at the switch, gate and RTL levels. The proposed project will revise Verilog 1364 to include new constructs which improve the utility of the language both at the detailed physical level and at high levels of abstraction to meet industry needs for improved design technology.<br />\n
          To provide an industry standard based on the Verilog Hardware Description Language.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Verilog Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1743289200 {#7317
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1001628000 {#7318
      date: 2001-09-28 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 792
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

[
  "product" => App\Entity\Product\Product {#7310
    #id: 9318
    #code: "IEEE00002052"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751038164 {#7274
      date: 2025-06-27 17:29:24.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969444 {#7322
      date: 2025-07-31 15:44:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 32281
        #name: "IEEE 1364:2001"
        #slug: "ieee-1364-2001-ieee00002052-240970"
        #description: """
          Revision Standard - Superseded.<br />\n
          Supersedes 1364-1995. The Verilog(R) Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable,it supports the development,verification, synthesis,and testing of hardware designs; the communication of hardware design data; and the maintenance,modification,and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.<br />\n
          \t\t\t\t<br />\n
          Verilog is a Hardware Description Language which was standardized as IEEE 1364-1995. It is currently used by integrated circuit designers to specify their designs at the switch, gate and RTL levels. The proposed project will revise Verilog 1364 to include new constructs which improve the utility of the language both at the detailed physical level and at high levels of abstraction to meet industry needs for improved design technology.<br />\n
          To provide an industry standard based on the Verilog Hardware Description Language.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Verilog Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1743289200 {#7317
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1001628000 {#7318
      date: 2001-09-28 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 792
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
]

App\Twig\Components\ProductType {#93187
  +product: App\Entity\Product\Product {#7310
    #id: 9318
    #code: "IEEE00002052"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751038164 {#7274
      date: 2025-06-27 17:29:24.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969444 {#7322
      date: 2025-07-31 15:44:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 32281
        #name: "IEEE 1364:2001"
        #slug: "ieee-1364-2001-ieee00002052-240970"
        #description: """
          Revision Standard - Superseded.<br />\n
          Supersedes 1364-1995. The Verilog(R) Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable,it supports the development,verification, synthesis,and testing of hardware designs; the communication of hardware design data; and the maintenance,modification,and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.<br />\n
          \t\t\t\t<br />\n
          Verilog is a Hardware Description Language which was standardized as IEEE 1364-1995. It is currently used by integrated circuit designers to specify their designs at the switch, gate and RTL levels. The proposed project will revise Verilog 1364 to include new constructs which improve the utility of the language both at the detailed physical level and at high levels of abstraction to meet industry needs for improved design technology.<br />\n
          To provide an industry standard based on the Verilog Hardware Description Language.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Verilog Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1743289200 {#7317
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1001628000 {#7318
      date: 2001-09-28 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 792
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +label: "Standard"
  -typeAttributeCode: "type"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

[
  "product" => App\Entity\Product\Product {#7310
    #id: 9318
    #code: "IEEE00002052"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751038164 {#7274
      date: 2025-06-27 17:29:24.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969444 {#7322
      date: 2025-07-31 15:44:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 32281
        #name: "IEEE 1364:2001"
        #slug: "ieee-1364-2001-ieee00002052-240970"
        #description: """
          Revision Standard - Superseded.<br />\n
          Supersedes 1364-1995. The Verilog(R) Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable,it supports the development,verification, synthesis,and testing of hardware designs; the communication of hardware design data; and the maintenance,modification,and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.<br />\n
          \t\t\t\t<br />\n
          Verilog is a Hardware Description Language which was standardized as IEEE 1364-1995. It is currently used by integrated circuit designers to specify their designs at the switch, gate and RTL levels. The proposed project will revise Verilog 1364 to include new constructs which improve the utility of the language both at the detailed physical level and at high levels of abstraction to meet industry needs for improved design technology.<br />\n
          To provide an industry standard based on the Verilog Hardware Description Language.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Verilog Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1743289200 {#7317
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1001628000 {#7318
      date: 2001-09-28 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 792
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
]

App\Twig\Components\ProductMostRecent {#93262
  +product: App\Entity\Product\Product {#7310
    #id: 9318
    #code: "IEEE00002052"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751038164 {#7274
      date: 2025-06-27 17:29:24.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969444 {#7322
      date: 2025-07-31 15:44:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 32281
        #name: "IEEE 1364:2001"
        #slug: "ieee-1364-2001-ieee00002052-240970"
        #description: """
          Revision Standard - Superseded.<br />\n
          Supersedes 1364-1995. The Verilog(R) Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable,it supports the development,verification, synthesis,and testing of hardware designs; the communication of hardware design data; and the maintenance,modification,and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.<br />\n
          \t\t\t\t<br />\n
          Verilog is a Hardware Description Language which was standardized as IEEE 1364-1995. It is currently used by integrated circuit designers to specify their designs at the switch, gate and RTL levels. The proposed project will revise Verilog 1364 to include new constructs which improve the utility of the language both at the detailed physical level and at high levels of abstraction to meet industry needs for improved design technology.<br />\n
          To provide an industry standard based on the Verilog Hardware Description Language.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Verilog Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1743289200 {#7317
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1001628000 {#7318
      date: 2001-09-28 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 792
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +label: "Historical"
  +icon: "historical"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

[
  "product" => App\Entity\Product\Product {#106821
    #id: 9317
    #code: "IEEE00002051"
    #attributes: Doctrine\ORM\PersistentCollection {#106804 …}
    #variants: Doctrine\ORM\PersistentCollection {#106801 …}
    #options: Doctrine\ORM\PersistentCollection {#106797 …}
    #associations: Doctrine\ORM\PersistentCollection {#106799 …}
    #createdAt: DateTime @1751038164 {#106829
      date: 2025-06-27 17:29:24.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#106802
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106815 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#106854
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106821}
        #id: 32277
        #name: "IEEE 1364:1995"
        #slug: "ieee-1364-1995-ieee00002051-240969"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          The Verilog Hardware Description Language (HDL) is defined. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.<br />\n
          \t\t\t\t<br />\n
          The intent of this standard is to serve as a complete specification of the Verilog Hardware Description Language (HDL). This document contains:<br />\n
          -- The formal syntax and semantics of all Verilog HDL construct; s<br />\n
          -- Simulation system tasks and functions, such as text output display commands;<br />\n
          -- Compiler directives, such as text substitution macros and simulation time scaling;<br />\n
          -- The Programming Language Interface (PLI) binding mechanism;<br />\n
          -- The formal syntax and semantics of access routines, task/function routines, and Verilog procedural interface routines;<br />\n
          -- Informative usage examples;<br />\n
          -- Listings of header Þles for PLI
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Hardware Description Language Based on the Verilog(R) Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106812 …}
    #channels: Doctrine\ORM\PersistentCollection {#106806 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106810 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106808 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106822 …}
    -apiLastModifiedAt: DateTime @1754517600 {#106789
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#106828
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @845244000 {#106827
      date: 1996-10-14 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 688
    -documents: Doctrine\ORM\PersistentCollection {#106819 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106817 …}
  }
  "showFullLabel" => "true"
]

[
  "showFullLabel" => "true"
]

App\Twig\Components\ProductState {#106837
  +product: App\Entity\Product\Product {#106821
    #id: 9317
    #code: "IEEE00002051"
    #attributes: Doctrine\ORM\PersistentCollection {#106804 …}
    #variants: Doctrine\ORM\PersistentCollection {#106801 …}
    #options: Doctrine\ORM\PersistentCollection {#106797 …}
    #associations: Doctrine\ORM\PersistentCollection {#106799 …}
    #createdAt: DateTime @1751038164 {#106829
      date: 2025-06-27 17:29:24.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#106802
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106815 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#106854
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106821}
        #id: 32277
        #name: "IEEE 1364:1995"
        #slug: "ieee-1364-1995-ieee00002051-240969"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          The Verilog Hardware Description Language (HDL) is defined. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.<br />\n
          \t\t\t\t<br />\n
          The intent of this standard is to serve as a complete specification of the Verilog Hardware Description Language (HDL). This document contains:<br />\n
          -- The formal syntax and semantics of all Verilog HDL construct; s<br />\n
          -- Simulation system tasks and functions, such as text output display commands;<br />\n
          -- Compiler directives, such as text substitution macros and simulation time scaling;<br />\n
          -- The Programming Language Interface (PLI) binding mechanism;<br />\n
          -- The formal syntax and semantics of access routines, task/function routines, and Verilog procedural interface routines;<br />\n
          -- Informative usage examples;<br />\n
          -- Listings of header Þles for PLI
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Hardware Description Language Based on the Verilog(R) Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106812 …}
    #channels: Doctrine\ORM\PersistentCollection {#106806 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106810 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106808 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106822 …}
    -apiLastModifiedAt: DateTime @1754517600 {#106789
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#106828
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @845244000 {#106827
      date: 1996-10-14 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 688
    -documents: Doctrine\ORM\PersistentCollection {#106819 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106817 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

[
  "product" => App\Entity\Product\Product {#106821
    #id: 9317
    #code: "IEEE00002051"
    #attributes: Doctrine\ORM\PersistentCollection {#106804 …}
    #variants: Doctrine\ORM\PersistentCollection {#106801 …}
    #options: Doctrine\ORM\PersistentCollection {#106797 …}
    #associations: Doctrine\ORM\PersistentCollection {#106799 …}
    #createdAt: DateTime @1751038164 {#106829
      date: 2025-06-27 17:29:24.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#106802
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106815 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#106854
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106821}
        #id: 32277
        #name: "IEEE 1364:1995"
        #slug: "ieee-1364-1995-ieee00002051-240969"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          The Verilog Hardware Description Language (HDL) is defined. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.<br />\n
          \t\t\t\t<br />\n
          The intent of this standard is to serve as a complete specification of the Verilog Hardware Description Language (HDL). This document contains:<br />\n
          -- The formal syntax and semantics of all Verilog HDL construct; s<br />\n
          -- Simulation system tasks and functions, such as text output display commands;<br />\n
          -- Compiler directives, such as text substitution macros and simulation time scaling;<br />\n
          -- The Programming Language Interface (PLI) binding mechanism;<br />\n
          -- The formal syntax and semantics of access routines, task/function routines, and Verilog procedural interface routines;<br />\n
          -- Informative usage examples;<br />\n
          -- Listings of header Þles for PLI
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Hardware Description Language Based on the Verilog(R) Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106812 …}
    #channels: Doctrine\ORM\PersistentCollection {#106806 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106810 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106808 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106822 …}
    -apiLastModifiedAt: DateTime @1754517600 {#106789
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#106828
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @845244000 {#106827
      date: 1996-10-14 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 688
    -documents: Doctrine\ORM\PersistentCollection {#106819 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106817 …}
  }
]

App\Twig\Components\ProductMostRecent {#106936
  +product: App\Entity\Product\Product {#106821
    #id: 9317
    #code: "IEEE00002051"
    #attributes: Doctrine\ORM\PersistentCollection {#106804 …}
    #variants: Doctrine\ORM\PersistentCollection {#106801 …}
    #options: Doctrine\ORM\PersistentCollection {#106797 …}
    #associations: Doctrine\ORM\PersistentCollection {#106799 …}
    #createdAt: DateTime @1751038164 {#106829
      date: 2025-06-27 17:29:24.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#106802
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106815 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#106854
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106821}
        #id: 32277
        #name: "IEEE 1364:1995"
        #slug: "ieee-1364-1995-ieee00002051-240969"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          The Verilog Hardware Description Language (HDL) is defined. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.<br />\n
          \t\t\t\t<br />\n
          The intent of this standard is to serve as a complete specification of the Verilog Hardware Description Language (HDL). This document contains:<br />\n
          -- The formal syntax and semantics of all Verilog HDL construct; s<br />\n
          -- Simulation system tasks and functions, such as text output display commands;<br />\n
          -- Compiler directives, such as text substitution macros and simulation time scaling;<br />\n
          -- The Programming Language Interface (PLI) binding mechanism;<br />\n
          -- The formal syntax and semantics of access routines, task/function routines, and Verilog procedural interface routines;<br />\n
          -- Informative usage examples;<br />\n
          -- Listings of header Þles for PLI
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Hardware Description Language Based on the Verilog(R) Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106812 …}
    #channels: Doctrine\ORM\PersistentCollection {#106806 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106810 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106808 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106822 …}
    -apiLastModifiedAt: DateTime @1754517600 {#106789
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#106828
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @845244000 {#106827
      date: 1996-10-14 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 688
    -documents: Doctrine\ORM\PersistentCollection {#106819 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106817 …}
  }
  +label: "Historical"
  +icon: "historical"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

[
  "product" => App\Entity\Product\Product {#93685
    #id: 10103
    #code: "IEEE00003641"
    #attributes: Doctrine\ORM\PersistentCollection {#93667 …}
    #variants: Doctrine\ORM\PersistentCollection {#93664 …}
    #options: Doctrine\ORM\PersistentCollection {#93660 …}
    #associations: Doctrine\ORM\PersistentCollection {#93662 …}
    #createdAt: DateTime @1751038817 {#93693
      date: 2025-06-27 17:40:17.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#93672
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#93678 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#93713
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#93685}
        #id: 35421
        #name: "IEEE 1364:2005"
        #slug: "ieee-1364-2005-ieee00003641-241755"
        #description: """
          Revision Standard - Superseded.<br />\n
          The Verilog hardware description language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementers of tools supporting the language and advanced users of the language.<br />\n
          (Supersedes IEEE Std 1364-2001. Superseded by IEEE Std 1800-2009).<br />\n
          \t\t\t\t<br />\n
          Verilog is a hardware description language (HDL) that was standardized as IEEE Std 1364™-1995 and first revised as IEEE Std 1364-2001. This revision corrects and clarifies features ambiguously described in the 1995 and 2001 editions. It also resolves incompatibilities and inconsistencies of IEEE 1364-2001 with IEEE Std 1800™-2005.<br />\n
          The intent of this standard is to serve as a complete specification of the Verilog HDL. This standard contains the following:<br />\n
          — The formal syntax and semantics of all Verilog HDL constructs<br />\n
          — The formal syntax and semantics of standard delay format (SDF) constructs<br />\n
          — Simulation system tasks and functions, such as text output display commands<br />\n
          — Compiler directives, such as text substitution macros and simulation time scaling<br />\n
          — The programming language interface (PLI) binding mechanism<br />\n
          — The formal syntax and semantics of the Verilog procedural interface (VPI)<br />\n
          — Informative usage examples<br />\n
          — Informative delay model for SDF<br />\n
          — The VPI header file<br />\n
          The purpose of the original document, IEEE Std 1364-2001, was to provide an industry standard based on the Verilog Hardware Description Language. The reason for the document's revision is to incorporate corrections that have been identified by the working group since 1364-1995 and 1364-2001 were published by the IEEE.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Verilog Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#93676 …}
    #channels: Doctrine\ORM\PersistentCollection {#93669 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#93674 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#93671 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#93686 …}
    -apiLastModifiedAt: DateTime @1754517600 {#93656
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1616454000 {#93692
      date: 2021-03-23 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1144360800 {#93691
      date: 2006-04-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 590
    -documents: Doctrine\ORM\PersistentCollection {#93682 …}
    -favorites: Doctrine\ORM\PersistentCollection {#93680 …}
  }
  "showFullLabel" => "true"
]

[
  "showFullLabel" => "true"
]

App\Twig\Components\ProductState {#113545
  +product: App\Entity\Product\Product {#93685
    #id: 10103
    #code: "IEEE00003641"
    #attributes: Doctrine\ORM\PersistentCollection {#93667 …}
    #variants: Doctrine\ORM\PersistentCollection {#93664 …}
    #options: Doctrine\ORM\PersistentCollection {#93660 …}
    #associations: Doctrine\ORM\PersistentCollection {#93662 …}
    #createdAt: DateTime @1751038817 {#93693
      date: 2025-06-27 17:40:17.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#93672
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#93678 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#93713
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#93685}
        #id: 35421
        #name: "IEEE 1364:2005"
        #slug: "ieee-1364-2005-ieee00003641-241755"
        #description: """
          Revision Standard - Superseded.<br />\n
          The Verilog hardware description language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementers of tools supporting the language and advanced users of the language.<br />\n
          (Supersedes IEEE Std 1364-2001. Superseded by IEEE Std 1800-2009).<br />\n
          \t\t\t\t<br />\n
          Verilog is a hardware description language (HDL) that was standardized as IEEE Std 1364™-1995 and first revised as IEEE Std 1364-2001. This revision corrects and clarifies features ambiguously described in the 1995 and 2001 editions. It also resolves incompatibilities and inconsistencies of IEEE 1364-2001 with IEEE Std 1800™-2005.<br />\n
          The intent of this standard is to serve as a complete specification of the Verilog HDL. This standard contains the following:<br />\n
          — The formal syntax and semantics of all Verilog HDL constructs<br />\n
          — The formal syntax and semantics of standard delay format (SDF) constructs<br />\n
          — Simulation system tasks and functions, such as text output display commands<br />\n
          — Compiler directives, such as text substitution macros and simulation time scaling<br />\n
          — The programming language interface (PLI) binding mechanism<br />\n
          — The formal syntax and semantics of the Verilog procedural interface (VPI)<br />\n
          — Informative usage examples<br />\n
          — Informative delay model for SDF<br />\n
          — The VPI header file<br />\n
          The purpose of the original document, IEEE Std 1364-2001, was to provide an industry standard based on the Verilog Hardware Description Language. The reason for the document's revision is to incorporate corrections that have been identified by the working group since 1364-1995 and 1364-2001 were published by the IEEE.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Verilog Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#93676 …}
    #channels: Doctrine\ORM\PersistentCollection {#93669 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#93674 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#93671 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#93686 …}
    -apiLastModifiedAt: DateTime @1754517600 {#93656
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1616454000 {#93692
      date: 2021-03-23 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1144360800 {#93691
      date: 2006-04-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 590
    -documents: Doctrine\ORM\PersistentCollection {#93682 …}
    -favorites: Doctrine\ORM\PersistentCollection {#93680 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

[
  "product" => App\Entity\Product\Product {#93685
    #id: 10103
    #code: "IEEE00003641"
    #attributes: Doctrine\ORM\PersistentCollection {#93667 …}
    #variants: Doctrine\ORM\PersistentCollection {#93664 …}
    #options: Doctrine\ORM\PersistentCollection {#93660 …}
    #associations: Doctrine\ORM\PersistentCollection {#93662 …}
    #createdAt: DateTime @1751038817 {#93693
      date: 2025-06-27 17:40:17.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#93672
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#93678 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#93713
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#93685}
        #id: 35421
        #name: "IEEE 1364:2005"
        #slug: "ieee-1364-2005-ieee00003641-241755"
        #description: """
          Revision Standard - Superseded.<br />\n
          The Verilog hardware description language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementers of tools supporting the language and advanced users of the language.<br />\n
          (Supersedes IEEE Std 1364-2001. Superseded by IEEE Std 1800-2009).<br />\n
          \t\t\t\t<br />\n
          Verilog is a hardware description language (HDL) that was standardized as IEEE Std 1364™-1995 and first revised as IEEE Std 1364-2001. This revision corrects and clarifies features ambiguously described in the 1995 and 2001 editions. It also resolves incompatibilities and inconsistencies of IEEE 1364-2001 with IEEE Std 1800™-2005.<br />\n
          The intent of this standard is to serve as a complete specification of the Verilog HDL. This standard contains the following:<br />\n
          — The formal syntax and semantics of all Verilog HDL constructs<br />\n
          — The formal syntax and semantics of standard delay format (SDF) constructs<br />\n
          — Simulation system tasks and functions, such as text output display commands<br />\n
          — Compiler directives, such as text substitution macros and simulation time scaling<br />\n
          — The programming language interface (PLI) binding mechanism<br />\n
          — The formal syntax and semantics of the Verilog procedural interface (VPI)<br />\n
          — Informative usage examples<br />\n
          — Informative delay model for SDF<br />\n
          — The VPI header file<br />\n
          The purpose of the original document, IEEE Std 1364-2001, was to provide an industry standard based on the Verilog Hardware Description Language. The reason for the document's revision is to incorporate corrections that have been identified by the working group since 1364-1995 and 1364-2001 were published by the IEEE.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Verilog Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#93676 …}
    #channels: Doctrine\ORM\PersistentCollection {#93669 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#93674 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#93671 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#93686 …}
    -apiLastModifiedAt: DateTime @1754517600 {#93656
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1616454000 {#93692
      date: 2021-03-23 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1144360800 {#93691
      date: 2006-04-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 590
    -documents: Doctrine\ORM\PersistentCollection {#93682 …}
    -favorites: Doctrine\ORM\PersistentCollection {#93680 …}
  }
]

App\Twig\Components\ProductMostRecent {#113612
  +product: App\Entity\Product\Product {#93685
    #id: 10103
    #code: "IEEE00003641"
    #attributes: Doctrine\ORM\PersistentCollection {#93667 …}
    #variants: Doctrine\ORM\PersistentCollection {#93664 …}
    #options: Doctrine\ORM\PersistentCollection {#93660 …}
    #associations: Doctrine\ORM\PersistentCollection {#93662 …}
    #createdAt: DateTime @1751038817 {#93693
      date: 2025-06-27 17:40:17.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#93672
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#93678 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#93713
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#93685}
        #id: 35421
        #name: "IEEE 1364:2005"
        #slug: "ieee-1364-2005-ieee00003641-241755"
        #description: """
          Revision Standard - Superseded.<br />\n
          The Verilog hardware description language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementers of tools supporting the language and advanced users of the language.<br />\n
          (Supersedes IEEE Std 1364-2001. Superseded by IEEE Std 1800-2009).<br />\n
          \t\t\t\t<br />\n
          Verilog is a hardware description language (HDL) that was standardized as IEEE Std 1364™-1995 and first revised as IEEE Std 1364-2001. This revision corrects and clarifies features ambiguously described in the 1995 and 2001 editions. It also resolves incompatibilities and inconsistencies of IEEE 1364-2001 with IEEE Std 1800™-2005.<br />\n
          The intent of this standard is to serve as a complete specification of the Verilog HDL. This standard contains the following:<br />\n
          — The formal syntax and semantics of all Verilog HDL constructs<br />\n
          — The formal syntax and semantics of standard delay format (SDF) constructs<br />\n
          — Simulation system tasks and functions, such as text output display commands<br />\n
          — Compiler directives, such as text substitution macros and simulation time scaling<br />\n
          — The programming language interface (PLI) binding mechanism<br />\n
          — The formal syntax and semantics of the Verilog procedural interface (VPI)<br />\n
          — Informative usage examples<br />\n
          — Informative delay model for SDF<br />\n
          — The VPI header file<br />\n
          The purpose of the original document, IEEE Std 1364-2001, was to provide an industry standard based on the Verilog Hardware Description Language. The reason for the document's revision is to incorporate corrections that have been identified by the working group since 1364-1995 and 1364-2001 were published by the IEEE.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Verilog Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#93676 …}
    #channels: Doctrine\ORM\PersistentCollection {#93669 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#93674 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#93671 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#93686 …}
    -apiLastModifiedAt: DateTime @1754517600 {#93656
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1616454000 {#93692
      date: 2021-03-23 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1144360800 {#93691
      date: 2006-04-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 590
    -documents: Doctrine\ORM\PersistentCollection {#93682 …}
    -favorites: Doctrine\ORM\PersistentCollection {#93680 …}
  }
  +label: "Historical"
  +icon: "historical"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

[
  "product" => App\Entity\Product\Product {#7310
    #id: 9318
    #code: "IEEE00002052"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751038164 {#7274
      date: 2025-06-27 17:29:24.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969444 {#7322
      date: 2025-07-31 15:44:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 32281
        #name: "IEEE 1364:2001"
        #slug: "ieee-1364-2001-ieee00002052-240970"
        #description: """
          Revision Standard - Superseded.<br />\n
          Supersedes 1364-1995. The Verilog(R) Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable,it supports the development,verification, synthesis,and testing of hardware designs; the communication of hardware design data; and the maintenance,modification,and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.<br />\n
          \t\t\t\t<br />\n
          Verilog is a Hardware Description Language which was standardized as IEEE 1364-1995. It is currently used by integrated circuit designers to specify their designs at the switch, gate and RTL levels. The proposed project will revise Verilog 1364 to include new constructs which improve the utility of the language both at the detailed physical level and at high levels of abstraction to meet industry needs for improved design technology.<br />\n
          To provide an industry standard based on the Verilog Hardware Description Language.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Verilog Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1743289200 {#7317
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1001628000 {#7318
      date: 2001-09-28 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 792
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  "showFullLabel" => "true"
]

[
  "showFullLabel" => "true"
]

App\Twig\Components\ProductState {#113677
  +product: App\Entity\Product\Product {#7310
    #id: 9318
    #code: "IEEE00002052"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751038164 {#7274
      date: 2025-06-27 17:29:24.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969444 {#7322
      date: 2025-07-31 15:44:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 32281
        #name: "IEEE 1364:2001"
        #slug: "ieee-1364-2001-ieee00002052-240970"
        #description: """
          Revision Standard - Superseded.<br />\n
          Supersedes 1364-1995. The Verilog(R) Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable,it supports the development,verification, synthesis,and testing of hardware designs; the communication of hardware design data; and the maintenance,modification,and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.<br />\n
          \t\t\t\t<br />\n
          Verilog is a Hardware Description Language which was standardized as IEEE 1364-1995. It is currently used by integrated circuit designers to specify their designs at the switch, gate and RTL levels. The proposed project will revise Verilog 1364 to include new constructs which improve the utility of the language both at the detailed physical level and at high levels of abstraction to meet industry needs for improved design technology.<br />\n
          To provide an industry standard based on the Verilog Hardware Description Language.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Verilog Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1743289200 {#7317
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1001628000 {#7318
      date: 2001-09-28 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 792
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

[
  "product" => App\Entity\Product\Product {#7310
    #id: 9318
    #code: "IEEE00002052"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751038164 {#7274
      date: 2025-06-27 17:29:24.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969444 {#7322
      date: 2025-07-31 15:44:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 32281
        #name: "IEEE 1364:2001"
        #slug: "ieee-1364-2001-ieee00002052-240970"
        #description: """
          Revision Standard - Superseded.<br />\n
          Supersedes 1364-1995. The Verilog(R) Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable,it supports the development,verification, synthesis,and testing of hardware designs; the communication of hardware design data; and the maintenance,modification,and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.<br />\n
          \t\t\t\t<br />\n
          Verilog is a Hardware Description Language which was standardized as IEEE 1364-1995. It is currently used by integrated circuit designers to specify their designs at the switch, gate and RTL levels. The proposed project will revise Verilog 1364 to include new constructs which improve the utility of the language both at the detailed physical level and at high levels of abstraction to meet industry needs for improved design technology.<br />\n
          To provide an industry standard based on the Verilog Hardware Description Language.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Verilog Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1743289200 {#7317
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1001628000 {#7318
      date: 2001-09-28 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 792
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
]

App\Twig\Components\ProductMostRecent {#113704
  +product: App\Entity\Product\Product {#7310
    #id: 9318
    #code: "IEEE00002052"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751038164 {#7274
      date: 2025-06-27 17:29:24.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969444 {#7322
      date: 2025-07-31 15:44:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 32281
        #name: "IEEE 1364:2001"
        #slug: "ieee-1364-2001-ieee00002052-240970"
        #description: """
          Revision Standard - Superseded.<br />\n
          Supersedes 1364-1995. The Verilog(R) Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable,it supports the development,verification, synthesis,and testing of hardware designs; the communication of hardware design data; and the maintenance,modification,and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.<br />\n
          \t\t\t\t<br />\n
          Verilog is a Hardware Description Language which was standardized as IEEE 1364-1995. It is currently used by integrated circuit designers to specify their designs at the switch, gate and RTL levels. The proposed project will revise Verilog 1364 to include new constructs which improve the utility of the language both at the detailed physical level and at high levels of abstraction to meet industry needs for improved design technology.<br />\n
          To provide an industry standard based on the Verilog Hardware Description Language.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Verilog Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1743289200 {#7317
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1001628000 {#7318
      date: 2001-09-28 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 792
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +label: "Historical"
  +icon: "historical"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

[
  "product" => App\Entity\Product\Product {#106821
    #id: 9317
    #code: "IEEE00002051"
    #attributes: Doctrine\ORM\PersistentCollection {#106804 …}
    #variants: Doctrine\ORM\PersistentCollection {#106801 …}
    #options: Doctrine\ORM\PersistentCollection {#106797 …}
    #associations: Doctrine\ORM\PersistentCollection {#106799 …}
    #createdAt: DateTime @1751038164 {#106829
      date: 2025-06-27 17:29:24.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#106802
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106815 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#106854
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106821}
        #id: 32277
        #name: "IEEE 1364:1995"
        #slug: "ieee-1364-1995-ieee00002051-240969"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          The Verilog Hardware Description Language (HDL) is defined. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.<br />\n
          \t\t\t\t<br />\n
          The intent of this standard is to serve as a complete specification of the Verilog Hardware Description Language (HDL). This document contains:<br />\n
          -- The formal syntax and semantics of all Verilog HDL construct; s<br />\n
          -- Simulation system tasks and functions, such as text output display commands;<br />\n
          -- Compiler directives, such as text substitution macros and simulation time scaling;<br />\n
          -- The Programming Language Interface (PLI) binding mechanism;<br />\n
          -- The formal syntax and semantics of access routines, task/function routines, and Verilog procedural interface routines;<br />\n
          -- Informative usage examples;<br />\n
          -- Listings of header Þles for PLI
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Hardware Description Language Based on the Verilog(R) Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106812 …}
    #channels: Doctrine\ORM\PersistentCollection {#106806 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106810 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106808 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106822 …}
    -apiLastModifiedAt: DateTime @1754517600 {#106789
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#106828
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @845244000 {#106827
      date: 1996-10-14 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 688
    -documents: Doctrine\ORM\PersistentCollection {#106819 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106817 …}
  }
  "showFullLabel" => "true"
]

[
  "showFullLabel" => "true"
]

App\Twig\Components\ProductState {#113768
  +product: App\Entity\Product\Product {#106821
    #id: 9317
    #code: "IEEE00002051"
    #attributes: Doctrine\ORM\PersistentCollection {#106804 …}
    #variants: Doctrine\ORM\PersistentCollection {#106801 …}
    #options: Doctrine\ORM\PersistentCollection {#106797 …}
    #associations: Doctrine\ORM\PersistentCollection {#106799 …}
    #createdAt: DateTime @1751038164 {#106829
      date: 2025-06-27 17:29:24.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#106802
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106815 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#106854
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106821}
        #id: 32277
        #name: "IEEE 1364:1995"
        #slug: "ieee-1364-1995-ieee00002051-240969"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          The Verilog Hardware Description Language (HDL) is defined. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.<br />\n
          \t\t\t\t<br />\n
          The intent of this standard is to serve as a complete specification of the Verilog Hardware Description Language (HDL). This document contains:<br />\n
          -- The formal syntax and semantics of all Verilog HDL construct; s<br />\n
          -- Simulation system tasks and functions, such as text output display commands;<br />\n
          -- Compiler directives, such as text substitution macros and simulation time scaling;<br />\n
          -- The Programming Language Interface (PLI) binding mechanism;<br />\n
          -- The formal syntax and semantics of access routines, task/function routines, and Verilog procedural interface routines;<br />\n
          -- Informative usage examples;<br />\n
          -- Listings of header Þles for PLI
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Hardware Description Language Based on the Verilog(R) Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106812 …}
    #channels: Doctrine\ORM\PersistentCollection {#106806 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106810 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106808 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106822 …}
    -apiLastModifiedAt: DateTime @1754517600 {#106789
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#106828
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @845244000 {#106827
      date: 1996-10-14 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 688
    -documents: Doctrine\ORM\PersistentCollection {#106819 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106817 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

[
  "product" => App\Entity\Product\Product {#106821
    #id: 9317
    #code: "IEEE00002051"
    #attributes: Doctrine\ORM\PersistentCollection {#106804 …}
    #variants: Doctrine\ORM\PersistentCollection {#106801 …}
    #options: Doctrine\ORM\PersistentCollection {#106797 …}
    #associations: Doctrine\ORM\PersistentCollection {#106799 …}
    #createdAt: DateTime @1751038164 {#106829
      date: 2025-06-27 17:29:24.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#106802
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106815 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#106854
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106821}
        #id: 32277
        #name: "IEEE 1364:1995"
        #slug: "ieee-1364-1995-ieee00002051-240969"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          The Verilog Hardware Description Language (HDL) is defined. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.<br />\n
          \t\t\t\t<br />\n
          The intent of this standard is to serve as a complete specification of the Verilog Hardware Description Language (HDL). This document contains:<br />\n
          -- The formal syntax and semantics of all Verilog HDL construct; s<br />\n
          -- Simulation system tasks and functions, such as text output display commands;<br />\n
          -- Compiler directives, such as text substitution macros and simulation time scaling;<br />\n
          -- The Programming Language Interface (PLI) binding mechanism;<br />\n
          -- The formal syntax and semantics of access routines, task/function routines, and Verilog procedural interface routines;<br />\n
          -- Informative usage examples;<br />\n
          -- Listings of header Þles for PLI
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Hardware Description Language Based on the Verilog(R) Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106812 …}
    #channels: Doctrine\ORM\PersistentCollection {#106806 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106810 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106808 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106822 …}
    -apiLastModifiedAt: DateTime @1754517600 {#106789
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#106828
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @845244000 {#106827
      date: 1996-10-14 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 688
    -documents: Doctrine\ORM\PersistentCollection {#106819 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106817 …}
  }
]

App\Twig\Components\ProductMostRecent {#113795
  +product: App\Entity\Product\Product {#106821
    #id: 9317
    #code: "IEEE00002051"
    #attributes: Doctrine\ORM\PersistentCollection {#106804 …}
    #variants: Doctrine\ORM\PersistentCollection {#106801 …}
    #options: Doctrine\ORM\PersistentCollection {#106797 …}
    #associations: Doctrine\ORM\PersistentCollection {#106799 …}
    #createdAt: DateTime @1751038164 {#106829
      date: 2025-06-27 17:29:24.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#106802
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106815 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#106854
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106821}
        #id: 32277
        #name: "IEEE 1364:1995"
        #slug: "ieee-1364-1995-ieee00002051-240969"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          The Verilog Hardware Description Language (HDL) is defined. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.<br />\n
          \t\t\t\t<br />\n
          The intent of this standard is to serve as a complete specification of the Verilog Hardware Description Language (HDL). This document contains:<br />\n
          -- The formal syntax and semantics of all Verilog HDL construct; s<br />\n
          -- Simulation system tasks and functions, such as text output display commands;<br />\n
          -- Compiler directives, such as text substitution macros and simulation time scaling;<br />\n
          -- The Programming Language Interface (PLI) binding mechanism;<br />\n
          -- The formal syntax and semantics of access routines, task/function routines, and Verilog procedural interface routines;<br />\n
          -- Informative usage examples;<br />\n
          -- Listings of header Þles for PLI
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Hardware Description Language Based on the Verilog(R) Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106812 …}
    #channels: Doctrine\ORM\PersistentCollection {#106806 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106810 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106808 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106822 …}
    -apiLastModifiedAt: DateTime @1754517600 {#106789
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#106828
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @845244000 {#106827
      date: 1996-10-14 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 688
    -documents: Doctrine\ORM\PersistentCollection {#106819 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106817 …}
  }
  +label: "Historical"
  +icon: "historical"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}