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Response
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Profiled on
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Components

4 Twig Components
8 Render Count
18 ms Render Time
112.0 MiB Memory Usage

Components

Name Metadata Render Count Render Time
ProductState 
"App\Twig\Components\ProductState"
components/ProductState.html.twig 		3 2.68ms
ProductMostRecent 
"App\Twig\Components\ProductMostRecent"
components/ProductMostRecent.html.twig 		3 2.87ms
ProductType 
"App\Twig\Components\ProductType"
components/ProductType.html.twig 		1 0.62ms
ProductCard 
"App\Twig\Components\ProductCard"
components/ProductCard.html.twig 		1 12.32ms

Render calls

ProductState App\Twig\Components\ProductState 92.0 MiB 2.23 ms
Input props 
[
  "product" => App\Entity\Product\Product {#7310
    #id: 9458
    #code: "IEEE00002372"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
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      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 32841
        #name: "IEEE/ISO/IEC 10861:1994"
        #slug: "ieee-iso-iec-10861-1994-ieee00002372-241110"
        #description: """
          New IEEE Standard - Inactive-Withdrawn.<br />\n
          The operation, functions, and attributes of a parallel system bus (PSB), called MULTIBUS II, are defined. A high-performance backplane bus intended for use in multiple processor systems, the PSB incorporates synchronous, 32-bit multiplexed address/data, with error detection, and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of cost-effective, high-performance VLSI for the bus interface. Memory, I/O, message, and geographic address spaces are defined. Error detection and retry are provided for messages. The message-passing design allows a VLSI implementation, so that virtually all modules on the bus will utilize the bus at its highest performance—32 to 40 Mbyte/s. An overview of PSB, signal descriptions, the PSB protocol, electrical characteristics, and mechanical specifications are covered.<br />\n
          \t\t\t\t<br />\n
          This International Standard defines the operation, functions, and attributes of the IEEE 1296 bus standard. This standard defines a high-performance 32-bit synchronous bus standard.The bus standard must have a design-in lifetime of 10 years with backward compatibility.The standard is intended for general purpose applications to optimize block transfers, including protocol for message passing. For real-time applications, the bus will provide a means of ensuring an upper limit to message delivery time.The standard is intended to be compatible with existing IEC mechanical standards (IEC Pub 297-1, 297-3, and 603-2) with recognition of the need for special front panels to address ESD, EMI, and RFI requirements.Options within the standard will be clearly identified.The standard is intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system.The standard is intended to support heterogeneous processor types in the same system.Message-passing format and protocol is intended for future migration to a serial system bus.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "ISO/IEC International Standard for Information Technology- Microprocessor Systems- High-Performance Synchronous 32-Bit Bus: Multibus II"
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    -lastUpdatedAt: DateTime @1578006000 {#7292
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    -author: ""
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Attributes 
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Component 
App\Twig\Components\ProductState {#92891
  +product: App\Entity\Product\Product {#7310
    #id: 9458
    #code: "IEEE00002372"
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    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
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      "en_US" => App\Entity\Product\ProductTranslation {#7920
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        #id: 32841
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          New IEEE Standard - Inactive-Withdrawn.<br />\n
          The operation, functions, and attributes of a parallel system bus (PSB), called MULTIBUS II, are defined. A high-performance backplane bus intended for use in multiple processor systems, the PSB incorporates synchronous, 32-bit multiplexed address/data, with error detection, and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of cost-effective, high-performance VLSI for the bus interface. Memory, I/O, message, and geographic address spaces are defined. Error detection and retry are provided for messages. The message-passing design allows a VLSI implementation, so that virtually all modules on the bus will utilize the bus at its highest performance—32 to 40 Mbyte/s. An overview of PSB, signal descriptions, the PSB protocol, electrical characteristics, and mechanical specifications are covered.<br />\n
          \t\t\t\t<br />\n
          This International Standard defines the operation, functions, and attributes of the IEEE 1296 bus standard. This standard defines a high-performance 32-bit synchronous bus standard.The bus standard must have a design-in lifetime of 10 years with backward compatibility.The standard is intended for general purpose applications to optimize block transfers, including protocol for message passing. For real-time applications, the bus will provide a means of ensuring an upper limit to message delivery time.The standard is intended to be compatible with existing IEC mechanical standards (IEC Pub 297-1, 297-3, and 603-2) with recognition of the need for special front panels to address ESD, EMI, and RFI requirements.Options within the standard will be clearly identified.The standard is intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system.The standard is intended to support heterogeneous processor types in the same system.Message-passing format and protocol is intended for future migration to a serial system bus.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "ISO/IEC International Standard for Information Technology- Microprocessor Systems- High-Performance Synchronous 32-Bit Bus: Multibus II"
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  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductType App\Twig\Components\ProductType 92.0 MiB 0.62 ms
Input props 
[
  "product" => App\Entity\Product\Product {#7310
    #id: 9458
    #code: "IEEE00002372"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751038280 {#7274
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    #updatedAt: DateTime @1754607004 {#7322
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    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 32841
        #name: "IEEE/ISO/IEC 10861:1994"
        #slug: "ieee-iso-iec-10861-1994-ieee00002372-241110"
        #description: """
          New IEEE Standard - Inactive-Withdrawn.<br />\n
          The operation, functions, and attributes of a parallel system bus (PSB), called MULTIBUS II, are defined. A high-performance backplane bus intended for use in multiple processor systems, the PSB incorporates synchronous, 32-bit multiplexed address/data, with error detection, and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of cost-effective, high-performance VLSI for the bus interface. Memory, I/O, message, and geographic address spaces are defined. Error detection and retry are provided for messages. The message-passing design allows a VLSI implementation, so that virtually all modules on the bus will utilize the bus at its highest performance—32 to 40 Mbyte/s. An overview of PSB, signal descriptions, the PSB protocol, electrical characteristics, and mechanical specifications are covered.<br />\n
          \t\t\t\t<br />\n
          This International Standard defines the operation, functions, and attributes of the IEEE 1296 bus standard. This standard defines a high-performance 32-bit synchronous bus standard.The bus standard must have a design-in lifetime of 10 years with backward compatibility.The standard is intended for general purpose applications to optimize block transfers, including protocol for message passing. For real-time applications, the bus will provide a means of ensuring an upper limit to message delivery time.The standard is intended to be compatible with existing IEC mechanical standards (IEC Pub 297-1, 297-3, and 603-2) with recognition of the need for special front panels to address ESD, EMI, and RFI requirements.Options within the standard will be clearly identified.The standard is intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system.The standard is intended to support heterogeneous processor types in the same system.Message-passing format and protocol is intended for future migration to a serial system bus.
          """
        #metaKeywords: null
        #metaDescription: null
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Attributes 
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Component 
App\Twig\Components\ProductType {#93062
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      "en_US" => App\Entity\Product\ProductTranslation {#7920
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        #id: 32841
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          New IEEE Standard - Inactive-Withdrawn.<br />\n
          The operation, functions, and attributes of a parallel system bus (PSB), called MULTIBUS II, are defined. A high-performance backplane bus intended for use in multiple processor systems, the PSB incorporates synchronous, 32-bit multiplexed address/data, with error detection, and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of cost-effective, high-performance VLSI for the bus interface. Memory, I/O, message, and geographic address spaces are defined. Error detection and retry are provided for messages. The message-passing design allows a VLSI implementation, so that virtually all modules on the bus will utilize the bus at its highest performance—32 to 40 Mbyte/s. An overview of PSB, signal descriptions, the PSB protocol, electrical characteristics, and mechanical specifications are covered.<br />\n
          \t\t\t\t<br />\n
          This International Standard defines the operation, functions, and attributes of the IEEE 1296 bus standard. This standard defines a high-performance 32-bit synchronous bus standard.The bus standard must have a design-in lifetime of 10 years with backward compatibility.The standard is intended for general purpose applications to optimize block transfers, including protocol for message passing. For real-time applications, the bus will provide a means of ensuring an upper limit to message delivery time.The standard is intended to be compatible with existing IEC mechanical standards (IEC Pub 297-1, 297-3, and 603-2) with recognition of the need for special front panels to address ESD, EMI, and RFI requirements.Options within the standard will be clearly identified.The standard is intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system.The standard is intended to support heterogeneous processor types in the same system.Message-passing format and protocol is intended for future migration to a serial system bus.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "ISO/IEC International Standard for Information Technology- Microprocessor Systems- High-Performance Synchronous 32-Bit Bus: Multibus II"
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  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductMostRecent App\Twig\Components\ProductMostRecent 92.0 MiB 1.35 ms
Input props 
[
  "product" => App\Entity\Product\Product {#7310
    #id: 9458
    #code: "IEEE00002372"
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    #createdAt: DateTime @1751038280 {#7274
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    #enabled: true
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      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
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          New IEEE Standard - Inactive-Withdrawn.<br />\n
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          \t\t\t\t<br />\n
          This International Standard defines the operation, functions, and attributes of the IEEE 1296 bus standard. This standard defines a high-performance 32-bit synchronous bus standard.The bus standard must have a design-in lifetime of 10 years with backward compatibility.The standard is intended for general purpose applications to optimize block transfers, including protocol for message passing. For real-time applications, the bus will provide a means of ensuring an upper limit to message delivery time.The standard is intended to be compatible with existing IEC mechanical standards (IEC Pub 297-1, 297-3, and 603-2) with recognition of the need for special front panels to address ESD, EMI, and RFI requirements.Options within the standard will be clearly identified.The standard is intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system.The standard is intended to support heterogeneous processor types in the same system.Message-passing format and protocol is intended for future migration to a serial system bus.
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Attributes 
[]
Component 
App\Twig\Components\ProductMostRecent {#93137
  +product: App\Entity\Product\Product {#7310
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      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 32841
        #name: "IEEE/ISO/IEC 10861:1994"
        #slug: "ieee-iso-iec-10861-1994-ieee00002372-241110"
        #description: """
          New IEEE Standard - Inactive-Withdrawn.<br />\n
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          \t\t\t\t<br />\n
          This International Standard defines the operation, functions, and attributes of the IEEE 1296 bus standard. This standard defines a high-performance 32-bit synchronous bus standard.The bus standard must have a design-in lifetime of 10 years with backward compatibility.The standard is intended for general purpose applications to optimize block transfers, including protocol for message passing. For real-time applications, the bus will provide a means of ensuring an upper limit to message delivery time.The standard is intended to be compatible with existing IEC mechanical standards (IEC Pub 297-1, 297-3, and 603-2) with recognition of the need for special front panels to address ESD, EMI, and RFI requirements.Options within the standard will be clearly identified.The standard is intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system.The standard is intended to support heterogeneous processor types in the same system.Message-passing format and protocol is intended for future migration to a serial system bus.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "ISO/IEC International Standard for Information Technology- Microprocessor Systems- High-Performance Synchronous 32-Bit Bus: Multibus II"
        -notes: "Inactive-Withdrawn"
      }
    ]
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  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
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ProductState App\Twig\Components\ProductState 92.0 MiB 0.21 ms
Input props 
[
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    #id: 9458
    #code: "IEEE00002372"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
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    #enabled: true
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      "en_US" => App\Entity\Product\ProductTranslation {#7920
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        #translatable: App\Entity\Product\Product {#7310}
        #id: 32841
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          New IEEE Standard - Inactive-Withdrawn.<br />\n
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          \t\t\t\t<br />\n
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Attributes 
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Component 
App\Twig\Components\ProductState {#100090
  +product: App\Entity\Product\Product {#7310
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    #code: "IEEE00002372"
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      "en_US" => App\Entity\Product\ProductTranslation {#7920
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          New IEEE Standard - Inactive-Withdrawn.<br />\n
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          \t\t\t\t<br />\n
          This International Standard defines the operation, functions, and attributes of the IEEE 1296 bus standard. This standard defines a high-performance 32-bit synchronous bus standard.The bus standard must have a design-in lifetime of 10 years with backward compatibility.The standard is intended for general purpose applications to optimize block transfers, including protocol for message passing. For real-time applications, the bus will provide a means of ensuring an upper limit to message delivery time.The standard is intended to be compatible with existing IEC mechanical standards (IEC Pub 297-1, 297-3, and 603-2) with recognition of the need for special front panels to address ESD, EMI, and RFI requirements.Options within the standard will be clearly identified.The standard is intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system.The standard is intended to support heterogeneous processor types in the same system.Message-passing format and protocol is intended for future migration to a serial system bus.
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        #metaKeywords: null
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  }
  +appearance: "state-withdrawn"
  +labels: [
    "Withdrawn"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductMostRecent App\Twig\Components\ProductMostRecent 92.0 MiB 0.76 ms
Input props 
[
  "product" => App\Entity\Product\Product {#7310
    #id: 9458
    #code: "IEEE00002372"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751038280 {#7274
      date: 2025-06-27 17:31:20.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#7322
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    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
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        #translatable: App\Entity\Product\Product {#7310}
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        #description: """
          New IEEE Standard - Inactive-Withdrawn.<br />\n
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          \t\t\t\t<br />\n
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        #metaKeywords: null
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Attributes 
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Component 
App\Twig\Components\ProductMostRecent {#100174
  +product: App\Entity\Product\Product {#7310
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    #createdAt: DateTime @1751038280 {#7274
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    }
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    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
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          New IEEE Standard - Inactive-Withdrawn.<br />\n
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          \t\t\t\t<br />\n
          This International Standard defines the operation, functions, and attributes of the IEEE 1296 bus standard. This standard defines a high-performance 32-bit synchronous bus standard.The bus standard must have a design-in lifetime of 10 years with backward compatibility.The standard is intended for general purpose applications to optimize block transfers, including protocol for message passing. For real-time applications, the bus will provide a means of ensuring an upper limit to message delivery time.The standard is intended to be compatible with existing IEC mechanical standards (IEC Pub 297-1, 297-3, and 603-2) with recognition of the need for special front panels to address ESD, EMI, and RFI requirements.Options within the standard will be clearly identified.The standard is intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system.The standard is intended to support heterogeneous processor types in the same system.Message-passing format and protocol is intended for future migration to a serial system bus.
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        #metaKeywords: null
        #metaDescription: null
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    #currentTranslation: null
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  +label: "Most Recent"
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  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductCard App\Twig\Components\ProductCard 112.0 MiB 12.32 ms
Input props 
[
  "product" => App\Entity\Product\Product {#121553
    #id: 9109
    #code: "IEEE00001643"
    #attributes: Doctrine\ORM\PersistentCollection {#121536 …}
    #variants: Doctrine\ORM\PersistentCollection {#121534 …}
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    #associations: Doctrine\ORM\PersistentCollection {#121531 …}
    #createdAt: DateTime @1751037978 {#121526
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    #updatedAt: DateTime @1754607611 {#121519
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
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    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#121547 …}
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        #translatable: App\Entity\Product\Product {#121553}
        #id: 31445
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        #description: """
          New IEEE Standard - Inactive-Withdrawn.<br />\n
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          \t\t\t\t<br />\n
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  "layout" => "vertical"
  "showPrice" => true
  "showStatusBadges" => true
  "additionalClasses" => "product__teaser--with-grey-border"
  "hasStretchedLink" => true
  "hoverType" => "shadow"
  "linkLabel" => "See more"
]
Attributes 
[]
Component 
App\Twig\Components\ProductCard {#121609
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    #enabled: true
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          \t\t\t\t<br />\n
          The purpose of this standard is the specification of dimensions that will ensure the mechanical interchangeability and environmental requirements of subracks and of plug-in units.
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ProductState App\Twig\Components\ProductState 112.0 MiB 0.24 ms
Input props 
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Attributes 
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Component 
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ProductMostRecent App\Twig\Components\ProductMostRecent 112.0 MiB 0.76 ms
Input props 
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Attributes 
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}