Components
4
Twig Components
10
Render Count
10
ms
Render Time
102.0
MiB
Memory Usage
Components
| Name | Metadata | Render Count | Render Time |
|---|---|---|---|
| ProductState |
"App\Twig\Components\ProductState"components/ProductState.html.twig |
4 | 0.94ms |
| ProductMostRecent |
"App\Twig\Components\ProductMostRecent"components/ProductMostRecent.html.twig |
4 | 2.94ms |
| ProductType |
"App\Twig\Components\ProductType"components/ProductType.html.twig |
1 | 0.21ms |
| ProductCard |
"App\Twig\Components\ProductCard"components/ProductCard.html.twig |
1 | 6.42ms |
Render calls
| ProductState | App\Twig\Components\ProductState | 68.0 MiB | 0.34 ms | |
|---|---|---|---|---|
| Input props | [ "product" => App\Entity\Product\Product {#7311 #id: 10347 #code: "IEEE00004212" #attributes: Doctrine\ORM\PersistentCollection {#7701 …} #variants: Doctrine\ORM\PersistentCollection {#7744 …} #options: Doctrine\ORM\PersistentCollection {#7916 …} #associations: Doctrine\ORM\PersistentCollection {#7900 …} #createdAt: DateTime @1751039005 {#7274 : 2025-06-27 17:43:25.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#7322 : 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7922 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7921 #locale: "en_US" #translatable: App\Entity\Product\Product {#7311} #id: 36397 #name: "IEEE 1581:2011" #slug: "ieee-1581-2011-ieee00004212-241999" #description: """ New IEEE Standard - Inactive-Reserved.<br />\n IEEE Std 1581 defines a low-cost method for testing the interconnection of discrete, complex memory integrated circuits (ICs) where additional pins for testing are not available and implementing boundary scan (IEEE Std 1149.1(TM)) is not feasible. This standard describes the implementation rules for the test logic and test mode access/exit methods in compliant ICs. The standard is limited to the behavioral description of the implementation and will not include the technical design for the test logic or test mode control circuitry.<br />\n \t\t\t\t<br />\n This standard defines a low-cost method for testing the interconnection of discrete, complex memory integrated circuits (ICs) where additional pins for testing are not available and implementing boundary scan (IEEE Std 1149.1)1 is not feasible. This standard describes the implementation rules for the test logic and test mode access/exit methods in compliant ICs. The standard is limited to the behavioral description of the implementation and will not include the technical design for the test logic or test mode control circuitry.<br />\n There is currently no defined, independent standard for test technology in memory devices. Each vendor is free in the way of implementing test hardware functionality in their ICs to support connectivity tests. Without an independent standard, testability is reduced, and test coverage may not be complete -- making the test technology less useful for others.<br />\n This standard will improve interconnect testing for discrete memory devices by specifying implementation rules for test logic and test mode entry/exit methods included in memory ICs as guidance both to IC vendors implementing the standard and to test equipment manufacturers supporting this standard. The standard is aimed at ICs that are otherwise not provisioned with design for testability (DFT) for any reason, targeting primarily memory devices but also allowing for implementation in other devices, while supporting the highest fault coverage and pin-level diagnostics of board-level connectivity faults on such devices. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Static Component Interconnection Test Protocol and Architecture" -notes: "Inactive-Reserved" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …} #channels: Doctrine\ORM\PersistentCollection {#7628 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#7613 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7645 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1648764000 {#7292 : 2022-04-01 00:00:00.0 Europe/Paris (+02:00) } -author: "" -publishedAt: DateTime @1308520800 {#7318 : 2011-06-20 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1648076400 {#7316 : 2022-03-24 00:00:00.0 Europe/Paris (+01:00) } -edition: null -coreDocument: "1581" -bookCollection: "" -pageCount: 61 -documents: Doctrine\ORM\PersistentCollection {#7465 …} -favorites: Doctrine\ORM\PersistentCollection {#7500 …} } "showFullLabel" => "true" ] |
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| Component | App\Twig\Components\ProductState {#93067 +product: App\Entity\Product\Product {#7311 #id: 10347 #code: "IEEE00004212" #attributes: Doctrine\ORM\PersistentCollection {#7701 …} #variants: Doctrine\ORM\PersistentCollection {#7744 …} #options: Doctrine\ORM\PersistentCollection {#7916 …} #associations: Doctrine\ORM\PersistentCollection {#7900 …} #createdAt: DateTime @1751039005 {#7274 : 2025-06-27 17:43:25.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#7322 : 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7922 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7921 #locale: "en_US" #translatable: App\Entity\Product\Product {#7311} #id: 36397 #name: "IEEE 1581:2011" #slug: "ieee-1581-2011-ieee00004212-241999" #description: """ New IEEE Standard - Inactive-Reserved.<br />\n IEEE Std 1581 defines a low-cost method for testing the interconnection of discrete, complex memory integrated circuits (ICs) where additional pins for testing are not available and implementing boundary scan (IEEE Std 1149.1(TM)) is not feasible. This standard describes the implementation rules for the test logic and test mode access/exit methods in compliant ICs. The standard is limited to the behavioral description of the implementation and will not include the technical design for the test logic or test mode control circuitry.<br />\n \t\t\t\t<br />\n This standard defines a low-cost method for testing the interconnection of discrete, complex memory integrated circuits (ICs) where additional pins for testing are not available and implementing boundary scan (IEEE Std 1149.1)1 is not feasible. This standard describes the implementation rules for the test logic and test mode access/exit methods in compliant ICs. The standard is limited to the behavioral description of the implementation and will not include the technical design for the test logic or test mode control circuitry.<br />\n There is currently no defined, independent standard for test technology in memory devices. Each vendor is free in the way of implementing test hardware functionality in their ICs to support connectivity tests. Without an independent standard, testability is reduced, and test coverage may not be complete -- making the test technology less useful for others.<br />\n This standard will improve interconnect testing for discrete memory devices by specifying implementation rules for test logic and test mode entry/exit methods included in memory ICs as guidance both to IC vendors implementing the standard and to test equipment manufacturers supporting this standard. The standard is aimed at ICs that are otherwise not provisioned with design for testability (DFT) for any reason, targeting primarily memory devices but also allowing for implementation in other devices, while supporting the highest fault coverage and pin-level diagnostics of board-level connectivity faults on such devices. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Static Component Interconnection Test Protocol and Architecture" -notes: "Inactive-Reserved" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …} #channels: Doctrine\ORM\PersistentCollection {#7628 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#7613 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7645 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1648764000 {#7292 : 2022-04-01 00:00:00.0 Europe/Paris (+02:00) } -author: "" -publishedAt: DateTime @1308520800 {#7318 : 2011-06-20 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1648076400 {#7316 : 2022-03-24 00:00:00.0 Europe/Paris (+01:00) } -edition: null -coreDocument: "1581" -bookCollection: "" -pageCount: 61 -documents: Doctrine\ORM\PersistentCollection {#7465 …} -favorites: Doctrine\ORM\PersistentCollection {#7500 …} } +appearance: "state-withdrawn" +labels: [ "Withdrawn" ] -stateAttributeCode: "state" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …} } |
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| ProductType | App\Twig\Components\ProductType | 68.0 MiB | 0.21 ms | |
|---|---|---|---|---|
| Input props | [ "product" => App\Entity\Product\Product {#7311 #id: 10347 #code: "IEEE00004212" #attributes: Doctrine\ORM\PersistentCollection {#7701 …} #variants: Doctrine\ORM\PersistentCollection {#7744 …} #options: Doctrine\ORM\PersistentCollection {#7916 …} #associations: Doctrine\ORM\PersistentCollection {#7900 …} #createdAt: DateTime @1751039005 {#7274 : 2025-06-27 17:43:25.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#7322 : 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7922 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7921 #locale: "en_US" #translatable: App\Entity\Product\Product {#7311} #id: 36397 #name: "IEEE 1581:2011" #slug: "ieee-1581-2011-ieee00004212-241999" #description: """ New IEEE Standard - Inactive-Reserved.<br />\n IEEE Std 1581 defines a low-cost method for testing the interconnection of discrete, complex memory integrated circuits (ICs) where additional pins for testing are not available and implementing boundary scan (IEEE Std 1149.1(TM)) is not feasible. This standard describes the implementation rules for the test logic and test mode access/exit methods in compliant ICs. The standard is limited to the behavioral description of the implementation and will not include the technical design for the test logic or test mode control circuitry.<br />\n \t\t\t\t<br />\n This standard defines a low-cost method for testing the interconnection of discrete, complex memory integrated circuits (ICs) where additional pins for testing are not available and implementing boundary scan (IEEE Std 1149.1)1 is not feasible. This standard describes the implementation rules for the test logic and test mode access/exit methods in compliant ICs. The standard is limited to the behavioral description of the implementation and will not include the technical design for the test logic or test mode control circuitry.<br />\n There is currently no defined, independent standard for test technology in memory devices. Each vendor is free in the way of implementing test hardware functionality in their ICs to support connectivity tests. Without an independent standard, testability is reduced, and test coverage may not be complete -- making the test technology less useful for others.<br />\n This standard will improve interconnect testing for discrete memory devices by specifying implementation rules for test logic and test mode entry/exit methods included in memory ICs as guidance both to IC vendors implementing the standard and to test equipment manufacturers supporting this standard. The standard is aimed at ICs that are otherwise not provisioned with design for testability (DFT) for any reason, targeting primarily memory devices but also allowing for implementation in other devices, while supporting the highest fault coverage and pin-level diagnostics of board-level connectivity faults on such devices. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Static Component Interconnection Test Protocol and Architecture" -notes: "Inactive-Reserved" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …} #channels: Doctrine\ORM\PersistentCollection {#7628 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#7613 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7645 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1648764000 {#7292 : 2022-04-01 00:00:00.0 Europe/Paris (+02:00) } -author: "" -publishedAt: DateTime @1308520800 {#7318 : 2011-06-20 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1648076400 {#7316 : 2022-03-24 00:00:00.0 Europe/Paris (+01:00) } -edition: null -coreDocument: "1581" -bookCollection: "" -pageCount: 61 -documents: Doctrine\ORM\PersistentCollection {#7465 …} -favorites: Doctrine\ORM\PersistentCollection {#7500 …} } ] |
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| Component | App\Twig\Components\ProductType {#93247 +product: App\Entity\Product\Product {#7311 #id: 10347 #code: "IEEE00004212" #attributes: Doctrine\ORM\PersistentCollection {#7701 …} #variants: Doctrine\ORM\PersistentCollection {#7744 …} #options: Doctrine\ORM\PersistentCollection {#7916 …} #associations: Doctrine\ORM\PersistentCollection {#7900 …} #createdAt: DateTime @1751039005 {#7274 : 2025-06-27 17:43:25.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#7322 : 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7922 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7921 #locale: "en_US" #translatable: App\Entity\Product\Product {#7311} #id: 36397 #name: "IEEE 1581:2011" #slug: "ieee-1581-2011-ieee00004212-241999" #description: """ New IEEE Standard - Inactive-Reserved.<br />\n IEEE Std 1581 defines a low-cost method for testing the interconnection of discrete, complex memory integrated circuits (ICs) where additional pins for testing are not available and implementing boundary scan (IEEE Std 1149.1(TM)) is not feasible. This standard describes the implementation rules for the test logic and test mode access/exit methods in compliant ICs. The standard is limited to the behavioral description of the implementation and will not include the technical design for the test logic or test mode control circuitry.<br />\n \t\t\t\t<br />\n This standard defines a low-cost method for testing the interconnection of discrete, complex memory integrated circuits (ICs) where additional pins for testing are not available and implementing boundary scan (IEEE Std 1149.1)1 is not feasible. This standard describes the implementation rules for the test logic and test mode access/exit methods in compliant ICs. The standard is limited to the behavioral description of the implementation and will not include the technical design for the test logic or test mode control circuitry.<br />\n There is currently no defined, independent standard for test technology in memory devices. Each vendor is free in the way of implementing test hardware functionality in their ICs to support connectivity tests. Without an independent standard, testability is reduced, and test coverage may not be complete -- making the test technology less useful for others.<br />\n This standard will improve interconnect testing for discrete memory devices by specifying implementation rules for test logic and test mode entry/exit methods included in memory ICs as guidance both to IC vendors implementing the standard and to test equipment manufacturers supporting this standard. The standard is aimed at ICs that are otherwise not provisioned with design for testability (DFT) for any reason, targeting primarily memory devices but also allowing for implementation in other devices, while supporting the highest fault coverage and pin-level diagnostics of board-level connectivity faults on such devices. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Static Component Interconnection Test Protocol and Architecture" -notes: "Inactive-Reserved" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …} #channels: Doctrine\ORM\PersistentCollection {#7628 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#7613 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7645 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1648764000 {#7292 : 2022-04-01 00:00:00.0 Europe/Paris (+02:00) } -author: "" -publishedAt: DateTime @1308520800 {#7318 : 2011-06-20 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1648076400 {#7316 : 2022-03-24 00:00:00.0 Europe/Paris (+01:00) } -edition: null -coreDocument: "1581" -bookCollection: "" -pageCount: 61 -documents: Doctrine\ORM\PersistentCollection {#7465 …} -favorites: Doctrine\ORM\PersistentCollection {#7500 …} } +label: "Standard" -typeAttributeCode: "type" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …} } |
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| ProductMostRecent | App\Twig\Components\ProductMostRecent | 68.0 MiB | 0.68 ms | |
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| Input props | [ "product" => App\Entity\Product\Product {#7311 #id: 10347 #code: "IEEE00004212" #attributes: Doctrine\ORM\PersistentCollection {#7701 …} #variants: Doctrine\ORM\PersistentCollection {#7744 …} #options: Doctrine\ORM\PersistentCollection {#7916 …} #associations: Doctrine\ORM\PersistentCollection {#7900 …} #createdAt: DateTime @1751039005 {#7274 : 2025-06-27 17:43:25.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#7322 : 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7922 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7921 #locale: "en_US" #translatable: App\Entity\Product\Product {#7311} #id: 36397 #name: "IEEE 1581:2011" #slug: "ieee-1581-2011-ieee00004212-241999" #description: """ New IEEE Standard - Inactive-Reserved.<br />\n IEEE Std 1581 defines a low-cost method for testing the interconnection of discrete, complex memory integrated circuits (ICs) where additional pins for testing are not available and implementing boundary scan (IEEE Std 1149.1(TM)) is not feasible. This standard describes the implementation rules for the test logic and test mode access/exit methods in compliant ICs. The standard is limited to the behavioral description of the implementation and will not include the technical design for the test logic or test mode control circuitry.<br />\n \t\t\t\t<br />\n This standard defines a low-cost method for testing the interconnection of discrete, complex memory integrated circuits (ICs) where additional pins for testing are not available and implementing boundary scan (IEEE Std 1149.1)1 is not feasible. This standard describes the implementation rules for the test logic and test mode access/exit methods in compliant ICs. The standard is limited to the behavioral description of the implementation and will not include the technical design for the test logic or test mode control circuitry.<br />\n There is currently no defined, independent standard for test technology in memory devices. Each vendor is free in the way of implementing test hardware functionality in their ICs to support connectivity tests. Without an independent standard, testability is reduced, and test coverage may not be complete -- making the test technology less useful for others.<br />\n This standard will improve interconnect testing for discrete memory devices by specifying implementation rules for test logic and test mode entry/exit methods included in memory ICs as guidance both to IC vendors implementing the standard and to test equipment manufacturers supporting this standard. The standard is aimed at ICs that are otherwise not provisioned with design for testability (DFT) for any reason, targeting primarily memory devices but also allowing for implementation in other devices, while supporting the highest fault coverage and pin-level diagnostics of board-level connectivity faults on such devices. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Static Component Interconnection Test Protocol and Architecture" -notes: "Inactive-Reserved" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …} #channels: Doctrine\ORM\PersistentCollection {#7628 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#7613 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7645 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1648764000 {#7292 : 2022-04-01 00:00:00.0 Europe/Paris (+02:00) } -author: "" -publishedAt: DateTime @1308520800 {#7318 : 2011-06-20 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1648076400 {#7316 : 2022-03-24 00:00:00.0 Europe/Paris (+01:00) } -edition: null -coreDocument: "1581" -bookCollection: "" -pageCount: 61 -documents: Doctrine\ORM\PersistentCollection {#7465 …} -favorites: Doctrine\ORM\PersistentCollection {#7500 …} } ] |
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| Component | App\Twig\Components\ProductMostRecent {#93322 +product: App\Entity\Product\Product {#7311 #id: 10347 #code: "IEEE00004212" #attributes: Doctrine\ORM\PersistentCollection {#7701 …} #variants: Doctrine\ORM\PersistentCollection {#7744 …} #options: Doctrine\ORM\PersistentCollection {#7916 …} #associations: Doctrine\ORM\PersistentCollection {#7900 …} #createdAt: DateTime @1751039005 {#7274 : 2025-06-27 17:43:25.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#7322 : 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7922 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7921 #locale: "en_US" #translatable: App\Entity\Product\Product {#7311} #id: 36397 #name: "IEEE 1581:2011" #slug: "ieee-1581-2011-ieee00004212-241999" #description: """ New IEEE Standard - Inactive-Reserved.<br />\n IEEE Std 1581 defines a low-cost method for testing the interconnection of discrete, complex memory integrated circuits (ICs) where additional pins for testing are not available and implementing boundary scan (IEEE Std 1149.1(TM)) is not feasible. This standard describes the implementation rules for the test logic and test mode access/exit methods in compliant ICs. The standard is limited to the behavioral description of the implementation and will not include the technical design for the test logic or test mode control circuitry.<br />\n \t\t\t\t<br />\n This standard defines a low-cost method for testing the interconnection of discrete, complex memory integrated circuits (ICs) where additional pins for testing are not available and implementing boundary scan (IEEE Std 1149.1)1 is not feasible. This standard describes the implementation rules for the test logic and test mode access/exit methods in compliant ICs. The standard is limited to the behavioral description of the implementation and will not include the technical design for the test logic or test mode control circuitry.<br />\n There is currently no defined, independent standard for test technology in memory devices. Each vendor is free in the way of implementing test hardware functionality in their ICs to support connectivity tests. Without an independent standard, testability is reduced, and test coverage may not be complete -- making the test technology less useful for others.<br />\n This standard will improve interconnect testing for discrete memory devices by specifying implementation rules for test logic and test mode entry/exit methods included in memory ICs as guidance both to IC vendors implementing the standard and to test equipment manufacturers supporting this standard. The standard is aimed at ICs that are otherwise not provisioned with design for testability (DFT) for any reason, targeting primarily memory devices but also allowing for implementation in other devices, while supporting the highest fault coverage and pin-level diagnostics of board-level connectivity faults on such devices. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Static Component Interconnection Test Protocol and Architecture" -notes: "Inactive-Reserved" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …} #channels: Doctrine\ORM\PersistentCollection {#7628 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#7613 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7645 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1648764000 {#7292 : 2022-04-01 00:00:00.0 Europe/Paris (+02:00) } -author: "" -publishedAt: DateTime @1308520800 {#7318 : 2011-06-20 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1648076400 {#7316 : 2022-03-24 00:00:00.0 Europe/Paris (+01:00) } -edition: null -coreDocument: "1581" -bookCollection: "" -pageCount: 61 -documents: Doctrine\ORM\PersistentCollection {#7465 …} -favorites: Doctrine\ORM\PersistentCollection {#7500 …} } +label: "Most Recent" +icon: "check-xs" -mostRecentAttributeCode: "most_recent" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …} } |
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| Input props | [ "product" => App\Entity\Product\Product {#93749 #id: 13346 #code: "IEEE00010428" #attributes: Doctrine\ORM\PersistentCollection {#93731 …} #variants: Doctrine\ORM\PersistentCollection {#93728 …} #options: Doctrine\ORM\PersistentCollection {#93724 …} #associations: Doctrine\ORM\PersistentCollection {#93726 …} #createdAt: DateTime @1751041080 {#93757 : 2025-06-27 18:18:00.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608621 {#93736 : 2025-08-08 01:17:01.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#93742 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#93777 #locale: "en_US" #translatable: App\Entity\Product\Product {#93749} #id: 48393 #name: "IEEE/IEC P1581" #slug: "ieee-iec-p1581-ieee00010428-580430" #description: """ Revision Standard - Active - Draft.<br />\n IEEE Std 1581 defines a low-cost method for testing the interconnection of discrete, complex memory integrated circuits (ICs) where additional pins for testing are not available and implementing boundary scan (IEEE Std 1149.1™) is not feasible. This standard describes the implementation rules for the test logic and test mode access/exit methods in conformant ICs. The standard is limited to the behavioral description of the implementation and will not include the technical design for the test logic or test mode control circuitry.<br />\n \t\t\t\t<br />\n This standard defines a low-cost method for testing the interconnection of discrete, complex memory integrated circuits (ICs) where additional pins for testing are not available and implementing boundary scan (IEEE Std 1149.1, IEEE Standard for Test Access Port and Boundary-Scan Architecture, https://standards.ieee.org/standard/1149_1-2013.html) is not feasible. This standard describes the implementation rules for the test logic and test mode access/exit methods in compliant ICs. The standard is limited to the behavioral description of the implementation and will not include the technical design for the test logic or test mode control circuitry.<br />\n There is currently no defined, independent standard for test technology in memory devices. Each vendor is free in the way of implementing test hardware functionality in their ICs to support connectivity tests. Without an independent standard, testability is reduced, and test coverage may not be complete -- making<br />\n the test technology less useful for others.<br />\n This standard will improve interconnect testing for discrete memory devices by specifying implementation rules for test logic and test mode entry/exit methods included in memory ICs as guidance both to IC vendors implementing the standard and to test equipment manufacturers supporting this standard. The standard is aimed at ICs that are otherwise not provisioned with design for testability (DFT) for any reason, targeting primarily memory devices but also allowing for implementation in other devices, while supporting the highest fault coverage and pin-level diagnostics of board-level connectivity faults on such devices. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Draft Standard for Static Component Interconnection Test Protocol and Architecture" -notes: "Active" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#93740 …} #channels: Doctrine\ORM\PersistentCollection {#93733 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#93738 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#93735 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#93750 …} -apiLastModifiedAt: DateTime @1754517600 {#93720 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1747692000 {#93756 : 2025-05-20 00:00:00.0 Europe/Paris (+02:00) } -author: "" -publishedAt: DateTime @1747692000 {#93755 : 2025-05-20 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1581" -bookCollection: "" -pageCount: 107 -documents: Doctrine\ORM\PersistentCollection {#93746 …} -favorites: Doctrine\ORM\PersistentCollection {#93744 …} } "showFullLabel" => "true" ] |
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| Input props | [ "product" => App\Entity\Product\Product {#7311 #id: 10347 #code: "IEEE00004212" #attributes: Doctrine\ORM\PersistentCollection {#7701 …} #variants: Doctrine\ORM\PersistentCollection {#7744 …} #options: Doctrine\ORM\PersistentCollection {#7916 …} #associations: Doctrine\ORM\PersistentCollection {#7900 …} #createdAt: DateTime @1751039005 {#7274 : 2025-06-27 17:43:25.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#7322 : 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7922 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7921 #locale: "en_US" #translatable: App\Entity\Product\Product {#7311} #id: 36397 #name: "IEEE 1581:2011" #slug: "ieee-1581-2011-ieee00004212-241999" #description: """ New IEEE Standard - Inactive-Reserved.<br />\n IEEE Std 1581 defines a low-cost method for testing the interconnection of discrete, complex memory integrated circuits (ICs) where additional pins for testing are not available and implementing boundary scan (IEEE Std 1149.1(TM)) is not feasible. This standard describes the implementation rules for the test logic and test mode access/exit methods in compliant ICs. The standard is limited to the behavioral description of the implementation and will not include the technical design for the test logic or test mode control circuitry.<br />\n \t\t\t\t<br />\n This standard defines a low-cost method for testing the interconnection of discrete, complex memory integrated circuits (ICs) where additional pins for testing are not available and implementing boundary scan (IEEE Std 1149.1)1 is not feasible. This standard describes the implementation rules for the test logic and test mode access/exit methods in compliant ICs. The standard is limited to the behavioral description of the implementation and will not include the technical design for the test logic or test mode control circuitry.<br />\n There is currently no defined, independent standard for test technology in memory devices. Each vendor is free in the way of implementing test hardware functionality in their ICs to support connectivity tests. Without an independent standard, testability is reduced, and test coverage may not be complete -- making the test technology less useful for others.<br />\n This standard will improve interconnect testing for discrete memory devices by specifying implementation rules for test logic and test mode entry/exit methods included in memory ICs as guidance both to IC vendors implementing the standard and to test equipment manufacturers supporting this standard. The standard is aimed at ICs that are otherwise not provisioned with design for testability (DFT) for any reason, targeting primarily memory devices but also allowing for implementation in other devices, while supporting the highest fault coverage and pin-level diagnostics of board-level connectivity faults on such devices. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Static Component Interconnection Test Protocol and Architecture" -notes: "Inactive-Reserved" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …} #channels: Doctrine\ORM\PersistentCollection {#7628 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#7613 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7645 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1648764000 {#7292 : 2022-04-01 00:00:00.0 Europe/Paris (+02:00) } -author: "" -publishedAt: DateTime @1308520800 {#7318 : 2011-06-20 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1648076400 {#7316 : 2022-03-24 00:00:00.0 Europe/Paris (+01:00) } -edition: null -coreDocument: "1581" -bookCollection: "" -pageCount: 61 -documents: Doctrine\ORM\PersistentCollection {#7465 …} -favorites: Doctrine\ORM\PersistentCollection {#7500 …} } "showFullLabel" => "true" ] |
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| ProductMostRecent | App\Twig\Components\ProductMostRecent | 80.0 MiB | 0.73 ms | |
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| Input props | [ "product" => App\Entity\Product\Product {#7311 #id: 10347 #code: "IEEE00004212" #attributes: Doctrine\ORM\PersistentCollection {#7701 …} #variants: Doctrine\ORM\PersistentCollection {#7744 …} #options: Doctrine\ORM\PersistentCollection {#7916 …} #associations: Doctrine\ORM\PersistentCollection {#7900 …} #createdAt: DateTime @1751039005 {#7274 : 2025-06-27 17:43:25.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#7322 : 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7922 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7921 #locale: "en_US" #translatable: App\Entity\Product\Product {#7311} #id: 36397 #name: "IEEE 1581:2011" #slug: "ieee-1581-2011-ieee00004212-241999" #description: """ New IEEE Standard - Inactive-Reserved.<br />\n IEEE Std 1581 defines a low-cost method for testing the interconnection of discrete, complex memory integrated circuits (ICs) where additional pins for testing are not available and implementing boundary scan (IEEE Std 1149.1(TM)) is not feasible. This standard describes the implementation rules for the test logic and test mode access/exit methods in compliant ICs. The standard is limited to the behavioral description of the implementation and will not include the technical design for the test logic or test mode control circuitry.<br />\n \t\t\t\t<br />\n This standard defines a low-cost method for testing the interconnection of discrete, complex memory integrated circuits (ICs) where additional pins for testing are not available and implementing boundary scan (IEEE Std 1149.1)1 is not feasible. This standard describes the implementation rules for the test logic and test mode access/exit methods in compliant ICs. The standard is limited to the behavioral description of the implementation and will not include the technical design for the test logic or test mode control circuitry.<br />\n There is currently no defined, independent standard for test technology in memory devices. Each vendor is free in the way of implementing test hardware functionality in their ICs to support connectivity tests. Without an independent standard, testability is reduced, and test coverage may not be complete -- making the test technology less useful for others.<br />\n This standard will improve interconnect testing for discrete memory devices by specifying implementation rules for test logic and test mode entry/exit methods included in memory ICs as guidance both to IC vendors implementing the standard and to test equipment manufacturers supporting this standard. The standard is aimed at ICs that are otherwise not provisioned with design for testability (DFT) for any reason, targeting primarily memory devices but also allowing for implementation in other devices, while supporting the highest fault coverage and pin-level diagnostics of board-level connectivity faults on such devices. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Static Component Interconnection Test Protocol and Architecture" -notes: "Inactive-Reserved" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …} #channels: Doctrine\ORM\PersistentCollection {#7628 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#7613 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7645 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1648764000 {#7292 : 2022-04-01 00:00:00.0 Europe/Paris (+02:00) } -author: "" -publishedAt: DateTime @1308520800 {#7318 : 2011-06-20 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1648076400 {#7316 : 2022-03-24 00:00:00.0 Europe/Paris (+01:00) } -edition: null -coreDocument: "1581" -bookCollection: "" -pageCount: 61 -documents: Doctrine\ORM\PersistentCollection {#7465 …} -favorites: Doctrine\ORM\PersistentCollection {#7500 …} } ] |
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| Attributes | [] |
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| Component | App\Twig\Components\ProductMostRecent {#107065 +product: App\Entity\Product\Product {#7311 #id: 10347 #code: "IEEE00004212" #attributes: Doctrine\ORM\PersistentCollection {#7701 …} #variants: Doctrine\ORM\PersistentCollection {#7744 …} #options: Doctrine\ORM\PersistentCollection {#7916 …} #associations: Doctrine\ORM\PersistentCollection {#7900 …} #createdAt: DateTime @1751039005 {#7274 : 2025-06-27 17:43:25.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#7322 : 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7922 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7921 #locale: "en_US" #translatable: App\Entity\Product\Product {#7311} #id: 36397 #name: "IEEE 1581:2011" #slug: "ieee-1581-2011-ieee00004212-241999" #description: """ New IEEE Standard - Inactive-Reserved.<br />\n IEEE Std 1581 defines a low-cost method for testing the interconnection of discrete, complex memory integrated circuits (ICs) where additional pins for testing are not available and implementing boundary scan (IEEE Std 1149.1(TM)) is not feasible. This standard describes the implementation rules for the test logic and test mode access/exit methods in compliant ICs. The standard is limited to the behavioral description of the implementation and will not include the technical design for the test logic or test mode control circuitry.<br />\n \t\t\t\t<br />\n This standard defines a low-cost method for testing the interconnection of discrete, complex memory integrated circuits (ICs) where additional pins for testing are not available and implementing boundary scan (IEEE Std 1149.1)1 is not feasible. This standard describes the implementation rules for the test logic and test mode access/exit methods in compliant ICs. The standard is limited to the behavioral description of the implementation and will not include the technical design for the test logic or test mode control circuitry.<br />\n There is currently no defined, independent standard for test technology in memory devices. Each vendor is free in the way of implementing test hardware functionality in their ICs to support connectivity tests. Without an independent standard, testability is reduced, and test coverage may not be complete -- making the test technology less useful for others.<br />\n This standard will improve interconnect testing for discrete memory devices by specifying implementation rules for test logic and test mode entry/exit methods included in memory ICs as guidance both to IC vendors implementing the standard and to test equipment manufacturers supporting this standard. The standard is aimed at ICs that are otherwise not provisioned with design for testability (DFT) for any reason, targeting primarily memory devices but also allowing for implementation in other devices, while supporting the highest fault coverage and pin-level diagnostics of board-level connectivity faults on such devices. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Static Component Interconnection Test Protocol and Architecture" -notes: "Inactive-Reserved" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …} #channels: Doctrine\ORM\PersistentCollection {#7628 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#7613 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7645 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1648764000 {#7292 : 2022-04-01 00:00:00.0 Europe/Paris (+02:00) } -author: "" -publishedAt: DateTime @1308520800 {#7318 : 2011-06-20 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1648076400 {#7316 : 2022-03-24 00:00:00.0 Europe/Paris (+01:00) } -edition: null -coreDocument: "1581" -bookCollection: "" -pageCount: 61 -documents: Doctrine\ORM\PersistentCollection {#7465 …} -favorites: Doctrine\ORM\PersistentCollection {#7500 …} } +label: "Most Recent" +icon: "check-xs" -mostRecentAttributeCode: "most_recent" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …} } |
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| ProductCard | App\Twig\Components\ProductCard | 102.0 MiB | 6.42 ms | |
|---|---|---|---|---|
| Input props | [ "product" => App\Entity\Product\Product {#128377 #id: 9152 #code: "IEEE00001728" #attributes: Doctrine\ORM\PersistentCollection {#128360 …} #variants: Doctrine\ORM\PersistentCollection {#128358 …} #options: Doctrine\ORM\PersistentCollection {#128353 …} #associations: Doctrine\ORM\PersistentCollection {#128355 …} #createdAt: DateTime @1751038014 {#128350 : 2025-06-27 17:26:54.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#128385 : 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#128371 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#128462 #locale: "en_US" #translatable: App\Entity\Product\Product {#128377} #id: 31617 #name: "IEEE 1149.1:2001 (R2008)" #slug: "ieee-1149-1-2001-r2008-ieee00001728-240804" #description: """ Revision Standard - Superseded.<br />\n Circuitry that may be built into an integrated circuit to assist in the test, maintenance, and support of assembled printed circuit boards is defined. The circuitry includes a standard interface through which instructions and test data are communicated. A set of test features is defined, including a boundary-scan register, such that the component is able to respond to a minimum set of instructions designed to assist with testing of assembled printed circuit boards.<br />\n \t\t\t\t<br />\n This standard defines test logic that can be included in an integrated circuit to provide standardized approaches to<br />\n — testing the interconnections between integrated circuits once they have been assembled onto a<br />\n printed circuit board or other substrate;<br />\n — testing the integrated circuit itself; and<br />\n — observing or modifying circuit activity during the component's normal operation. The test logic consists of a boundary-scan register and other building blocks and is accessed through a Test Access Port (TAP).<br />\n As technology has changed, the original 1149.1 standard does not address the new needs of the end users. The purpose of this PAR is to address these new needs in the IEEE 1149.1 standard. The intended users are silicon vendors, silicon designers, board and system electronic manufacturers and test equiment manufacturers. The benefits are additional capabilities and ease-of-use of 1149.1 for the current technology of mix-signal devices, differential logic and programmable devices. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard Test Access Port and Boundary Scan Architecture" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#128369 …} #channels: Doctrine\ORM\PersistentCollection {#128362 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#128366 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#128364 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#128379 …} -apiLastModifiedAt: DateTime @1754517600 {#128336 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#128384 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @995839200 {#128343 : 2001-07-23 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: DateTime @1206572400 {#128356 : 2008-03-27 00:00:00.0 Europe/Paris (+01:00) } -canceledAt: null -edition: null -coreDocument: "1149.1" -bookCollection: "" -pageCount: 212 -documents: Doctrine\ORM\PersistentCollection {#128375 …} -favorites: Doctrine\ORM\PersistentCollection {#128373 …} } "layout" => "vertical" "showPrice" => true "showStatusBadges" => true "additionalClasses" => "product__teaser--with-grey-border" "hasStretchedLink" => true "hoverType" => "shadow" "linkLabel" => "See more" ] |
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| Attributes | [] |
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| Component | App\Twig\Components\ProductCard {#128433 +product: App\Entity\Product\Product {#128377 #id: 9152 #code: "IEEE00001728" #attributes: Doctrine\ORM\PersistentCollection {#128360 …} #variants: Doctrine\ORM\PersistentCollection {#128358 …} #options: Doctrine\ORM\PersistentCollection {#128353 …} #associations: Doctrine\ORM\PersistentCollection {#128355 …} #createdAt: DateTime @1751038014 {#128350 : 2025-06-27 17:26:54.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#128385 : 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#128371 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#128462 #locale: "en_US" #translatable: App\Entity\Product\Product {#128377} #id: 31617 #name: "IEEE 1149.1:2001 (R2008)" #slug: "ieee-1149-1-2001-r2008-ieee00001728-240804" #description: """ Revision Standard - Superseded.<br />\n Circuitry that may be built into an integrated circuit to assist in the test, maintenance, and support of assembled printed circuit boards is defined. The circuitry includes a standard interface through which instructions and test data are communicated. A set of test features is defined, including a boundary-scan register, such that the component is able to respond to a minimum set of instructions designed to assist with testing of assembled printed circuit boards.<br />\n \t\t\t\t<br />\n This standard defines test logic that can be included in an integrated circuit to provide standardized approaches to<br />\n — testing the interconnections between integrated circuits once they have been assembled onto a<br />\n printed circuit board or other substrate;<br />\n — testing the integrated circuit itself; and<br />\n — observing or modifying circuit activity during the component's normal operation. The test logic consists of a boundary-scan register and other building blocks and is accessed through a Test Access Port (TAP).<br />\n As technology has changed, the original 1149.1 standard does not address the new needs of the end users. The purpose of this PAR is to address these new needs in the IEEE 1149.1 standard. The intended users are silicon vendors, silicon designers, board and system electronic manufacturers and test equiment manufacturers. The benefits are additional capabilities and ease-of-use of 1149.1 for the current technology of mix-signal devices, differential logic and programmable devices. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard Test Access Port and Boundary Scan Architecture" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#128369 …} #channels: Doctrine\ORM\PersistentCollection {#128362 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#128366 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#128364 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#128379 …} -apiLastModifiedAt: DateTime @1754517600 {#128336 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#128384 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @995839200 {#128343 : 2001-07-23 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: DateTime @1206572400 {#128356 : 2008-03-27 00:00:00.0 Europe/Paris (+01:00) } -canceledAt: null -edition: null -coreDocument: "1149.1" -bookCollection: "" -pageCount: 212 -documents: Doctrine\ORM\PersistentCollection {#128375 …} -favorites: Doctrine\ORM\PersistentCollection {#128373 …} } +layout: "vertical" +showPrice: true +showStatusBadges: true +additionalClasses: "product__teaser--with-grey-border" +linkLabel: "See more" +imageFilter: "product_thumbnail_teaser" +hasStretchedLink: true +backgroundColor: "white" +hoverType: "shadow" } |
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| ProductState | App\Twig\Components\ProductState | 102.0 MiB | 0.19 ms | |
|---|---|---|---|---|
| Input props | [ "product" => App\Entity\Product\Product {#128377 #id: 9152 #code: "IEEE00001728" #attributes: Doctrine\ORM\PersistentCollection {#128360 …} #variants: Doctrine\ORM\PersistentCollection {#128358 …} #options: Doctrine\ORM\PersistentCollection {#128353 …} #associations: Doctrine\ORM\PersistentCollection {#128355 …} #createdAt: DateTime @1751038014 {#128350 : 2025-06-27 17:26:54.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#128385 : 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#128371 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#128462 #locale: "en_US" #translatable: App\Entity\Product\Product {#128377} #id: 31617 #name: "IEEE 1149.1:2001 (R2008)" #slug: "ieee-1149-1-2001-r2008-ieee00001728-240804" #description: """ Revision Standard - Superseded.<br />\n Circuitry that may be built into an integrated circuit to assist in the test, maintenance, and support of assembled printed circuit boards is defined. The circuitry includes a standard interface through which instructions and test data are communicated. A set of test features is defined, including a boundary-scan register, such that the component is able to respond to a minimum set of instructions designed to assist with testing of assembled printed circuit boards.<br />\n \t\t\t\t<br />\n This standard defines test logic that can be included in an integrated circuit to provide standardized approaches to<br />\n — testing the interconnections between integrated circuits once they have been assembled onto a<br />\n printed circuit board or other substrate;<br />\n — testing the integrated circuit itself; and<br />\n — observing or modifying circuit activity during the component's normal operation. The test logic consists of a boundary-scan register and other building blocks and is accessed through a Test Access Port (TAP).<br />\n As technology has changed, the original 1149.1 standard does not address the new needs of the end users. The purpose of this PAR is to address these new needs in the IEEE 1149.1 standard. The intended users are silicon vendors, silicon designers, board and system electronic manufacturers and test equiment manufacturers. The benefits are additional capabilities and ease-of-use of 1149.1 for the current technology of mix-signal devices, differential logic and programmable devices. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard Test Access Port and Boundary Scan Architecture" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#128369 …} #channels: Doctrine\ORM\PersistentCollection {#128362 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#128366 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#128364 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#128379 …} -apiLastModifiedAt: DateTime @1754517600 {#128336 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#128384 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @995839200 {#128343 : 2001-07-23 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: DateTime @1206572400 {#128356 : 2008-03-27 00:00:00.0 Europe/Paris (+01:00) } -canceledAt: null -edition: null -coreDocument: "1149.1" -bookCollection: "" -pageCount: 212 -documents: Doctrine\ORM\PersistentCollection {#128375 …} -favorites: Doctrine\ORM\PersistentCollection {#128373 …} } ] |
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| Attributes | [ "showFullLabel" => false ] |
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| Component | App\Twig\Components\ProductState {#128466 +product: App\Entity\Product\Product {#128377 #id: 9152 #code: "IEEE00001728" #attributes: Doctrine\ORM\PersistentCollection {#128360 …} #variants: Doctrine\ORM\PersistentCollection {#128358 …} #options: Doctrine\ORM\PersistentCollection {#128353 …} #associations: Doctrine\ORM\PersistentCollection {#128355 …} #createdAt: DateTime @1751038014 {#128350 : 2025-06-27 17:26:54.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#128385 : 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#128371 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#128462 #locale: "en_US" #translatable: App\Entity\Product\Product {#128377} #id: 31617 #name: "IEEE 1149.1:2001 (R2008)" #slug: "ieee-1149-1-2001-r2008-ieee00001728-240804" #description: """ Revision Standard - Superseded.<br />\n Circuitry that may be built into an integrated circuit to assist in the test, maintenance, and support of assembled printed circuit boards is defined. The circuitry includes a standard interface through which instructions and test data are communicated. A set of test features is defined, including a boundary-scan register, such that the component is able to respond to a minimum set of instructions designed to assist with testing of assembled printed circuit boards.<br />\n \t\t\t\t<br />\n This standard defines test logic that can be included in an integrated circuit to provide standardized approaches to<br />\n — testing the interconnections between integrated circuits once they have been assembled onto a<br />\n printed circuit board or other substrate;<br />\n — testing the integrated circuit itself; and<br />\n — observing or modifying circuit activity during the component's normal operation. The test logic consists of a boundary-scan register and other building blocks and is accessed through a Test Access Port (TAP).<br />\n As technology has changed, the original 1149.1 standard does not address the new needs of the end users. The purpose of this PAR is to address these new needs in the IEEE 1149.1 standard. The intended users are silicon vendors, silicon designers, board and system electronic manufacturers and test equiment manufacturers. The benefits are additional capabilities and ease-of-use of 1149.1 for the current technology of mix-signal devices, differential logic and programmable devices. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard Test Access Port and Boundary Scan Architecture" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#128369 …} #channels: Doctrine\ORM\PersistentCollection {#128362 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#128366 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#128364 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#128379 …} -apiLastModifiedAt: DateTime @1754517600 {#128336 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#128384 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @995839200 {#128343 : 2001-07-23 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: DateTime @1206572400 {#128356 : 2008-03-27 00:00:00.0 Europe/Paris (+01:00) } -canceledAt: null -edition: null -coreDocument: "1149.1" -bookCollection: "" -pageCount: 212 -documents: Doctrine\ORM\PersistentCollection {#128375 …} -favorites: Doctrine\ORM\PersistentCollection {#128373 …} } +appearance: "state-suspended" +labels: [ "Superseded" ] -stateAttributeCode: "state" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …} } |
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| ProductMostRecent | App\Twig\Components\ProductMostRecent | 102.0 MiB | 0.73 ms | |
|---|---|---|---|---|
| Input props | [ "product" => App\Entity\Product\Product {#128377 #id: 9152 #code: "IEEE00001728" #attributes: Doctrine\ORM\PersistentCollection {#128360 …} #variants: Doctrine\ORM\PersistentCollection {#128358 …} #options: Doctrine\ORM\PersistentCollection {#128353 …} #associations: Doctrine\ORM\PersistentCollection {#128355 …} #createdAt: DateTime @1751038014 {#128350 : 2025-06-27 17:26:54.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#128385 : 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#128371 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#128462 #locale: "en_US" #translatable: App\Entity\Product\Product {#128377} #id: 31617 #name: "IEEE 1149.1:2001 (R2008)" #slug: "ieee-1149-1-2001-r2008-ieee00001728-240804" #description: """ Revision Standard - Superseded.<br />\n Circuitry that may be built into an integrated circuit to assist in the test, maintenance, and support of assembled printed circuit boards is defined. The circuitry includes a standard interface through which instructions and test data are communicated. A set of test features is defined, including a boundary-scan register, such that the component is able to respond to a minimum set of instructions designed to assist with testing of assembled printed circuit boards.<br />\n \t\t\t\t<br />\n This standard defines test logic that can be included in an integrated circuit to provide standardized approaches to<br />\n — testing the interconnections between integrated circuits once they have been assembled onto a<br />\n printed circuit board or other substrate;<br />\n — testing the integrated circuit itself; and<br />\n — observing or modifying circuit activity during the component's normal operation. The test logic consists of a boundary-scan register and other building blocks and is accessed through a Test Access Port (TAP).<br />\n As technology has changed, the original 1149.1 standard does not address the new needs of the end users. The purpose of this PAR is to address these new needs in the IEEE 1149.1 standard. The intended users are silicon vendors, silicon designers, board and system electronic manufacturers and test equiment manufacturers. The benefits are additional capabilities and ease-of-use of 1149.1 for the current technology of mix-signal devices, differential logic and programmable devices. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard Test Access Port and Boundary Scan Architecture" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#128369 …} #channels: Doctrine\ORM\PersistentCollection {#128362 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#128366 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#128364 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#128379 …} -apiLastModifiedAt: DateTime @1754517600 {#128336 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#128384 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @995839200 {#128343 : 2001-07-23 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: DateTime @1206572400 {#128356 : 2008-03-27 00:00:00.0 Europe/Paris (+01:00) } -canceledAt: null -edition: null -coreDocument: "1149.1" -bookCollection: "" -pageCount: 212 -documents: Doctrine\ORM\PersistentCollection {#128375 …} -favorites: Doctrine\ORM\PersistentCollection {#128373 …} } ] |
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| Attributes | [] |
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| Component | App\Twig\Components\ProductMostRecent {#128544 +product: App\Entity\Product\Product {#128377 #id: 9152 #code: "IEEE00001728" #attributes: Doctrine\ORM\PersistentCollection {#128360 …} #variants: Doctrine\ORM\PersistentCollection {#128358 …} #options: Doctrine\ORM\PersistentCollection {#128353 …} #associations: Doctrine\ORM\PersistentCollection {#128355 …} #createdAt: DateTime @1751038014 {#128350 : 2025-06-27 17:26:54.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#128385 : 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#128371 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#128462 #locale: "en_US" #translatable: App\Entity\Product\Product {#128377} #id: 31617 #name: "IEEE 1149.1:2001 (R2008)" #slug: "ieee-1149-1-2001-r2008-ieee00001728-240804" #description: """ Revision Standard - Superseded.<br />\n Circuitry that may be built into an integrated circuit to assist in the test, maintenance, and support of assembled printed circuit boards is defined. The circuitry includes a standard interface through which instructions and test data are communicated. A set of test features is defined, including a boundary-scan register, such that the component is able to respond to a minimum set of instructions designed to assist with testing of assembled printed circuit boards.<br />\n \t\t\t\t<br />\n This standard defines test logic that can be included in an integrated circuit to provide standardized approaches to<br />\n — testing the interconnections between integrated circuits once they have been assembled onto a<br />\n printed circuit board or other substrate;<br />\n — testing the integrated circuit itself; and<br />\n — observing or modifying circuit activity during the component's normal operation. The test logic consists of a boundary-scan register and other building blocks and is accessed through a Test Access Port (TAP).<br />\n As technology has changed, the original 1149.1 standard does not address the new needs of the end users. The purpose of this PAR is to address these new needs in the IEEE 1149.1 standard. The intended users are silicon vendors, silicon designers, board and system electronic manufacturers and test equiment manufacturers. The benefits are additional capabilities and ease-of-use of 1149.1 for the current technology of mix-signal devices, differential logic and programmable devices. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard Test Access Port and Boundary Scan Architecture" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#128369 …} #channels: Doctrine\ORM\PersistentCollection {#128362 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#128366 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#128364 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#128379 …} -apiLastModifiedAt: DateTime @1754517600 {#128336 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#128384 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @995839200 {#128343 : 2001-07-23 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: DateTime @1206572400 {#128356 : 2008-03-27 00:00:00.0 Europe/Paris (+01:00) } -canceledAt: null -edition: null -coreDocument: "1149.1" -bookCollection: "" -pageCount: 212 -documents: Doctrine\ORM\PersistentCollection {#128375 …} -favorites: Doctrine\ORM\PersistentCollection {#128373 …} } +label: "Historical" +icon: "historical" -mostRecentAttributeCode: "most_recent" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …} } |
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