Components

4 Twig Components
8 Render Count
14 ms Render Time
158.0 MiB Memory Usage

Components

Name Metadata Render Count Render Time
ProductState
"App\Twig\Components\ProductState"
components/ProductState.html.twig
3 0.81ms
ProductMostRecent
"App\Twig\Components\ProductMostRecent"
components/ProductMostRecent.html.twig
3 2.61ms
ProductType
"App\Twig\Components\ProductType"
components/ProductType.html.twig
1 0.28ms
ProductCard
"App\Twig\Components\ProductCard"
components/ProductCard.html.twig
1 11.91ms

Render calls

ProductState App\Twig\Components\ProductState 158.0 MiB 0.35 ms
Input props
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    #code: "IEEE00004137"
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          Replaces IEEE Std 1364.1-2002. To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standard IEEE 1364.<br />\n
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Component
App\Twig\Components\ProductState {#93007
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ProductType App\Twig\Components\ProductType 158.0 MiB 0.28 ms
Input props
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Attributes
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Component
App\Twig\Components\ProductType {#93187
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ProductMostRecent App\Twig\Components\ProductMostRecent 158.0 MiB 0.88 ms
Input props
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Attributes
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Component
App\Twig\Components\ProductMostRecent {#93262
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ProductState App\Twig\Components\ProductState 158.0 MiB 0.20 ms
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Component
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