GET https://dev.normadoc.fr/products/ieee-896-1-1987-ieee00001268-240567

Components

3 Twig Components
7 Render Count
3 ms Render Time
310.0 MiB Memory Usage

Components

Name Metadata Render Count Render Time
ProductState
"App\Twig\Components\ProductState"
components/ProductState.html.twig
3 0.67ms
ProductMostRecent
"App\Twig\Components\ProductMostRecent"
components/ProductMostRecent.html.twig
3 1.98ms
ProductType
"App\Twig\Components\ProductType"
components/ProductType.html.twig
1 0.21ms

Render calls

ProductState App\Twig\Components\ProductState 310.0 MiB 0.30 ms
Input props
[
  "product" => App\Entity\Product\Product {#7310
    #id: 8915
    #code: "IEEE00001268"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751037816 {#7274
      date: 2025-06-27 17:23:36.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754606304 {#7322
      date: 2025-08-08 00:38:24.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 30669
        #name: "IEEE 896.1:1987"
        #slug: "ieee-896-1-1987-ieee00001268-240567"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          This document provides a level of specification sufficient to design modules that are functionally, operationally, electrically, and mechanically compatible. Additional documents are necessary only to promote a higher degree of system level compatibility in manufacturers’ products.<br />\n
          \t\t\t\t<br />\n
          This IEEE standard specifies the functional, electrical, and mechanical requirements for a set of signal lines that constitute a backplane bus, and for the interfacing<br />\n
          of boards connected to that bus. The bus provides the means for the transfer of binary digital information between boards over a single backplane. The number of physical modules is restricted to 24 due to electrical and mechanical constraints, even though slot addressing allows up to 31 modules. The modules may contain any combination of<br />\n
          one or more processors and immediate peripherals such as memory, peripheral, and communication controllers. Figure 1 shows a block diagram of a typical board.<br />\n
          %o connector pins are allocated for a serial bus, but the provision of such a bus is optional. The purpose of providing a serial bus would be to increase the degree of<br />\n
          fault tolerance and survivability of the system. In any high integrity system an alternate control path is required in order to prevent major system faults and<br />\n
          allow, at least partially, orderly operation in the event of a component failure associated with the parallel bus. A serial bus is the most cost-effective way of<br />\n
          providing such an alternate control path. The definition of the serial bus is outside the scope of this standard. It is anticipated that a common serial bus protocol will<br />\n
          be developed within the IEEE P1394 Working Group that will be applicable to all future parallel bus standards. Protocols are specified for the allocation of bus time to modules needing to conduct transactions with other modules over the bus. However, the standard does not lay down mandatory priority rules for modules to use when competing for use of the bus. These are considered the responsibility and privilege of the system implementer. The standard includes a full set of signaling rules to be followed by all modules in the distributed control acquisition process leading to bus mastership (Section 6). The standard also gives a full set of signaling rules for all modules participating in a bus transaction (Section 7).
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Backplane Bus Specifications for Multiprocessor Architectures: Futurebus+(R)"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @586044000 {#7318
      date: 1988-07-28 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "896.1"
    -bookCollection: ""
    -pageCount: 64
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  "showFullLabel" => "true"
]
Attributes
[
  "showFullLabel" => "true"
]
Component
App\Twig\Components\ProductState {#93007
  +product: App\Entity\Product\Product {#7310
    #id: 8915
    #code: "IEEE00001268"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751037816 {#7274
      date: 2025-06-27 17:23:36.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754606304 {#7322
      date: 2025-08-08 00:38:24.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 30669
        #name: "IEEE 896.1:1987"
        #slug: "ieee-896-1-1987-ieee00001268-240567"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          This document provides a level of specification sufficient to design modules that are functionally, operationally, electrically, and mechanically compatible. Additional documents are necessary only to promote a higher degree of system level compatibility in manufacturers’ products.<br />\n
          \t\t\t\t<br />\n
          This IEEE standard specifies the functional, electrical, and mechanical requirements for a set of signal lines that constitute a backplane bus, and for the interfacing<br />\n
          of boards connected to that bus. The bus provides the means for the transfer of binary digital information between boards over a single backplane. The number of physical modules is restricted to 24 due to electrical and mechanical constraints, even though slot addressing allows up to 31 modules. The modules may contain any combination of<br />\n
          one or more processors and immediate peripherals such as memory, peripheral, and communication controllers. Figure 1 shows a block diagram of a typical board.<br />\n
          %o connector pins are allocated for a serial bus, but the provision of such a bus is optional. The purpose of providing a serial bus would be to increase the degree of<br />\n
          fault tolerance and survivability of the system. In any high integrity system an alternate control path is required in order to prevent major system faults and<br />\n
          allow, at least partially, orderly operation in the event of a component failure associated with the parallel bus. A serial bus is the most cost-effective way of<br />\n
          providing such an alternate control path. The definition of the serial bus is outside the scope of this standard. It is anticipated that a common serial bus protocol will<br />\n
          be developed within the IEEE P1394 Working Group that will be applicable to all future parallel bus standards. Protocols are specified for the allocation of bus time to modules needing to conduct transactions with other modules over the bus. However, the standard does not lay down mandatory priority rules for modules to use when competing for use of the bus. These are considered the responsibility and privilege of the system implementer. The standard includes a full set of signaling rules to be followed by all modules in the distributed control acquisition process leading to bus mastership (Section 6). The standard also gives a full set of signaling rules for all modules participating in a bus transaction (Section 7).
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Backplane Bus Specifications for Multiprocessor Architectures: Futurebus+(R)"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @586044000 {#7318
      date: 1988-07-28 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "896.1"
    -bookCollection: ""
    -pageCount: 64
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductType App\Twig\Components\ProductType 310.0 MiB 0.21 ms
Input props
[
  "product" => App\Entity\Product\Product {#7310
    #id: 8915
    #code: "IEEE00001268"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751037816 {#7274
      date: 2025-06-27 17:23:36.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754606304 {#7322
      date: 2025-08-08 00:38:24.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 30669
        #name: "IEEE 896.1:1987"
        #slug: "ieee-896-1-1987-ieee00001268-240567"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          This document provides a level of specification sufficient to design modules that are functionally, operationally, electrically, and mechanically compatible. Additional documents are necessary only to promote a higher degree of system level compatibility in manufacturers’ products.<br />\n
          \t\t\t\t<br />\n
          This IEEE standard specifies the functional, electrical, and mechanical requirements for a set of signal lines that constitute a backplane bus, and for the interfacing<br />\n
          of boards connected to that bus. The bus provides the means for the transfer of binary digital information between boards over a single backplane. The number of physical modules is restricted to 24 due to electrical and mechanical constraints, even though slot addressing allows up to 31 modules. The modules may contain any combination of<br />\n
          one or more processors and immediate peripherals such as memory, peripheral, and communication controllers. Figure 1 shows a block diagram of a typical board.<br />\n
          %o connector pins are allocated for a serial bus, but the provision of such a bus is optional. The purpose of providing a serial bus would be to increase the degree of<br />\n
          fault tolerance and survivability of the system. In any high integrity system an alternate control path is required in order to prevent major system faults and<br />\n
          allow, at least partially, orderly operation in the event of a component failure associated with the parallel bus. A serial bus is the most cost-effective way of<br />\n
          providing such an alternate control path. The definition of the serial bus is outside the scope of this standard. It is anticipated that a common serial bus protocol will<br />\n
          be developed within the IEEE P1394 Working Group that will be applicable to all future parallel bus standards. Protocols are specified for the allocation of bus time to modules needing to conduct transactions with other modules over the bus. However, the standard does not lay down mandatory priority rules for modules to use when competing for use of the bus. These are considered the responsibility and privilege of the system implementer. The standard includes a full set of signaling rules to be followed by all modules in the distributed control acquisition process leading to bus mastership (Section 6). The standard also gives a full set of signaling rules for all modules participating in a bus transaction (Section 7).
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Backplane Bus Specifications for Multiprocessor Architectures: Futurebus+(R)"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @586044000 {#7318
      date: 1988-07-28 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "896.1"
    -bookCollection: ""
    -pageCount: 64
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
]
Attributes
[]
Component
App\Twig\Components\ProductType {#93187
  +product: App\Entity\Product\Product {#7310
    #id: 8915
    #code: "IEEE00001268"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751037816 {#7274
      date: 2025-06-27 17:23:36.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754606304 {#7322
      date: 2025-08-08 00:38:24.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 30669
        #name: "IEEE 896.1:1987"
        #slug: "ieee-896-1-1987-ieee00001268-240567"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          This document provides a level of specification sufficient to design modules that are functionally, operationally, electrically, and mechanically compatible. Additional documents are necessary only to promote a higher degree of system level compatibility in manufacturers’ products.<br />\n
          \t\t\t\t<br />\n
          This IEEE standard specifies the functional, electrical, and mechanical requirements for a set of signal lines that constitute a backplane bus, and for the interfacing<br />\n
          of boards connected to that bus. The bus provides the means for the transfer of binary digital information between boards over a single backplane. The number of physical modules is restricted to 24 due to electrical and mechanical constraints, even though slot addressing allows up to 31 modules. The modules may contain any combination of<br />\n
          one or more processors and immediate peripherals such as memory, peripheral, and communication controllers. Figure 1 shows a block diagram of a typical board.<br />\n
          %o connector pins are allocated for a serial bus, but the provision of such a bus is optional. The purpose of providing a serial bus would be to increase the degree of<br />\n
          fault tolerance and survivability of the system. In any high integrity system an alternate control path is required in order to prevent major system faults and<br />\n
          allow, at least partially, orderly operation in the event of a component failure associated with the parallel bus. A serial bus is the most cost-effective way of<br />\n
          providing such an alternate control path. The definition of the serial bus is outside the scope of this standard. It is anticipated that a common serial bus protocol will<br />\n
          be developed within the IEEE P1394 Working Group that will be applicable to all future parallel bus standards. Protocols are specified for the allocation of bus time to modules needing to conduct transactions with other modules over the bus. However, the standard does not lay down mandatory priority rules for modules to use when competing for use of the bus. These are considered the responsibility and privilege of the system implementer. The standard includes a full set of signaling rules to be followed by all modules in the distributed control acquisition process leading to bus mastership (Section 6). The standard also gives a full set of signaling rules for all modules participating in a bus transaction (Section 7).
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Backplane Bus Specifications for Multiprocessor Architectures: Futurebus+(R)"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @586044000 {#7318
      date: 1988-07-28 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "896.1"
    -bookCollection: ""
    -pageCount: 64
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +label: "Standard"
  -typeAttributeCode: "type"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductMostRecent App\Twig\Components\ProductMostRecent 310.0 MiB 0.65 ms
Input props
[
  "product" => App\Entity\Product\Product {#7310
    #id: 8915
    #code: "IEEE00001268"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751037816 {#7274
      date: 2025-06-27 17:23:36.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754606304 {#7322
      date: 2025-08-08 00:38:24.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 30669
        #name: "IEEE 896.1:1987"
        #slug: "ieee-896-1-1987-ieee00001268-240567"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          This document provides a level of specification sufficient to design modules that are functionally, operationally, electrically, and mechanically compatible. Additional documents are necessary only to promote a higher degree of system level compatibility in manufacturers’ products.<br />\n
          \t\t\t\t<br />\n
          This IEEE standard specifies the functional, electrical, and mechanical requirements for a set of signal lines that constitute a backplane bus, and for the interfacing<br />\n
          of boards connected to that bus. The bus provides the means for the transfer of binary digital information between boards over a single backplane. The number of physical modules is restricted to 24 due to electrical and mechanical constraints, even though slot addressing allows up to 31 modules. The modules may contain any combination of<br />\n
          one or more processors and immediate peripherals such as memory, peripheral, and communication controllers. Figure 1 shows a block diagram of a typical board.<br />\n
          %o connector pins are allocated for a serial bus, but the provision of such a bus is optional. The purpose of providing a serial bus would be to increase the degree of<br />\n
          fault tolerance and survivability of the system. In any high integrity system an alternate control path is required in order to prevent major system faults and<br />\n
          allow, at least partially, orderly operation in the event of a component failure associated with the parallel bus. A serial bus is the most cost-effective way of<br />\n
          providing such an alternate control path. The definition of the serial bus is outside the scope of this standard. It is anticipated that a common serial bus protocol will<br />\n
          be developed within the IEEE P1394 Working Group that will be applicable to all future parallel bus standards. Protocols are specified for the allocation of bus time to modules needing to conduct transactions with other modules over the bus. However, the standard does not lay down mandatory priority rules for modules to use when competing for use of the bus. These are considered the responsibility and privilege of the system implementer. The standard includes a full set of signaling rules to be followed by all modules in the distributed control acquisition process leading to bus mastership (Section 6). The standard also gives a full set of signaling rules for all modules participating in a bus transaction (Section 7).
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Backplane Bus Specifications for Multiprocessor Architectures: Futurebus+(R)"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @586044000 {#7318
      date: 1988-07-28 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "896.1"
    -bookCollection: ""
    -pageCount: 64
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
]
Attributes
[]
Component
App\Twig\Components\ProductMostRecent {#93262
  +product: App\Entity\Product\Product {#7310
    #id: 8915
    #code: "IEEE00001268"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751037816 {#7274
      date: 2025-06-27 17:23:36.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754606304 {#7322
      date: 2025-08-08 00:38:24.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 30669
        #name: "IEEE 896.1:1987"
        #slug: "ieee-896-1-1987-ieee00001268-240567"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          This document provides a level of specification sufficient to design modules that are functionally, operationally, electrically, and mechanically compatible. Additional documents are necessary only to promote a higher degree of system level compatibility in manufacturers’ products.<br />\n
          \t\t\t\t<br />\n
          This IEEE standard specifies the functional, electrical, and mechanical requirements for a set of signal lines that constitute a backplane bus, and for the interfacing<br />\n
          of boards connected to that bus. The bus provides the means for the transfer of binary digital information between boards over a single backplane. The number of physical modules is restricted to 24 due to electrical and mechanical constraints, even though slot addressing allows up to 31 modules. The modules may contain any combination of<br />\n
          one or more processors and immediate peripherals such as memory, peripheral, and communication controllers. Figure 1 shows a block diagram of a typical board.<br />\n
          %o connector pins are allocated for a serial bus, but the provision of such a bus is optional. The purpose of providing a serial bus would be to increase the degree of<br />\n
          fault tolerance and survivability of the system. In any high integrity system an alternate control path is required in order to prevent major system faults and<br />\n
          allow, at least partially, orderly operation in the event of a component failure associated with the parallel bus. A serial bus is the most cost-effective way of<br />\n
          providing such an alternate control path. The definition of the serial bus is outside the scope of this standard. It is anticipated that a common serial bus protocol will<br />\n
          be developed within the IEEE P1394 Working Group that will be applicable to all future parallel bus standards. Protocols are specified for the allocation of bus time to modules needing to conduct transactions with other modules over the bus. However, the standard does not lay down mandatory priority rules for modules to use when competing for use of the bus. These are considered the responsibility and privilege of the system implementer. The standard includes a full set of signaling rules to be followed by all modules in the distributed control acquisition process leading to bus mastership (Section 6). The standard also gives a full set of signaling rules for all modules participating in a bus transaction (Section 7).
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Backplane Bus Specifications for Multiprocessor Architectures: Futurebus+(R)"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @586044000 {#7318
      date: 1988-07-28 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "896.1"
    -bookCollection: ""
    -pageCount: 64
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +label: "Historical"
  +icon: "historical"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductState App\Twig\Components\ProductState 310.0 MiB 0.19 ms
Input props
[
  "product" => App\Entity\Product\Product {#93672
    #id: 8916
    #code: "IEEE00001269"
    #attributes: Doctrine\ORM\PersistentCollection {#93652 …}
    #variants: Doctrine\ORM\PersistentCollection {#93649 …}
    #options: Doctrine\ORM\PersistentCollection {#93645 …}
    #associations: Doctrine\ORM\PersistentCollection {#93641 …}
    #createdAt: DateTime @1751037817 {#93679
      date: 2025-06-27 17:23:37.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754606304 {#93658
      date: 2025-08-08 00:38:24.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#93663 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#93704
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#93672}
        #id: 30673
        #name: "IEEE 896.1:1991"
        #slug: "ieee-896-1-1991-ieee00001269-240568"
        #description: """
          Revision Standard - Inactive-Withdrawn.<br />\n
          IEEE Std 896.1-1991 provides a set of tools with which to implement a Futurebus+architecture with performance and cost scalability over time, for multiple generations of single- and multiple-bus multiprocessor systems. Although this specification is principally intended for 64-bit address and data operation, a fully compatible 32-bit subset is provided, along with compatible extensions to support 128- and 256-bit data highways. Allocation of bus bandwidth to competing modules is provided by either a fast centralized arbiter, or a fully distributed, one or two pass, parallel contention arbiter. Bus allocation rules are provided to suit the needs of both real-time (priority based) and fairness (equal opportunity access based) configurations. Transmission of data over the multiplexed address/data highway is governed by one of two intercompatible transmission methods: (1) a technology-independent, compelled-protocol, supporting broadcast, broadcall, and transfer intervention (the minimum requirement for all Futurebus+systems), and (2) a configurable transfer-rate, source-synchronized protocol supporting only block transfers and source-synchronized broadcast for systems requiring the highest possible performance.<br />\n
          \t\t\t\t
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Futurebus+(R) -- Logical Protocol Specification"
        -notes: "Inactive-Withdrawn"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#93661 …}
    #channels: Doctrine\ORM\PersistentCollection {#93654 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#93659 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#93656 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#93669 …}
    -apiLastModifiedAt: DateTime @1754517600 {#93642
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#93678
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @700182000 {#93677
      date: 1992-03-10 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: DateTime @881622000 {#93671
      date: 1997-12-09 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "896.1"
    -bookCollection: ""
    -pageCount: 208
    -documents: Doctrine\ORM\PersistentCollection {#93667 …}
    -favorites: Doctrine\ORM\PersistentCollection {#93665 …}
  }
  "showFullLabel" => "true"
]
Attributes
[
  "showFullLabel" => "true"
]
Component
App\Twig\Components\ProductState {#106840
  +product: App\Entity\Product\Product {#93672
    #id: 8916
    #code: "IEEE00001269"
    #attributes: Doctrine\ORM\PersistentCollection {#93652 …}
    #variants: Doctrine\ORM\PersistentCollection {#93649 …}
    #options: Doctrine\ORM\PersistentCollection {#93645 …}
    #associations: Doctrine\ORM\PersistentCollection {#93641 …}
    #createdAt: DateTime @1751037817 {#93679
      date: 2025-06-27 17:23:37.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754606304 {#93658
      date: 2025-08-08 00:38:24.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#93663 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#93704
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#93672}
        #id: 30673
        #name: "IEEE 896.1:1991"
        #slug: "ieee-896-1-1991-ieee00001269-240568"
        #description: """
          Revision Standard - Inactive-Withdrawn.<br />\n
          IEEE Std 896.1-1991 provides a set of tools with which to implement a Futurebus+architecture with performance and cost scalability over time, for multiple generations of single- and multiple-bus multiprocessor systems. Although this specification is principally intended for 64-bit address and data operation, a fully compatible 32-bit subset is provided, along with compatible extensions to support 128- and 256-bit data highways. Allocation of bus bandwidth to competing modules is provided by either a fast centralized arbiter, or a fully distributed, one or two pass, parallel contention arbiter. Bus allocation rules are provided to suit the needs of both real-time (priority based) and fairness (equal opportunity access based) configurations. Transmission of data over the multiplexed address/data highway is governed by one of two intercompatible transmission methods: (1) a technology-independent, compelled-protocol, supporting broadcast, broadcall, and transfer intervention (the minimum requirement for all Futurebus+systems), and (2) a configurable transfer-rate, source-synchronized protocol supporting only block transfers and source-synchronized broadcast for systems requiring the highest possible performance.<br />\n
          \t\t\t\t
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Futurebus+(R) -- Logical Protocol Specification"
        -notes: "Inactive-Withdrawn"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#93661 …}
    #channels: Doctrine\ORM\PersistentCollection {#93654 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#93659 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#93656 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#93669 …}
    -apiLastModifiedAt: DateTime @1754517600 {#93642
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#93678
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @700182000 {#93677
      date: 1992-03-10 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: DateTime @881622000 {#93671
      date: 1997-12-09 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "896.1"
    -bookCollection: ""
    -pageCount: 208
    -documents: Doctrine\ORM\PersistentCollection {#93667 …}
    -favorites: Doctrine\ORM\PersistentCollection {#93665 …}
  }
  +appearance: "state-withdrawn"
  +labels: [
    "Withdrawn"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductMostRecent App\Twig\Components\ProductMostRecent 310.0 MiB 0.72 ms
Input props
[
  "product" => App\Entity\Product\Product {#93672
    #id: 8916
    #code: "IEEE00001269"
    #attributes: Doctrine\ORM\PersistentCollection {#93652 …}
    #variants: Doctrine\ORM\PersistentCollection {#93649 …}
    #options: Doctrine\ORM\PersistentCollection {#93645 …}
    #associations: Doctrine\ORM\PersistentCollection {#93641 …}
    #createdAt: DateTime @1751037817 {#93679
      date: 2025-06-27 17:23:37.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754606304 {#93658
      date: 2025-08-08 00:38:24.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#93663 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#93704
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#93672}
        #id: 30673
        #name: "IEEE 896.1:1991"
        #slug: "ieee-896-1-1991-ieee00001269-240568"
        #description: """
          Revision Standard - Inactive-Withdrawn.<br />\n
          IEEE Std 896.1-1991 provides a set of tools with which to implement a Futurebus+architecture with performance and cost scalability over time, for multiple generations of single- and multiple-bus multiprocessor systems. Although this specification is principally intended for 64-bit address and data operation, a fully compatible 32-bit subset is provided, along with compatible extensions to support 128- and 256-bit data highways. Allocation of bus bandwidth to competing modules is provided by either a fast centralized arbiter, or a fully distributed, one or two pass, parallel contention arbiter. Bus allocation rules are provided to suit the needs of both real-time (priority based) and fairness (equal opportunity access based) configurations. Transmission of data over the multiplexed address/data highway is governed by one of two intercompatible transmission methods: (1) a technology-independent, compelled-protocol, supporting broadcast, broadcall, and transfer intervention (the minimum requirement for all Futurebus+systems), and (2) a configurable transfer-rate, source-synchronized protocol supporting only block transfers and source-synchronized broadcast for systems requiring the highest possible performance.<br />\n
          \t\t\t\t
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Futurebus+(R) -- Logical Protocol Specification"
        -notes: "Inactive-Withdrawn"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#93661 …}
    #channels: Doctrine\ORM\PersistentCollection {#93654 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#93659 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#93656 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#93669 …}
    -apiLastModifiedAt: DateTime @1754517600 {#93642
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#93678
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @700182000 {#93677
      date: 1992-03-10 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: DateTime @881622000 {#93671
      date: 1997-12-09 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "896.1"
    -bookCollection: ""
    -pageCount: 208
    -documents: Doctrine\ORM\PersistentCollection {#93667 …}
    -favorites: Doctrine\ORM\PersistentCollection {#93665 …}
  }
]
Attributes
[]
Component
App\Twig\Components\ProductMostRecent {#106895
  +product: App\Entity\Product\Product {#93672
    #id: 8916
    #code: "IEEE00001269"
    #attributes: Doctrine\ORM\PersistentCollection {#93652 …}
    #variants: Doctrine\ORM\PersistentCollection {#93649 …}
    #options: Doctrine\ORM\PersistentCollection {#93645 …}
    #associations: Doctrine\ORM\PersistentCollection {#93641 …}
    #createdAt: DateTime @1751037817 {#93679
      date: 2025-06-27 17:23:37.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754606304 {#93658
      date: 2025-08-08 00:38:24.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#93663 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#93704
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#93672}
        #id: 30673
        #name: "IEEE 896.1:1991"
        #slug: "ieee-896-1-1991-ieee00001269-240568"
        #description: """
          Revision Standard - Inactive-Withdrawn.<br />\n
          IEEE Std 896.1-1991 provides a set of tools with which to implement a Futurebus+architecture with performance and cost scalability over time, for multiple generations of single- and multiple-bus multiprocessor systems. Although this specification is principally intended for 64-bit address and data operation, a fully compatible 32-bit subset is provided, along with compatible extensions to support 128- and 256-bit data highways. Allocation of bus bandwidth to competing modules is provided by either a fast centralized arbiter, or a fully distributed, one or two pass, parallel contention arbiter. Bus allocation rules are provided to suit the needs of both real-time (priority based) and fairness (equal opportunity access based) configurations. Transmission of data over the multiplexed address/data highway is governed by one of two intercompatible transmission methods: (1) a technology-independent, compelled-protocol, supporting broadcast, broadcall, and transfer intervention (the minimum requirement for all Futurebus+systems), and (2) a configurable transfer-rate, source-synchronized protocol supporting only block transfers and source-synchronized broadcast for systems requiring the highest possible performance.<br />\n
          \t\t\t\t
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Futurebus+(R) -- Logical Protocol Specification"
        -notes: "Inactive-Withdrawn"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#93661 …}
    #channels: Doctrine\ORM\PersistentCollection {#93654 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#93659 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#93656 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#93669 …}
    -apiLastModifiedAt: DateTime @1754517600 {#93642
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#93678
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @700182000 {#93677
      date: 1992-03-10 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: DateTime @881622000 {#93671
      date: 1997-12-09 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "896.1"
    -bookCollection: ""
    -pageCount: 208
    -documents: Doctrine\ORM\PersistentCollection {#93667 …}
    -favorites: Doctrine\ORM\PersistentCollection {#93665 …}
  }
  +label: "Most Recent"
  +icon: "check-xs"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductState App\Twig\Components\ProductState 310.0 MiB 0.18 ms
Input props
[
  "product" => App\Entity\Product\Product {#7310
    #id: 8915
    #code: "IEEE00001268"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751037816 {#7274
      date: 2025-06-27 17:23:36.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754606304 {#7322
      date: 2025-08-08 00:38:24.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 30669
        #name: "IEEE 896.1:1987"
        #slug: "ieee-896-1-1987-ieee00001268-240567"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          This document provides a level of specification sufficient to design modules that are functionally, operationally, electrically, and mechanically compatible. Additional documents are necessary only to promote a higher degree of system level compatibility in manufacturers’ products.<br />\n
          \t\t\t\t<br />\n
          This IEEE standard specifies the functional, electrical, and mechanical requirements for a set of signal lines that constitute a backplane bus, and for the interfacing<br />\n
          of boards connected to that bus. The bus provides the means for the transfer of binary digital information between boards over a single backplane. The number of physical modules is restricted to 24 due to electrical and mechanical constraints, even though slot addressing allows up to 31 modules. The modules may contain any combination of<br />\n
          one or more processors and immediate peripherals such as memory, peripheral, and communication controllers. Figure 1 shows a block diagram of a typical board.<br />\n
          %o connector pins are allocated for a serial bus, but the provision of such a bus is optional. The purpose of providing a serial bus would be to increase the degree of<br />\n
          fault tolerance and survivability of the system. In any high integrity system an alternate control path is required in order to prevent major system faults and<br />\n
          allow, at least partially, orderly operation in the event of a component failure associated with the parallel bus. A serial bus is the most cost-effective way of<br />\n
          providing such an alternate control path. The definition of the serial bus is outside the scope of this standard. It is anticipated that a common serial bus protocol will<br />\n
          be developed within the IEEE P1394 Working Group that will be applicable to all future parallel bus standards. Protocols are specified for the allocation of bus time to modules needing to conduct transactions with other modules over the bus. However, the standard does not lay down mandatory priority rules for modules to use when competing for use of the bus. These are considered the responsibility and privilege of the system implementer. The standard includes a full set of signaling rules to be followed by all modules in the distributed control acquisition process leading to bus mastership (Section 6). The standard also gives a full set of signaling rules for all modules participating in a bus transaction (Section 7).
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Backplane Bus Specifications for Multiprocessor Architectures: Futurebus+(R)"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @586044000 {#7318
      date: 1988-07-28 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "896.1"
    -bookCollection: ""
    -pageCount: 64
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  "showFullLabel" => "true"
]
Attributes
[
  "showFullLabel" => "true"
]
Component
App\Twig\Components\ProductState {#106960
  +product: App\Entity\Product\Product {#7310
    #id: 8915
    #code: "IEEE00001268"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751037816 {#7274
      date: 2025-06-27 17:23:36.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754606304 {#7322
      date: 2025-08-08 00:38:24.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 30669
        #name: "IEEE 896.1:1987"
        #slug: "ieee-896-1-1987-ieee00001268-240567"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          This document provides a level of specification sufficient to design modules that are functionally, operationally, electrically, and mechanically compatible. Additional documents are necessary only to promote a higher degree of system level compatibility in manufacturers’ products.<br />\n
          \t\t\t\t<br />\n
          This IEEE standard specifies the functional, electrical, and mechanical requirements for a set of signal lines that constitute a backplane bus, and for the interfacing<br />\n
          of boards connected to that bus. The bus provides the means for the transfer of binary digital information between boards over a single backplane. The number of physical modules is restricted to 24 due to electrical and mechanical constraints, even though slot addressing allows up to 31 modules. The modules may contain any combination of<br />\n
          one or more processors and immediate peripherals such as memory, peripheral, and communication controllers. Figure 1 shows a block diagram of a typical board.<br />\n
          %o connector pins are allocated for a serial bus, but the provision of such a bus is optional. The purpose of providing a serial bus would be to increase the degree of<br />\n
          fault tolerance and survivability of the system. In any high integrity system an alternate control path is required in order to prevent major system faults and<br />\n
          allow, at least partially, orderly operation in the event of a component failure associated with the parallel bus. A serial bus is the most cost-effective way of<br />\n
          providing such an alternate control path. The definition of the serial bus is outside the scope of this standard. It is anticipated that a common serial bus protocol will<br />\n
          be developed within the IEEE P1394 Working Group that will be applicable to all future parallel bus standards. Protocols are specified for the allocation of bus time to modules needing to conduct transactions with other modules over the bus. However, the standard does not lay down mandatory priority rules for modules to use when competing for use of the bus. These are considered the responsibility and privilege of the system implementer. The standard includes a full set of signaling rules to be followed by all modules in the distributed control acquisition process leading to bus mastership (Section 6). The standard also gives a full set of signaling rules for all modules participating in a bus transaction (Section 7).
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Backplane Bus Specifications for Multiprocessor Architectures: Futurebus+(R)"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @586044000 {#7318
      date: 1988-07-28 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "896.1"
    -bookCollection: ""
    -pageCount: 64
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductMostRecent App\Twig\Components\ProductMostRecent 310.0 MiB 0.61 ms
Input props
[
  "product" => App\Entity\Product\Product {#7310
    #id: 8915
    #code: "IEEE00001268"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751037816 {#7274
      date: 2025-06-27 17:23:36.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754606304 {#7322
      date: 2025-08-08 00:38:24.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 30669
        #name: "IEEE 896.1:1987"
        #slug: "ieee-896-1-1987-ieee00001268-240567"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          This document provides a level of specification sufficient to design modules that are functionally, operationally, electrically, and mechanically compatible. Additional documents are necessary only to promote a higher degree of system level compatibility in manufacturers’ products.<br />\n
          \t\t\t\t<br />\n
          This IEEE standard specifies the functional, electrical, and mechanical requirements for a set of signal lines that constitute a backplane bus, and for the interfacing<br />\n
          of boards connected to that bus. The bus provides the means for the transfer of binary digital information between boards over a single backplane. The number of physical modules is restricted to 24 due to electrical and mechanical constraints, even though slot addressing allows up to 31 modules. The modules may contain any combination of<br />\n
          one or more processors and immediate peripherals such as memory, peripheral, and communication controllers. Figure 1 shows a block diagram of a typical board.<br />\n
          %o connector pins are allocated for a serial bus, but the provision of such a bus is optional. The purpose of providing a serial bus would be to increase the degree of<br />\n
          fault tolerance and survivability of the system. In any high integrity system an alternate control path is required in order to prevent major system faults and<br />\n
          allow, at least partially, orderly operation in the event of a component failure associated with the parallel bus. A serial bus is the most cost-effective way of<br />\n
          providing such an alternate control path. The definition of the serial bus is outside the scope of this standard. It is anticipated that a common serial bus protocol will<br />\n
          be developed within the IEEE P1394 Working Group that will be applicable to all future parallel bus standards. Protocols are specified for the allocation of bus time to modules needing to conduct transactions with other modules over the bus. However, the standard does not lay down mandatory priority rules for modules to use when competing for use of the bus. These are considered the responsibility and privilege of the system implementer. The standard includes a full set of signaling rules to be followed by all modules in the distributed control acquisition process leading to bus mastership (Section 6). The standard also gives a full set of signaling rules for all modules participating in a bus transaction (Section 7).
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Backplane Bus Specifications for Multiprocessor Architectures: Futurebus+(R)"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @586044000 {#7318
      date: 1988-07-28 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "896.1"
    -bookCollection: ""
    -pageCount: 64
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
]
Attributes
[]
Component
App\Twig\Components\ProductMostRecent {#106987
  +product: App\Entity\Product\Product {#7310
    #id: 8915
    #code: "IEEE00001268"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751037816 {#7274
      date: 2025-06-27 17:23:36.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754606304 {#7322
      date: 2025-08-08 00:38:24.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 30669
        #name: "IEEE 896.1:1987"
        #slug: "ieee-896-1-1987-ieee00001268-240567"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          This document provides a level of specification sufficient to design modules that are functionally, operationally, electrically, and mechanically compatible. Additional documents are necessary only to promote a higher degree of system level compatibility in manufacturers’ products.<br />\n
          \t\t\t\t<br />\n
          This IEEE standard specifies the functional, electrical, and mechanical requirements for a set of signal lines that constitute a backplane bus, and for the interfacing<br />\n
          of boards connected to that bus. The bus provides the means for the transfer of binary digital information between boards over a single backplane. The number of physical modules is restricted to 24 due to electrical and mechanical constraints, even though slot addressing allows up to 31 modules. The modules may contain any combination of<br />\n
          one or more processors and immediate peripherals such as memory, peripheral, and communication controllers. Figure 1 shows a block diagram of a typical board.<br />\n
          %o connector pins are allocated for a serial bus, but the provision of such a bus is optional. The purpose of providing a serial bus would be to increase the degree of<br />\n
          fault tolerance and survivability of the system. In any high integrity system an alternate control path is required in order to prevent major system faults and<br />\n
          allow, at least partially, orderly operation in the event of a component failure associated with the parallel bus. A serial bus is the most cost-effective way of<br />\n
          providing such an alternate control path. The definition of the serial bus is outside the scope of this standard. It is anticipated that a common serial bus protocol will<br />\n
          be developed within the IEEE P1394 Working Group that will be applicable to all future parallel bus standards. Protocols are specified for the allocation of bus time to modules needing to conduct transactions with other modules over the bus. However, the standard does not lay down mandatory priority rules for modules to use when competing for use of the bus. These are considered the responsibility and privilege of the system implementer. The standard includes a full set of signaling rules to be followed by all modules in the distributed control acquisition process leading to bus mastership (Section 6). The standard also gives a full set of signaling rules for all modules participating in a bus transaction (Section 7).
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Backplane Bus Specifications for Multiprocessor Architectures: Futurebus+(R)"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @586044000 {#7318
      date: 1988-07-28 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "896.1"
    -bookCollection: ""
    -pageCount: 64
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +label: "Historical"
  +icon: "historical"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}