Components

3 Twig Components
7 Render Count
3 ms Render Time
680.0 MiB Memory Usage

Components

Name Metadata Render Count Render Time
ProductState
"App\Twig\Components\ProductState"
components/ProductState.html.twig
3 0.67ms
ProductMostRecent
"App\Twig\Components\ProductMostRecent"
components/ProductMostRecent.html.twig
3 1.97ms
ProductType
"App\Twig\Components\ProductType"
components/ProductType.html.twig
1 0.22ms

Render calls

ProductState App\Twig\Components\ProductState 680.0 MiB 0.30 ms
Input props
[
  "product" => App\Entity\Product\Product {#7519
    #id: 11378
    #code: "IEEE00006021"
    #attributes: Doctrine\ORM\PersistentCollection {#8208 …}
    #variants: Doctrine\ORM\PersistentCollection {#8290 …}
    #options: Doctrine\ORM\PersistentCollection {#8629 …}
    #associations: Doctrine\ORM\PersistentCollection {#8586 …}
    #createdAt: DateTime @1751039666 {#7536
      date: 2025-06-27 17:54:26.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754608190 {#7535
      date: 2025-08-08 01:09:50.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#8628 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#8613
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7519}
        #id: 40521
        #name: "IEEE 1800.2:2017"
        #slug: "ieee-1800-2-2017-ieee00006021-243030"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.<br />\n
          \t\t\t\t<br />\n
          This standard establishes the Universal Verification Methodology (UVM), a set of Application Programming Interfaces (APIs) that define a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE 1800 SystemVerilog standard.<br />\n
          Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically-dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting Intellectual Property (IP) for each new project or electronic design automation tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Universal Verification Methodology Language Reference Manual"
        -notes: "Superseded"
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    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7944 …}
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    #reviews: Doctrine\ORM\PersistentCollection {#8067 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#8119 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7682 …}
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    -apiLastModifiedAt: DateTime @1754517600 {#7530
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
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    -lastUpdatedAt: DateTime @1604012400 {#7496
      date: 2020-10-30 00:00:00.0 Europe/Paris (+01:00)
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    -author: ""
    -publishedAt: DateTime @1495749600 {#7531
      date: 2017-05-26 00:00:00.0 Europe/Paris (+02:00)
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      date: 2017-05-26 00:00:00.0 Europe/Paris (+02:00)
    }
    -edition: null
    -coreDocument: "1800.2"
    -bookCollection: ""
    -pageCount: 472
    -documents: Doctrine\ORM\PersistentCollection {#7787 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7929 …}
  }
  "showFullLabel" => "true"
]
Attributes
[
  "showFullLabel" => "true"
]
Component
App\Twig\Components\ProductState {#95062
  +product: App\Entity\Product\Product {#7519
    #id: 11378
    #code: "IEEE00006021"
    #attributes: Doctrine\ORM\PersistentCollection {#8208 …}
    #variants: Doctrine\ORM\PersistentCollection {#8290 …}
    #options: Doctrine\ORM\PersistentCollection {#8629 …}
    #associations: Doctrine\ORM\PersistentCollection {#8586 …}
    #createdAt: DateTime @1751039666 {#7536
      date: 2025-06-27 17:54:26.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754608190 {#7535
      date: 2025-08-08 01:09:50.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#8628 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#8613
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7519}
        #id: 40521
        #name: "IEEE 1800.2:2017"
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        #description: """
          New IEEE Standard - Superseded.<br />\n
          The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.<br />\n
          \t\t\t\t<br />\n
          This standard establishes the Universal Verification Methodology (UVM), a set of Application Programming Interfaces (APIs) that define a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE 1800 SystemVerilog standard.<br />\n
          Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically-dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting Intellectual Property (IP) for each new project or electronic design automation tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry.
          """
        #metaKeywords: null
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        #shortDescription: "IEEE Standard for Universal Verification Methodology Language Reference Manual"
        -notes: "Superseded"
      }
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    #currentLocale: "en_US"
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    #reviews: Doctrine\ORM\PersistentCollection {#8067 …}
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    #images: Doctrine\ORM\PersistentCollection {#8119 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7682 …}
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    -apiLastModifiedAt: DateTime @1754517600 {#7530
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1604012400 {#7496
      date: 2020-10-30 00:00:00.0 Europe/Paris (+01:00)
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    -author: ""
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      date: 2017-05-26 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
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      date: 2017-05-26 00:00:00.0 Europe/Paris (+02:00)
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    -coreDocument: "1800.2"
    -bookCollection: ""
    -pageCount: 472
    -documents: Doctrine\ORM\PersistentCollection {#7787 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7929 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductType App\Twig\Components\ProductType 680.0 MiB 0.22 ms
Input props
[
  "product" => App\Entity\Product\Product {#7519
    #id: 11378
    #code: "IEEE00006021"
    #attributes: Doctrine\ORM\PersistentCollection {#8208 …}
    #variants: Doctrine\ORM\PersistentCollection {#8290 …}
    #options: Doctrine\ORM\PersistentCollection {#8629 …}
    #associations: Doctrine\ORM\PersistentCollection {#8586 …}
    #createdAt: DateTime @1751039666 {#7536
      date: 2025-06-27 17:54:26.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754608190 {#7535
      date: 2025-08-08 01:09:50.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#8628 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#8613
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7519}
        #id: 40521
        #name: "IEEE 1800.2:2017"
        #slug: "ieee-1800-2-2017-ieee00006021-243030"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.<br />\n
          \t\t\t\t<br />\n
          This standard establishes the Universal Verification Methodology (UVM), a set of Application Programming Interfaces (APIs) that define a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE 1800 SystemVerilog standard.<br />\n
          Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically-dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting Intellectual Property (IP) for each new project or electronic design automation tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Universal Verification Methodology Language Reference Manual"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
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    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7944 …}
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    #reviews: Doctrine\ORM\PersistentCollection {#8067 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#8119 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7682 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7747 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7530
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
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    -lastUpdatedAt: DateTime @1604012400 {#7496
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    -author: ""
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    -pageCount: 472
    -documents: Doctrine\ORM\PersistentCollection {#7787 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7929 …}
  }
]
Attributes
[]
Component
App\Twig\Components\ProductType {#95242
  +product: App\Entity\Product\Product {#7519
    #id: 11378
    #code: "IEEE00006021"
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    #variants: Doctrine\ORM\PersistentCollection {#8290 …}
    #options: Doctrine\ORM\PersistentCollection {#8629 …}
    #associations: Doctrine\ORM\PersistentCollection {#8586 …}
    #createdAt: DateTime @1751039666 {#7536
      date: 2025-06-27 17:54:26.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754608190 {#7535
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    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#8628 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#8613
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7519}
        #id: 40521
        #name: "IEEE 1800.2:2017"
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        #description: """
          New IEEE Standard - Superseded.<br />\n
          The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.<br />\n
          \t\t\t\t<br />\n
          This standard establishes the Universal Verification Methodology (UVM), a set of Application Programming Interfaces (APIs) that define a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE 1800 SystemVerilog standard.<br />\n
          Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically-dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting Intellectual Property (IP) for each new project or electronic design automation tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry.
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        #metaKeywords: null
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        -notes: "Superseded"
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    #currentLocale: "en_US"
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    -apiLastModifiedAt: DateTime @1754517600 {#7530
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
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    -lastUpdatedAt: DateTime @1604012400 {#7496
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      date: 2017-05-26 00:00:00.0 Europe/Paris (+02:00)
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    -pageCount: 472
    -documents: Doctrine\ORM\PersistentCollection {#7787 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7929 …}
  }
  +label: "Standard"
  -typeAttributeCode: "type"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductMostRecent App\Twig\Components\ProductMostRecent 680.0 MiB 0.66 ms
Input props
[
  "product" => App\Entity\Product\Product {#7519
    #id: 11378
    #code: "IEEE00006021"
    #attributes: Doctrine\ORM\PersistentCollection {#8208 …}
    #variants: Doctrine\ORM\PersistentCollection {#8290 …}
    #options: Doctrine\ORM\PersistentCollection {#8629 …}
    #associations: Doctrine\ORM\PersistentCollection {#8586 …}
    #createdAt: DateTime @1751039666 {#7536
      date: 2025-06-27 17:54:26.0 Europe/Paris (+02:00)
    }
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      date: 2025-08-08 01:09:50.0 Europe/Paris (+02:00)
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      "en_US" => App\Entity\Product\ProductTranslation {#8613
        #locale: "en_US"
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          New IEEE Standard - Superseded.<br />\n
          The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.<br />\n
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          This standard establishes the Universal Verification Methodology (UVM), a set of Application Programming Interfaces (APIs) that define a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE 1800 SystemVerilog standard.<br />\n
          Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically-dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting Intellectual Property (IP) for each new project or electronic design automation tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry.
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Attributes
[]
Component
App\Twig\Components\ProductMostRecent {#95317
  +product: App\Entity\Product\Product {#7519
    #id: 11378
    #code: "IEEE00006021"
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    #enabled: true
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        #name: "IEEE 1800.2:2017"
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          New IEEE Standard - Superseded.<br />\n
          The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.<br />\n
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          This standard establishes the Universal Verification Methodology (UVM), a set of Application Programming Interfaces (APIs) that define a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE 1800 SystemVerilog standard.<br />\n
          Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically-dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting Intellectual Property (IP) for each new project or electronic design automation tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry.
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  +label: "Historical"
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  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductState App\Twig\Components\ProductState 680.0 MiB 0.20 ms
Input props
[
  "product" => App\Entity\Product\Product {#95731
    #id: 12374
    #code: "IEEE00007567"
    #attributes: Doctrine\ORM\PersistentCollection {#95711 …}
    #variants: Doctrine\ORM\PersistentCollection {#95708 …}
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