Forms
sylius_add_to_cart
Errors
This form has no errors.
Default Data
| Property | Value |
|---|---|
| Model Format | same as normalized format |
| Normalized Format | Sylius\Bundle\OrderBundle\Controller\AddToCartCommand {#113793 -cart: App\Entity\Order\Order {#13330 …} -cartItem: App\Entity\Order\OrderItem {#113781 #id: null #order: null #quantity: 1 #unitPrice: 0 #originalUnitPrice: 0 #total: 0 #immutable: false #units: Doctrine\Common\Collections\ArrayCollection {#113806 …} #unitsTotal: 0 #adjustments: Doctrine\Common\Collections\ArrayCollection {#113805 …} #adjustmentsTotal: 0 #version: 1 #variant: App\Entity\Product\ProductVariant {#8099 #id: 4126 #code: "IEEE00003617PDF" #product: App\Entity\Product\Product {#7310 #id: 10090 #code: "IEEE00003617" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …} #initialized: true -snapshot: [ …4] -owner: App\Entity\Product\Product {#7310} -association: [ …21] -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …} -backRefFieldName: null -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#223708 …} -isDirty: false } #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751038807 {#7274 : 2025-06-27 17:40:07.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607004 {#7322 : 2025-08-08 00:50:04.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 35369 #name: "IEEE 1800:2005" #slug: "ieee-1800-2005-ieee00003617-241742" #description: """ New IEEE Standard - Superseded.<br />\n This standard represents a merger of two previous standards: IEEE 1364-2005 Verilog hardware description language (HDL) and IEEE 1800-2005 SystemVerilog unified hardware design, specification and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard enables users to have all information regarding syntax and semantics in a single document.<br />\n \t\t\t\t<br />\n SystemVerilog is a Unified Hardware Design, Specification and Verification language that is based on the work done by Accellera, a consortium of Electronic Design Automation (EDA), semiconductor, and system companies. The proposed project will create an IEEE standard that is leveraged from Accellera SystemVerilog 3.1a. The new standard will include design specification methods, embedded assertions language, test bench language including coverage and assertions API, and a direct programming interface. The proposed SystemVerilog standard enables a productivity boost in design and validation, and covers design, simulation, validation, and formal assertion based verification flows.<br />\n The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a well-defined and official IEEE Unified Hardware Design, Specification and Verification standard language. The language is designed to co-exist and enhance those hardware description languages presently used by designers while providing the capabilities lacking in those languages. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for SystemVerilog: Unified Hardware Design, Specification and Verification Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1132614000 {#7318 : 2005-11-22 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1800" -bookCollection: "" -pageCount: 648 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } #optionValues: Doctrine\ORM\PersistentCollection {#8315 …} #position: 0 #createdAt: DateTime @1751041185 {#7966 : 2025-06-27 18:19:45.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1755611983 {#8116 : 2025-08-19 15:59:43.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#8259 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductVariantTranslation {#93313 #locale: "en_US" #translatable: App\Entity\Product\ProductVariant {#8099} #id: 4144 #name: null -shortDescription: null -description: null -notes: null -shippingInformation: "Instant download" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #version: 9 #onHold: 0 #onHand: 0 #tracked: false #weight: 0.0 #width: null #height: null #depth: null #taxCategory: Proxies\__CG__\App\Entity\Taxation\TaxCategory {#8131 …} #shippingCategory: null #channelPricings: Doctrine\ORM\PersistentCollection {#8293 …} #shippingRequired: true #images: Doctrine\ORM\PersistentCollection {#8290 …} -apiLastModifiedAt: DateTime @1753740000 {#8098 : 2025-07-29 00:00:00.0 Europe/Paris (+02:00) } -publishedAt: null -isbn: "978-0-7381-4811-3" -ean: "9780738148113" -numberOfUsers: 1 -physicalProduct: false -downloadableImmediately: true -downloadable: true -drmViewerUrl: "https://online-viewer.normadoc.com/bcu4KN" -sellable: true -documents: Doctrine\ORM\PersistentCollection {#8127 …} -drmTokens: Doctrine\ORM\PersistentCollection {#8119 …} -enabledForSubscribers: true -currentAreaContext: null } #productName: null #variantName: null } } |
| View Format | same as normalized format |
Submitted Data
This form was not submitted.
Passed Options
| Option | Passed Value | Resolved Value |
|---|---|---|
| data | Sylius\Bundle\OrderBundle\Controller\AddToCartCommand {#113793 -cart: App\Entity\Order\Order {#13330 …} -cartItem: App\Entity\Order\OrderItem {#113781 #id: null #order: null #quantity: 1 #unitPrice: 0 #originalUnitPrice: 0 #total: 0 #immutable: false #units: Doctrine\Common\Collections\ArrayCollection {#113806 …} #unitsTotal: 0 #adjustments: Doctrine\Common\Collections\ArrayCollection {#113805 …} #adjustmentsTotal: 0 #version: 1 #variant: App\Entity\Product\ProductVariant {#8099 #id: 4126 #code: "IEEE00003617PDF" #product: App\Entity\Product\Product {#7310 #id: 10090 #code: "IEEE00003617" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …} #initialized: true -snapshot: [ …4] -owner: App\Entity\Product\Product {#7310} -association: [ …21] -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …} -backRefFieldName: null -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#223708 …} -isDirty: false } #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751038807 {#7274 : 2025-06-27 17:40:07.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607004 {#7322 : 2025-08-08 00:50:04.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 35369 #name: "IEEE 1800:2005" #slug: "ieee-1800-2005-ieee00003617-241742" #description: """ New IEEE Standard - Superseded.<br />\n This standard represents a merger of two previous standards: IEEE 1364-2005 Verilog hardware description language (HDL) and IEEE 1800-2005 SystemVerilog unified hardware design, specification and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard enables users to have all information regarding syntax and semantics in a single document.<br />\n \t\t\t\t<br />\n SystemVerilog is a Unified Hardware Design, Specification and Verification language that is based on the work done by Accellera, a consortium of Electronic Design Automation (EDA), semiconductor, and system companies. The proposed project will create an IEEE standard that is leveraged from Accellera SystemVerilog 3.1a. The new standard will include design specification methods, embedded assertions language, test bench language including coverage and assertions API, and a direct programming interface. The proposed SystemVerilog standard enables a productivity boost in design and validation, and covers design, simulation, validation, and formal assertion based verification flows.<br />\n The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a well-defined and official IEEE Unified Hardware Design, Specification and Verification standard language. The language is designed to co-exist and enhance those hardware description languages presently used by designers while providing the capabilities lacking in those languages. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for SystemVerilog: Unified Hardware Design, Specification and Verification Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1132614000 {#7318 : 2005-11-22 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1800" -bookCollection: "" -pageCount: 648 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } #optionValues: Doctrine\ORM\PersistentCollection {#8315 …} #position: 0 #createdAt: DateTime @1751041185 {#7966 : 2025-06-27 18:19:45.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1755611983 {#8116 : 2025-08-19 15:59:43.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#8259 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductVariantTranslation {#93313 #locale: "en_US" #translatable: App\Entity\Product\ProductVariant {#8099} #id: 4144 #name: null -shortDescription: null -description: null -notes: null -shippingInformation: "Instant download" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #version: 9 #onHold: 0 #onHand: 0 #tracked: false #weight: 0.0 #width: null #height: null #depth: null #taxCategory: Proxies\__CG__\App\Entity\Taxation\TaxCategory {#8131 …} #shippingCategory: null #channelPricings: Doctrine\ORM\PersistentCollection {#8293 …} #shippingRequired: true #images: Doctrine\ORM\PersistentCollection {#8290 …} -apiLastModifiedAt: DateTime @1753740000 {#8098 : 2025-07-29 00:00:00.0 Europe/Paris (+02:00) } -publishedAt: null -isbn: "978-0-7381-4811-3" -ean: "9780738148113" -numberOfUsers: 1 -physicalProduct: false -downloadableImmediately: true -downloadable: true -drmViewerUrl: "https://online-viewer.normadoc.com/bcu4KN" -sellable: true -documents: Doctrine\ORM\PersistentCollection {#8127 …} -drmTokens: Doctrine\ORM\PersistentCollection {#8119 …} -enabledForSubscribers: true -currentAreaContext: null } #productName: null #variantName: null } } |
same as passed value |
| product | App\Entity\Product\Product {#7310 #id: 10090 #code: "IEEE00003617" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …} #initialized: true -snapshot: [ …4] -owner: App\Entity\Product\Product {#7310} -association: [ …21] -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …} -backRefFieldName: null -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#223708 …} -isDirty: false } #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751038807 {#7274 : 2025-06-27 17:40:07.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607004 {#7322 : 2025-08-08 00:50:04.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 35369 #name: "IEEE 1800:2005" #slug: "ieee-1800-2005-ieee00003617-241742" #description: """ New IEEE Standard - Superseded.<br />\n This standard represents a merger of two previous standards: IEEE 1364-2005 Verilog hardware description language (HDL) and IEEE 1800-2005 SystemVerilog unified hardware design, specification and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard enables users to have all information regarding syntax and semantics in a single document.<br />\n \t\t\t\t<br />\n SystemVerilog is a Unified Hardware Design, Specification and Verification language that is based on the work done by Accellera, a consortium of Electronic Design Automation (EDA), semiconductor, and system companies. The proposed project will create an IEEE standard that is leveraged from Accellera SystemVerilog 3.1a. The new standard will include design specification methods, embedded assertions language, test bench language including coverage and assertions API, and a direct programming interface. The proposed SystemVerilog standard enables a productivity boost in design and validation, and covers design, simulation, validation, and formal assertion based verification flows.<br />\n The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a well-defined and official IEEE Unified Hardware Design, Specification and Verification standard language. The language is designed to co-exist and enhance those hardware description languages presently used by designers while providing the capabilities lacking in those languages. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for SystemVerilog: Unified Hardware Design, Specification and Verification Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1132614000 {#7318 : 2005-11-22 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1800" -bookCollection: "" -pageCount: 648 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } |
same as passed value |
Resolved Options
| Option | Value |
|---|---|
| action | "" |
| allow_extra_fields | false |
| allow_file_upload | false |
| attr | [] |
| attr_translation_parameters | [] |
| auto_initialize | true |
| block_name | null |
| block_prefix | null |
| by_reference | true |
| compound | true |
| constraints | [] |
| csrf_field_name | "_token" |
| csrf_message | "The CSRF token is invalid. Please try to resubmit the form." |
| csrf_protection | true |
| csrf_token_id | null |
| csrf_token_manager | Symfony\Component\Security\Csrf\CsrfTokenManager {#113813 -generator: Symfony\Component\Security\Csrf\TokenGenerator\UriSafeTokenGenerator {#113814 …} -storage: Symfony\Component\Security\Csrf\TokenStorage\SessionTokenStorage {#113815 …} -namespace: Closure() {#113817 …} } |
| data | Sylius\Bundle\OrderBundle\Controller\AddToCartCommand {#113793 -cart: App\Entity\Order\Order {#13330 …} -cartItem: App\Entity\Order\OrderItem {#113781 #id: null #order: null #quantity: 1 #unitPrice: 0 #originalUnitPrice: 0 #total: 0 #immutable: false #units: Doctrine\Common\Collections\ArrayCollection {#113806 …} #unitsTotal: 0 #adjustments: Doctrine\Common\Collections\ArrayCollection {#113805 …} #adjustmentsTotal: 0 #version: 1 #variant: App\Entity\Product\ProductVariant {#8099 #id: 4126 #code: "IEEE00003617PDF" #product: App\Entity\Product\Product {#7310 #id: 10090 #code: "IEEE00003617" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …} #initialized: true -snapshot: [ …4] -owner: App\Entity\Product\Product {#7310} -association: [ …21] -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …} -backRefFieldName: null -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#223708 …} -isDirty: false } #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751038807 {#7274 : 2025-06-27 17:40:07.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607004 {#7322 : 2025-08-08 00:50:04.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 35369 #name: "IEEE 1800:2005" #slug: "ieee-1800-2005-ieee00003617-241742" #description: """ New IEEE Standard - Superseded.<br />\n This standard represents a merger of two previous standards: IEEE 1364-2005 Verilog hardware description language (HDL) and IEEE 1800-2005 SystemVerilog unified hardware design, specification and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard enables users to have all information regarding syntax and semantics in a single document.<br />\n \t\t\t\t<br />\n SystemVerilog is a Unified Hardware Design, Specification and Verification language that is based on the work done by Accellera, a consortium of Electronic Design Automation (EDA), semiconductor, and system companies. The proposed project will create an IEEE standard that is leveraged from Accellera SystemVerilog 3.1a. The new standard will include design specification methods, embedded assertions language, test bench language including coverage and assertions API, and a direct programming interface. The proposed SystemVerilog standard enables a productivity boost in design and validation, and covers design, simulation, validation, and formal assertion based verification flows.<br />\n The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a well-defined and official IEEE Unified Hardware Design, Specification and Verification standard language. The language is designed to co-exist and enhance those hardware description languages presently used by designers while providing the capabilities lacking in those languages. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for SystemVerilog: Unified Hardware Design, Specification and Verification Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1132614000 {#7318 : 2005-11-22 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1800" -bookCollection: "" -pageCount: 648 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } #optionValues: Doctrine\ORM\PersistentCollection {#8315 …} #position: 0 #createdAt: DateTime @1751041185 {#7966 : 2025-06-27 18:19:45.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1755611983 {#8116 : 2025-08-19 15:59:43.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#8259 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductVariantTranslation {#93313 #locale: "en_US" #translatable: App\Entity\Product\ProductVariant {#8099} #id: 4144 #name: null -shortDescription: null -description: null -notes: null -shippingInformation: "Instant download" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #version: 9 #onHold: 0 #onHand: 0 #tracked: false #weight: 0.0 #width: null #height: null #depth: null #taxCategory: Proxies\__CG__\App\Entity\Taxation\TaxCategory {#8131 …} #shippingCategory: null #channelPricings: Doctrine\ORM\PersistentCollection {#8293 …} #shippingRequired: true #images: Doctrine\ORM\PersistentCollection {#8290 …} -apiLastModifiedAt: DateTime @1753740000 {#8098 : 2025-07-29 00:00:00.0 Europe/Paris (+02:00) } -publishedAt: null -isbn: "978-0-7381-4811-3" -ean: "9780738148113" -numberOfUsers: 1 -physicalProduct: false -downloadableImmediately: true -downloadable: true -drmViewerUrl: "https://online-viewer.normadoc.com/bcu4KN" -sellable: true -documents: Doctrine\ORM\PersistentCollection {#8127 …} -drmTokens: Doctrine\ORM\PersistentCollection {#8119 …} -enabledForSubscribers: true -currentAreaContext: null } #productName: null #variantName: null } } |
| data_class | "Sylius\Bundle\OrderBundle\Controller\AddToCartCommand" |
| disabled | false |
| empty_data | Closure(FormInterface $form) {#113840 : "Symfony\Component\Form\Extension\Core\Type\FormType" : { : "Sylius\Bundle\OrderBundle\Controller\AddToCartCommand" } } |
| error_bubbling | true |
| error_mapping | [] |
| extra_fields_message | "This form should not contain extra fields." |
| form_attr | false |
| getter | null |
| help | null |
| help_attr | [] |
| help_html | false |
| help_translation_parameters | [] |
| inherit_data | false |
| invalid_message | "This value is not valid." |
| invalid_message_parameters | [] |
| is_empty_callback | null |
| label | null |
| label_attr | [] |
| label_format | null |
| label_html | false |
| label_translation_parameters | [] |
| mapped | true |
| method | "POST" |
| post_max_size_message | "The uploaded file was too large. Please try to upload a smaller file." |
| priority | 0 |
| product | App\Entity\Product\Product {#7310 #id: 10090 #code: "IEEE00003617" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …} #initialized: true -snapshot: [ …4] -owner: App\Entity\Product\Product {#7310} -association: [ …21] -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …} -backRefFieldName: null -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#223708 …} -isDirty: false } #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751038807 {#7274 : 2025-06-27 17:40:07.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607004 {#7322 : 2025-08-08 00:50:04.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 35369 #name: "IEEE 1800:2005" #slug: "ieee-1800-2005-ieee00003617-241742" #description: """ New IEEE Standard - Superseded.<br />\n This standard represents a merger of two previous standards: IEEE 1364-2005 Verilog hardware description language (HDL) and IEEE 1800-2005 SystemVerilog unified hardware design, specification and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard enables users to have all information regarding syntax and semantics in a single document.<br />\n \t\t\t\t<br />\n SystemVerilog is a Unified Hardware Design, Specification and Verification language that is based on the work done by Accellera, a consortium of Electronic Design Automation (EDA), semiconductor, and system companies. The proposed project will create an IEEE standard that is leveraged from Accellera SystemVerilog 3.1a. The new standard will include design specification methods, embedded assertions language, test bench language including coverage and assertions API, and a direct programming interface. The proposed SystemVerilog standard enables a productivity boost in design and validation, and covers design, simulation, validation, and formal assertion based verification flows.<br />\n The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a well-defined and official IEEE Unified Hardware Design, Specification and Verification standard language. The language is designed to co-exist and enhance those hardware description languages presently used by designers while providing the capabilities lacking in those languages. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for SystemVerilog: Unified Hardware Design, Specification and Verification Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1132614000 {#7318 : 2005-11-22 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1800" -bookCollection: "" -pageCount: 648 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } |
| property_path | null |
| required | true |
| row_attr | [] |
| setter | null |
| translation_domain | null |
| trim | true |
| upload_max_size_message | Closure() {#113842 : "Symfony\Component\Form\Extension\Validator\Type\UploadValidatorExtension" : { : Symfony\Component\Translation\DataCollectorTranslator {#2251 …} : Closure() {#113841 …} : "validators" } } |
| validation_groups | [
"sylius"
] |
View Vars
| Variable | Value |
|---|---|
| action | "" |
| attr | [] |
| attr_translation_parameters | [] |
| block_prefixes | [ "form" "sylius_add_to_cart" "_sylius_add_to_cart" ] |
| cache_key | "_sylius_add_to_cart_sylius_add_to_cart" |
| compound | true |
| data | Sylius\Bundle\OrderBundle\Controller\AddToCartCommand {#113793 -cart: App\Entity\Order\Order {#13330 …} -cartItem: App\Entity\Order\OrderItem {#113781 #id: null #order: null #quantity: 1 #unitPrice: 0 #originalUnitPrice: 0 #total: 0 #immutable: false #units: Doctrine\Common\Collections\ArrayCollection {#113806 …} #unitsTotal: 0 #adjustments: Doctrine\Common\Collections\ArrayCollection {#113805 …} #adjustmentsTotal: 0 #version: 1 #variant: App\Entity\Product\ProductVariant {#8099 #id: 4126 #code: "IEEE00003617PDF" #product: App\Entity\Product\Product {#7310 #id: 10090 #code: "IEEE00003617" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …} #initialized: true -snapshot: [ …4] -owner: App\Entity\Product\Product {#7310} -association: [ …21] -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …} -backRefFieldName: null -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#223708 …} -isDirty: false } #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751038807 {#7274 : 2025-06-27 17:40:07.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607004 {#7322 : 2025-08-08 00:50:04.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 35369 #name: "IEEE 1800:2005" #slug: "ieee-1800-2005-ieee00003617-241742" #description: """ New IEEE Standard - Superseded.<br />\n This standard represents a merger of two previous standards: IEEE 1364-2005 Verilog hardware description language (HDL) and IEEE 1800-2005 SystemVerilog unified hardware design, specification and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard enables users to have all information regarding syntax and semantics in a single document.<br />\n \t\t\t\t<br />\n SystemVerilog is a Unified Hardware Design, Specification and Verification language that is based on the work done by Accellera, a consortium of Electronic Design Automation (EDA), semiconductor, and system companies. The proposed project will create an IEEE standard that is leveraged from Accellera SystemVerilog 3.1a. The new standard will include design specification methods, embedded assertions language, test bench language including coverage and assertions API, and a direct programming interface. The proposed SystemVerilog standard enables a productivity boost in design and validation, and covers design, simulation, validation, and formal assertion based verification flows.<br />\n The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a well-defined and official IEEE Unified Hardware Design, Specification and Verification standard language. The language is designed to co-exist and enhance those hardware description languages presently used by designers while providing the capabilities lacking in those languages. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for SystemVerilog: Unified Hardware Design, Specification and Verification Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1132614000 {#7318 : 2005-11-22 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1800" -bookCollection: "" -pageCount: 648 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } #optionValues: Doctrine\ORM\PersistentCollection {#8315 …} #position: 0 #createdAt: DateTime @1751041185 {#7966 : 2025-06-27 18:19:45.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1755611983 {#8116 : 2025-08-19 15:59:43.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#8259 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductVariantTranslation {#93313 #locale: "en_US" #translatable: App\Entity\Product\ProductVariant {#8099} #id: 4144 #name: null -shortDescription: null -description: null -notes: null -shippingInformation: "Instant download" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #version: 9 #onHold: 0 #onHand: 0 #tracked: false #weight: 0.0 #width: null #height: null #depth: null #taxCategory: Proxies\__CG__\App\Entity\Taxation\TaxCategory {#8131 …} #shippingCategory: null #channelPricings: Doctrine\ORM\PersistentCollection {#8293 …} #shippingRequired: true #images: Doctrine\ORM\PersistentCollection {#8290 …} -apiLastModifiedAt: DateTime @1753740000 {#8098 : 2025-07-29 00:00:00.0 Europe/Paris (+02:00) } -publishedAt: null -isbn: "978-0-7381-4811-3" -ean: "9780738148113" -numberOfUsers: 1 -physicalProduct: false -downloadableImmediately: true -downloadable: true -drmViewerUrl: "https://online-viewer.normadoc.com/bcu4KN" -sellable: true -documents: Doctrine\ORM\PersistentCollection {#8127 …} -drmTokens: Doctrine\ORM\PersistentCollection {#8119 …} -enabledForSubscribers: true -currentAreaContext: null } #productName: null #variantName: null } } |
| disabled | false |
| errors | Symfony\Component\Form\FormErrorIterator {#113863 -form: Symfony\Component\Form\Form {#113872 …} -errors: [] } |
| form | Symfony\Component\Form\FormView {#113843 …5} |
| full_name | "sylius_add_to_cart" |
| help | null |
| help_attr | [] |
| help_html | false |
| help_translation_parameters | [] |
| id | "sylius_add_to_cart" |
| label | null |
| label_attr | [] |
| label_format | null |
| label_html | false |
| label_translation_parameters | [] |
| method | "POST" |
| multipart | false |
| name | "sylius_add_to_cart" |
| priority | 0 |
| required | true |
| row_attr | [] |
| submitted | false |
| translation_domain | null |
| unique_block_prefix | "_sylius_add_to_cart" |
| valid | true |
| value | Sylius\Bundle\OrderBundle\Controller\AddToCartCommand {#113793 -cart: App\Entity\Order\Order {#13330 …} -cartItem: App\Entity\Order\OrderItem {#113781 #id: null #order: null #quantity: 1 #unitPrice: 0 #originalUnitPrice: 0 #total: 0 #immutable: false #units: Doctrine\Common\Collections\ArrayCollection {#113806 …} #unitsTotal: 0 #adjustments: Doctrine\Common\Collections\ArrayCollection {#113805 …} #adjustmentsTotal: 0 #version: 1 #variant: App\Entity\Product\ProductVariant {#8099 #id: 4126 #code: "IEEE00003617PDF" #product: App\Entity\Product\Product {#7310 #id: 10090 #code: "IEEE00003617" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …} #initialized: true -snapshot: [ …4] -owner: App\Entity\Product\Product {#7310} -association: [ …21] -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …} -backRefFieldName: null -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#223708 …} -isDirty: false } #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751038807 {#7274 : 2025-06-27 17:40:07.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607004 {#7322 : 2025-08-08 00:50:04.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 35369 #name: "IEEE 1800:2005" #slug: "ieee-1800-2005-ieee00003617-241742" #description: """ New IEEE Standard - Superseded.<br />\n This standard represents a merger of two previous standards: IEEE 1364-2005 Verilog hardware description language (HDL) and IEEE 1800-2005 SystemVerilog unified hardware design, specification and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard enables users to have all information regarding syntax and semantics in a single document.<br />\n \t\t\t\t<br />\n SystemVerilog is a Unified Hardware Design, Specification and Verification language that is based on the work done by Accellera, a consortium of Electronic Design Automation (EDA), semiconductor, and system companies. The proposed project will create an IEEE standard that is leveraged from Accellera SystemVerilog 3.1a. The new standard will include design specification methods, embedded assertions language, test bench language including coverage and assertions API, and a direct programming interface. The proposed SystemVerilog standard enables a productivity boost in design and validation, and covers design, simulation, validation, and formal assertion based verification flows.<br />\n The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a well-defined and official IEEE Unified Hardware Design, Specification and Verification standard language. The language is designed to co-exist and enhance those hardware description languages presently used by designers while providing the capabilities lacking in those languages. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for SystemVerilog: Unified Hardware Design, Specification and Verification Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1132614000 {#7318 : 2005-11-22 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1800" -bookCollection: "" -pageCount: 648 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } #optionValues: Doctrine\ORM\PersistentCollection {#8315 …} #position: 0 #createdAt: DateTime @1751041185 {#7966 : 2025-06-27 18:19:45.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1755611983 {#8116 : 2025-08-19 15:59:43.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#8259 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductVariantTranslation {#93313 #locale: "en_US" #translatable: App\Entity\Product\ProductVariant {#8099} #id: 4144 #name: null -shortDescription: null -description: null -notes: null -shippingInformation: "Instant download" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #version: 9 #onHold: 0 #onHand: 0 #tracked: false #weight: 0.0 #width: null #height: null #depth: null #taxCategory: Proxies\__CG__\App\Entity\Taxation\TaxCategory {#8131 …} #shippingCategory: null #channelPricings: Doctrine\ORM\PersistentCollection {#8293 …} #shippingRequired: true #images: Doctrine\ORM\PersistentCollection {#8290 …} -apiLastModifiedAt: DateTime @1753740000 {#8098 : 2025-07-29 00:00:00.0 Europe/Paris (+02:00) } -publishedAt: null -isbn: "978-0-7381-4811-3" -ean: "9780738148113" -numberOfUsers: 1 -physicalProduct: false -downloadableImmediately: true -downloadable: true -drmViewerUrl: "https://online-viewer.normadoc.com/bcu4KN" -sellable: true -documents: Doctrine\ORM\PersistentCollection {#8127 …} -drmTokens: Doctrine\ORM\PersistentCollection {#8119 …} -enabledForSubscribers: true -currentAreaContext: null } #productName: null #variantName: null } } |