GET https://dev.normadoc.fr/products/ieee-1800-2012-ieee00004934-242395

Response
200 OK
IP
216.73.216.19
Profiled on
Token
45121c

Components

4 Twig Components
16 Render Count
14 ms Render Time
110.0 MiB Memory Usage

Components

Name Metadata Render Count Render Time
ProductState 
"App\Twig\Components\ProductState"
components/ProductState.html.twig 		7 1.24ms
ProductMostRecent 
"App\Twig\Components\ProductMostRecent"
components/ProductMostRecent.html.twig 		7 4.35ms
ProductType 
"App\Twig\Components\ProductType"
components/ProductType.html.twig 		1 0.19ms
ProductCard 
"App\Twig\Components\ProductCard"
components/ProductCard.html.twig 		1 8.99ms

Render calls

ProductState App\Twig\Components\ProductState 68.0 MiB 0.30 ms
Input props 
[
  "product" => App\Entity\Product\Product {#7310
    #id: 10743
    #code: "IEEE00004934"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751039255 {#7274
      date: 2025-06-27 17:47:35.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#7322
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 37981
        #name: "IEEE 1800:2012"
        #slug: "ieee-1800-2012-ieee00004934-242395"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified<br />\n
          hardware design, specification, and verification language, is provided. This standard includes<br />\n
          support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level<br />\n
          abstraction levels, and for writing test benches using coverage, assertions, object-oriented<br />\n
          programming, and constrained random verification. The standard also provides application<br />\n
          programming interfaces (APIs) to foreign programming languages. (Thanks to our sponsor, the PDF of this standard is provided to the public no charge. Visit GETIEEE program located at https://ieeexplore.ieee.org/browse/standards/get-program/page for details.)<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800™<br />\n
          SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2009.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1361401200 {#7318
      date: 2013-02-21 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  "showFullLabel" => "true"
]
Attributes 
[
  "showFullLabel" => "true"
]
Component 
App\Twig\Components\ProductState {#93007
  +product: App\Entity\Product\Product {#7310
    #id: 10743
    #code: "IEEE00004934"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751039255 {#7274
      date: 2025-06-27 17:47:35.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#7322
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 37981
        #name: "IEEE 1800:2012"
        #slug: "ieee-1800-2012-ieee00004934-242395"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified<br />\n
          hardware design, specification, and verification language, is provided. This standard includes<br />\n
          support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level<br />\n
          abstraction levels, and for writing test benches using coverage, assertions, object-oriented<br />\n
          programming, and constrained random verification. The standard also provides application<br />\n
          programming interfaces (APIs) to foreign programming languages. (Thanks to our sponsor, the PDF of this standard is provided to the public no charge. Visit GETIEEE program located at https://ieeexplore.ieee.org/browse/standards/get-program/page for details.)<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800™<br />\n
          SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2009.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1361401200 {#7318
      date: 2013-02-21 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductType App\Twig\Components\ProductType 68.0 MiB 0.19 ms
Input props 
[
  "product" => App\Entity\Product\Product {#7310
    #id: 10743
    #code: "IEEE00004934"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751039255 {#7274
      date: 2025-06-27 17:47:35.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#7322
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 37981
        #name: "IEEE 1800:2012"
        #slug: "ieee-1800-2012-ieee00004934-242395"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified<br />\n
          hardware design, specification, and verification language, is provided. This standard includes<br />\n
          support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level<br />\n
          abstraction levels, and for writing test benches using coverage, assertions, object-oriented<br />\n
          programming, and constrained random verification. The standard also provides application<br />\n
          programming interfaces (APIs) to foreign programming languages. (Thanks to our sponsor, the PDF of this standard is provided to the public no charge. Visit GETIEEE program located at https://ieeexplore.ieee.org/browse/standards/get-program/page for details.)<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800™<br />\n
          SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2009.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1361401200 {#7318
      date: 2013-02-21 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
]
Attributes 
[]
Component 
App\Twig\Components\ProductType {#93187
  +product: App\Entity\Product\Product {#7310
    #id: 10743
    #code: "IEEE00004934"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751039255 {#7274
      date: 2025-06-27 17:47:35.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#7322
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 37981
        #name: "IEEE 1800:2012"
        #slug: "ieee-1800-2012-ieee00004934-242395"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified<br />\n
          hardware design, specification, and verification language, is provided. This standard includes<br />\n
          support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level<br />\n
          abstraction levels, and for writing test benches using coverage, assertions, object-oriented<br />\n
          programming, and constrained random verification. The standard also provides application<br />\n
          programming interfaces (APIs) to foreign programming languages. (Thanks to our sponsor, the PDF of this standard is provided to the public no charge. Visit GETIEEE program located at https://ieeexplore.ieee.org/browse/standards/get-program/page for details.)<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800™<br />\n
          SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2009.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1361401200 {#7318
      date: 2013-02-21 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +label: "Standard"
  -typeAttributeCode: "type"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductMostRecent App\Twig\Components\ProductMostRecent 68.0 MiB 0.63 ms
Input props 
[
  "product" => App\Entity\Product\Product {#7310
    #id: 10743
    #code: "IEEE00004934"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751039255 {#7274
      date: 2025-06-27 17:47:35.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#7322
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 37981
        #name: "IEEE 1800:2012"
        #slug: "ieee-1800-2012-ieee00004934-242395"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified<br />\n
          hardware design, specification, and verification language, is provided. This standard includes<br />\n
          support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level<br />\n
          abstraction levels, and for writing test benches using coverage, assertions, object-oriented<br />\n
          programming, and constrained random verification. The standard also provides application<br />\n
          programming interfaces (APIs) to foreign programming languages. (Thanks to our sponsor, the PDF of this standard is provided to the public no charge. Visit GETIEEE program located at https://ieeexplore.ieee.org/browse/standards/get-program/page for details.)<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800™<br />\n
          SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2009.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1361401200 {#7318
      date: 2013-02-21 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
]
Attributes 
[]
Component 
App\Twig\Components\ProductMostRecent {#93262
  +product: App\Entity\Product\Product {#7310
    #id: 10743
    #code: "IEEE00004934"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751039255 {#7274
      date: 2025-06-27 17:47:35.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#7322
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 37981
        #name: "IEEE 1800:2012"
        #slug: "ieee-1800-2012-ieee00004934-242395"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified<br />\n
          hardware design, specification, and verification language, is provided. This standard includes<br />\n
          support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level<br />\n
          abstraction levels, and for writing test benches using coverage, assertions, object-oriented<br />\n
          programming, and constrained random verification. The standard also provides application<br />\n
          programming interfaces (APIs) to foreign programming languages. (Thanks to our sponsor, the PDF of this standard is provided to the public no charge. Visit GETIEEE program located at https://ieeexplore.ieee.org/browse/standards/get-program/page for details.)<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800™<br />\n
          SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2009.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1361401200 {#7318
      date: 2013-02-21 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +label: "Historical"
  +icon: "historical"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductState App\Twig\Components\ProductState 80.0 MiB 0.17 ms
Input props 
[
  "product" => App\Entity\Product\Product {#106837
    #id: 10248
    #code: "IEEE00003989"
    #attributes: Doctrine\ORM\PersistentCollection {#106820 …}
    #variants: Doctrine\ORM\PersistentCollection {#106817 …}
    #options: Doctrine\ORM\PersistentCollection {#106813 …}
    #associations: Doctrine\ORM\PersistentCollection {#106815 …}
    #createdAt: DateTime @1751038925 {#106845
      date: 2025-06-27 17:42:05.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#106818
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106831 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#106863
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106837}
        #id: 36001
        #name: "IEEE 1800:2009"
        #slug: "ieee-1800-2009-ieee00003989-241900"
        #description: """
          Revision Standard - Superseded.<br />\n
          This standard represents a merger of two previous standards: IEEE Std 1364(TM)-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document.<br />\n
          (IEEE Std1800-2009 was a revision of both IEEE Std1364-2005 and IEEE Std1800-2005.)<br />\n
          \t\t\t\t<br />\n
          This SystemVerilog standard (IEEE Std 1800) is a Unified Hardware Design, Specification, and Verification language. IEEE Std 1364TM-2005 Verilog is a design language. Both standards were approved by the IEEE-SASB in November 2005. This standard creates new revisions of the IEEE 1364 Verilog and IEEE 1800 SystemVerilog standards, which include errata fixes and resolutions, enhancements, enhanced assertion language, merger of Verilog Language Reference Manual (LRM) and SystemVerilog 1800 LRM into a single LRM, integration with Verilog-AMS, and ensures interoperability with other languages such as SystemC and VHDL.<br />\n
          The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a solid and well-defined IEEE Unified Hardware Design, Specification and Verification standard language, while resolving errata and developing enhancements to the current IEEE 1800 SystemVerilog standard. The language is designed to co-exist, be interoperable, possibly merge, and enhance those hardware description languages presently used by designers.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106828 …}
    #channels: Doctrine\ORM\PersistentCollection {#106822 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106826 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106824 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106838 …}
    -apiLastModifiedAt: DateTime @1754517600 {#106805
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1613602800 {#106844
      date: 2021-02-18 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1260486000 {#106843
      date: 2009-12-11 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1285
    -documents: Doctrine\ORM\PersistentCollection {#106835 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106833 …}
  }
  "showFullLabel" => "true"
]
Attributes 
[
  "showFullLabel" => "true"
]
Component 
App\Twig\Components\ProductState {#106889
  +product: App\Entity\Product\Product {#106837
    #id: 10248
    #code: "IEEE00003989"
    #attributes: Doctrine\ORM\PersistentCollection {#106820 …}
    #variants: Doctrine\ORM\PersistentCollection {#106817 …}
    #options: Doctrine\ORM\PersistentCollection {#106813 …}
    #associations: Doctrine\ORM\PersistentCollection {#106815 …}
    #createdAt: DateTime @1751038925 {#106845
      date: 2025-06-27 17:42:05.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#106818
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106831 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#106863
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106837}
        #id: 36001
        #name: "IEEE 1800:2009"
        #slug: "ieee-1800-2009-ieee00003989-241900"
        #description: """
          Revision Standard - Superseded.<br />\n
          This standard represents a merger of two previous standards: IEEE Std 1364(TM)-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document.<br />\n
          (IEEE Std1800-2009 was a revision of both IEEE Std1364-2005 and IEEE Std1800-2005.)<br />\n
          \t\t\t\t<br />\n
          This SystemVerilog standard (IEEE Std 1800) is a Unified Hardware Design, Specification, and Verification language. IEEE Std 1364TM-2005 Verilog is a design language. Both standards were approved by the IEEE-SASB in November 2005. This standard creates new revisions of the IEEE 1364 Verilog and IEEE 1800 SystemVerilog standards, which include errata fixes and resolutions, enhancements, enhanced assertion language, merger of Verilog Language Reference Manual (LRM) and SystemVerilog 1800 LRM into a single LRM, integration with Verilog-AMS, and ensures interoperability with other languages such as SystemC and VHDL.<br />\n
          The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a solid and well-defined IEEE Unified Hardware Design, Specification and Verification standard language, while resolving errata and developing enhancements to the current IEEE 1800 SystemVerilog standard. The language is designed to co-exist, be interoperable, possibly merge, and enhance those hardware description languages presently used by designers.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106828 …}
    #channels: Doctrine\ORM\PersistentCollection {#106822 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106826 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106824 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106838 …}
    -apiLastModifiedAt: DateTime @1754517600 {#106805
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1613602800 {#106844
      date: 2021-02-18 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1260486000 {#106843
      date: 2009-12-11 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1285
    -documents: Doctrine\ORM\PersistentCollection {#106835 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106833 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductMostRecent App\Twig\Components\ProductMostRecent 80.0 MiB 0.68 ms
Input props 
[
  "product" => App\Entity\Product\Product {#106837
    #id: 10248
    #code: "IEEE00003989"
    #attributes: Doctrine\ORM\PersistentCollection {#106820 …}
    #variants: Doctrine\ORM\PersistentCollection {#106817 …}
    #options: Doctrine\ORM\PersistentCollection {#106813 …}
    #associations: Doctrine\ORM\PersistentCollection {#106815 …}
    #createdAt: DateTime @1751038925 {#106845
      date: 2025-06-27 17:42:05.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#106818
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106831 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#106863
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106837}
        #id: 36001
        #name: "IEEE 1800:2009"
        #slug: "ieee-1800-2009-ieee00003989-241900"
        #description: """
          Revision Standard - Superseded.<br />\n
          This standard represents a merger of two previous standards: IEEE Std 1364(TM)-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document.<br />\n
          (IEEE Std1800-2009 was a revision of both IEEE Std1364-2005 and IEEE Std1800-2005.)<br />\n
          \t\t\t\t<br />\n
          This SystemVerilog standard (IEEE Std 1800) is a Unified Hardware Design, Specification, and Verification language. IEEE Std 1364TM-2005 Verilog is a design language. Both standards were approved by the IEEE-SASB in November 2005. This standard creates new revisions of the IEEE 1364 Verilog and IEEE 1800 SystemVerilog standards, which include errata fixes and resolutions, enhancements, enhanced assertion language, merger of Verilog Language Reference Manual (LRM) and SystemVerilog 1800 LRM into a single LRM, integration with Verilog-AMS, and ensures interoperability with other languages such as SystemC and VHDL.<br />\n
          The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a solid and well-defined IEEE Unified Hardware Design, Specification and Verification standard language, while resolving errata and developing enhancements to the current IEEE 1800 SystemVerilog standard. The language is designed to co-exist, be interoperable, possibly merge, and enhance those hardware description languages presently used by designers.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106828 …}
    #channels: Doctrine\ORM\PersistentCollection {#106822 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106826 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106824 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106838 …}
    -apiLastModifiedAt: DateTime @1754517600 {#106805
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1613602800 {#106844
      date: 2021-02-18 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1260486000 {#106843
      date: 2009-12-11 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1285
    -documents: Doctrine\ORM\PersistentCollection {#106835 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106833 …}
  }
]
Attributes 
[]
Component 
App\Twig\Components\ProductMostRecent {#106956
  +product: App\Entity\Product\Product {#106837
    #id: 10248
    #code: "IEEE00003989"
    #attributes: Doctrine\ORM\PersistentCollection {#106820 …}
    #variants: Doctrine\ORM\PersistentCollection {#106817 …}
    #options: Doctrine\ORM\PersistentCollection {#106813 …}
    #associations: Doctrine\ORM\PersistentCollection {#106815 …}
    #createdAt: DateTime @1751038925 {#106845
      date: 2025-06-27 17:42:05.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#106818
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106831 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#106863
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106837}
        #id: 36001
        #name: "IEEE 1800:2009"
        #slug: "ieee-1800-2009-ieee00003989-241900"
        #description: """
          Revision Standard - Superseded.<br />\n
          This standard represents a merger of two previous standards: IEEE Std 1364(TM)-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document.<br />\n
          (IEEE Std1800-2009 was a revision of both IEEE Std1364-2005 and IEEE Std1800-2005.)<br />\n
          \t\t\t\t<br />\n
          This SystemVerilog standard (IEEE Std 1800) is a Unified Hardware Design, Specification, and Verification language. IEEE Std 1364TM-2005 Verilog is a design language. Both standards were approved by the IEEE-SASB in November 2005. This standard creates new revisions of the IEEE 1364 Verilog and IEEE 1800 SystemVerilog standards, which include errata fixes and resolutions, enhancements, enhanced assertion language, merger of Verilog Language Reference Manual (LRM) and SystemVerilog 1800 LRM into a single LRM, integration with Verilog-AMS, and ensures interoperability with other languages such as SystemC and VHDL.<br />\n
          The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a solid and well-defined IEEE Unified Hardware Design, Specification and Verification standard language, while resolving errata and developing enhancements to the current IEEE 1800 SystemVerilog standard. The language is designed to co-exist, be interoperable, possibly merge, and enhance those hardware description languages presently used by designers.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106828 …}
    #channels: Doctrine\ORM\PersistentCollection {#106822 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106826 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106824 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106838 …}
    -apiLastModifiedAt: DateTime @1754517600 {#106805
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1613602800 {#106844
      date: 2021-02-18 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1260486000 {#106843
      date: 2009-12-11 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1285
    -documents: Doctrine\ORM\PersistentCollection {#106835 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106833 …}
  }
  +label: "Historical"
  +icon: "historical"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductState App\Twig\Components\ProductState 88.0 MiB 0.17 ms
Input props 
[
  "product" => App\Entity\Product\Product {#93699
    #id: 11861
    #code: "IEEE00006700"
    #attributes: Doctrine\ORM\PersistentCollection {#93681 …}
    #variants: Doctrine\ORM\PersistentCollection {#93678 …}
    #options: Doctrine\ORM\PersistentCollection {#93674 …}
    #associations: Doctrine\ORM\PersistentCollection {#93676 …}
    #createdAt: DateTime @1751040040 {#93707
      date: 2025-06-27 18:00:40.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754608621 {#93686
      date: 2025-08-08 01:17:01.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#93692 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#93727
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#93699}
        #id: 42453
        #name: "IEEE 1800:2017"
        #slug: "ieee-1800-2017-ieee00006700-243513"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800(TM) SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#93690 …}
    #channels: Doctrine\ORM\PersistentCollection {#93683 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#93688 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#93685 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#93700 …}
    -apiLastModifiedAt: DateTime @1754517600 {#93670
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1709074800 {#93706
      date: 2024-02-28 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1519254000 {#93705
      date: 2018-02-22 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#93696 …}
    -favorites: Doctrine\ORM\PersistentCollection {#93694 …}
  }
  "showFullLabel" => "true"
]
Attributes 
[
  "showFullLabel" => "true"
]
Component 
App\Twig\Components\ProductState {#113452
  +product: App\Entity\Product\Product {#93699
    #id: 11861
    #code: "IEEE00006700"
    #attributes: Doctrine\ORM\PersistentCollection {#93681 …}
    #variants: Doctrine\ORM\PersistentCollection {#93678 …}
    #options: Doctrine\ORM\PersistentCollection {#93674 …}
    #associations: Doctrine\ORM\PersistentCollection {#93676 …}
    #createdAt: DateTime @1751040040 {#93707
      date: 2025-06-27 18:00:40.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754608621 {#93686
      date: 2025-08-08 01:17:01.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#93692 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#93727
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#93699}
        #id: 42453
        #name: "IEEE 1800:2017"
        #slug: "ieee-1800-2017-ieee00006700-243513"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800(TM) SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#93690 …}
    #channels: Doctrine\ORM\PersistentCollection {#93683 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#93688 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#93685 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#93700 …}
    -apiLastModifiedAt: DateTime @1754517600 {#93670
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1709074800 {#93706
      date: 2024-02-28 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1519254000 {#93705
      date: 2018-02-22 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#93696 …}
    -favorites: Doctrine\ORM\PersistentCollection {#93694 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductMostRecent App\Twig\Components\ProductMostRecent 88.0 MiB 0.67 ms
Input props 
[
  "product" => App\Entity\Product\Product {#93699
    #id: 11861
    #code: "IEEE00006700"
    #attributes: Doctrine\ORM\PersistentCollection {#93681 …}
    #variants: Doctrine\ORM\PersistentCollection {#93678 …}
    #options: Doctrine\ORM\PersistentCollection {#93674 …}
    #associations: Doctrine\ORM\PersistentCollection {#93676 …}
    #createdAt: DateTime @1751040040 {#93707
      date: 2025-06-27 18:00:40.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754608621 {#93686
      date: 2025-08-08 01:17:01.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#93692 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#93727
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#93699}
        #id: 42453
        #name: "IEEE 1800:2017"
        #slug: "ieee-1800-2017-ieee00006700-243513"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800(TM) SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#93690 …}
    #channels: Doctrine\ORM\PersistentCollection {#93683 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#93688 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#93685 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#93700 …}
    -apiLastModifiedAt: DateTime @1754517600 {#93670
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1709074800 {#93706
      date: 2024-02-28 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1519254000 {#93705
      date: 2018-02-22 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#93696 …}
    -favorites: Doctrine\ORM\PersistentCollection {#93694 …}
  }
]
Attributes 
[]
Component 
App\Twig\Components\ProductMostRecent {#113518
  +product: App\Entity\Product\Product {#93699
    #id: 11861
    #code: "IEEE00006700"
    #attributes: Doctrine\ORM\PersistentCollection {#93681 …}
    #variants: Doctrine\ORM\PersistentCollection {#93678 …}
    #options: Doctrine\ORM\PersistentCollection {#93674 …}
    #associations: Doctrine\ORM\PersistentCollection {#93676 …}
    #createdAt: DateTime @1751040040 {#93707
      date: 2025-06-27 18:00:40.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754608621 {#93686
      date: 2025-08-08 01:17:01.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#93692 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#93727
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#93699}
        #id: 42453
        #name: "IEEE 1800:2017"
        #slug: "ieee-1800-2017-ieee00006700-243513"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800(TM) SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#93690 …}
    #channels: Doctrine\ORM\PersistentCollection {#93683 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#93688 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#93685 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#93700 …}
    -apiLastModifiedAt: DateTime @1754517600 {#93670
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1709074800 {#93706
      date: 2024-02-28 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1519254000 {#93705
      date: 2018-02-22 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#93696 …}
    -favorites: Doctrine\ORM\PersistentCollection {#93694 …}
  }
  +label: "Historical"
  +icon: "historical"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductState App\Twig\Components\ProductState 88.0 MiB 0.14 ms
Input props 
[
  "product" => App\Entity\Product\Product {#7310
    #id: 10743
    #code: "IEEE00004934"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751039255 {#7274
      date: 2025-06-27 17:47:35.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#7322
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 37981
        #name: "IEEE 1800:2012"
        #slug: "ieee-1800-2012-ieee00004934-242395"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified<br />\n
          hardware design, specification, and verification language, is provided. This standard includes<br />\n
          support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level<br />\n
          abstraction levels, and for writing test benches using coverage, assertions, object-oriented<br />\n
          programming, and constrained random verification. The standard also provides application<br />\n
          programming interfaces (APIs) to foreign programming languages. (Thanks to our sponsor, the PDF of this standard is provided to the public no charge. Visit GETIEEE program located at https://ieeexplore.ieee.org/browse/standards/get-program/page for details.)<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800™<br />\n
          SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2009.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1361401200 {#7318
      date: 2013-02-21 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  "showFullLabel" => "true"
]
Attributes 
[
  "showFullLabel" => "true"
]
Component 
App\Twig\Components\ProductState {#113583
  +product: App\Entity\Product\Product {#7310
    #id: 10743
    #code: "IEEE00004934"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751039255 {#7274
      date: 2025-06-27 17:47:35.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#7322
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 37981
        #name: "IEEE 1800:2012"
        #slug: "ieee-1800-2012-ieee00004934-242395"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified<br />\n
          hardware design, specification, and verification language, is provided. This standard includes<br />\n
          support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level<br />\n
          abstraction levels, and for writing test benches using coverage, assertions, object-oriented<br />\n
          programming, and constrained random verification. The standard also provides application<br />\n
          programming interfaces (APIs) to foreign programming languages. (Thanks to our sponsor, the PDF of this standard is provided to the public no charge. Visit GETIEEE program located at https://ieeexplore.ieee.org/browse/standards/get-program/page for details.)<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800™<br />\n
          SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2009.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1361401200 {#7318
      date: 2013-02-21 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductMostRecent App\Twig\Components\ProductMostRecent 88.0 MiB 0.58 ms
Input props 
[
  "product" => App\Entity\Product\Product {#7310
    #id: 10743
    #code: "IEEE00004934"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751039255 {#7274
      date: 2025-06-27 17:47:35.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#7322
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 37981
        #name: "IEEE 1800:2012"
        #slug: "ieee-1800-2012-ieee00004934-242395"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified<br />\n
          hardware design, specification, and verification language, is provided. This standard includes<br />\n
          support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level<br />\n
          abstraction levels, and for writing test benches using coverage, assertions, object-oriented<br />\n
          programming, and constrained random verification. The standard also provides application<br />\n
          programming interfaces (APIs) to foreign programming languages. (Thanks to our sponsor, the PDF of this standard is provided to the public no charge. Visit GETIEEE program located at https://ieeexplore.ieee.org/browse/standards/get-program/page for details.)<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800™<br />\n
          SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2009.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1361401200 {#7318
      date: 2013-02-21 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
]
Attributes 
[]
Component 
App\Twig\Components\ProductMostRecent {#113610
  +product: App\Entity\Product\Product {#7310
    #id: 10743
    #code: "IEEE00004934"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751039255 {#7274
      date: 2025-06-27 17:47:35.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#7322
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 37981
        #name: "IEEE 1800:2012"
        #slug: "ieee-1800-2012-ieee00004934-242395"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified<br />\n
          hardware design, specification, and verification language, is provided. This standard includes<br />\n
          support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level<br />\n
          abstraction levels, and for writing test benches using coverage, assertions, object-oriented<br />\n
          programming, and constrained random verification. The standard also provides application<br />\n
          programming interfaces (APIs) to foreign programming languages. (Thanks to our sponsor, the PDF of this standard is provided to the public no charge. Visit GETIEEE program located at https://ieeexplore.ieee.org/browse/standards/get-program/page for details.)<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800™<br />\n
          SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2009.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1361401200 {#7318
      date: 2013-02-21 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +label: "Historical"
  +icon: "historical"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductState App\Twig\Components\ProductState 88.0 MiB 0.14 ms
Input props 
[
  "product" => App\Entity\Product\Product {#106837
    #id: 10248
    #code: "IEEE00003989"
    #attributes: Doctrine\ORM\PersistentCollection {#106820 …}
    #variants: Doctrine\ORM\PersistentCollection {#106817 …}
    #options: Doctrine\ORM\PersistentCollection {#106813 …}
    #associations: Doctrine\ORM\PersistentCollection {#106815 …}
    #createdAt: DateTime @1751038925 {#106845
      date: 2025-06-27 17:42:05.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#106818
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106831 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#106863
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106837}
        #id: 36001
        #name: "IEEE 1800:2009"
        #slug: "ieee-1800-2009-ieee00003989-241900"
        #description: """
          Revision Standard - Superseded.<br />\n
          This standard represents a merger of two previous standards: IEEE Std 1364(TM)-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document.<br />\n
          (IEEE Std1800-2009 was a revision of both IEEE Std1364-2005 and IEEE Std1800-2005.)<br />\n
          \t\t\t\t<br />\n
          This SystemVerilog standard (IEEE Std 1800) is a Unified Hardware Design, Specification, and Verification language. IEEE Std 1364TM-2005 Verilog is a design language. Both standards were approved by the IEEE-SASB in November 2005. This standard creates new revisions of the IEEE 1364 Verilog and IEEE 1800 SystemVerilog standards, which include errata fixes and resolutions, enhancements, enhanced assertion language, merger of Verilog Language Reference Manual (LRM) and SystemVerilog 1800 LRM into a single LRM, integration with Verilog-AMS, and ensures interoperability with other languages such as SystemC and VHDL.<br />\n
          The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a solid and well-defined IEEE Unified Hardware Design, Specification and Verification standard language, while resolving errata and developing enhancements to the current IEEE 1800 SystemVerilog standard. The language is designed to co-exist, be interoperable, possibly merge, and enhance those hardware description languages presently used by designers.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106828 …}
    #channels: Doctrine\ORM\PersistentCollection {#106822 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106826 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106824 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106838 …}
    -apiLastModifiedAt: DateTime @1754517600 {#106805
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1613602800 {#106844
      date: 2021-02-18 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1260486000 {#106843
      date: 2009-12-11 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1285
    -documents: Doctrine\ORM\PersistentCollection {#106835 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106833 …}
  }
  "showFullLabel" => "true"
]
Attributes 
[
  "showFullLabel" => "true"
]
Component 
App\Twig\Components\ProductState {#113674
  +product: App\Entity\Product\Product {#106837
    #id: 10248
    #code: "IEEE00003989"
    #attributes: Doctrine\ORM\PersistentCollection {#106820 …}
    #variants: Doctrine\ORM\PersistentCollection {#106817 …}
    #options: Doctrine\ORM\PersistentCollection {#106813 …}
    #associations: Doctrine\ORM\PersistentCollection {#106815 …}
    #createdAt: DateTime @1751038925 {#106845
      date: 2025-06-27 17:42:05.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#106818
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106831 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#106863
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106837}
        #id: 36001
        #name: "IEEE 1800:2009"
        #slug: "ieee-1800-2009-ieee00003989-241900"
        #description: """
          Revision Standard - Superseded.<br />\n
          This standard represents a merger of two previous standards: IEEE Std 1364(TM)-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document.<br />\n
          (IEEE Std1800-2009 was a revision of both IEEE Std1364-2005 and IEEE Std1800-2005.)<br />\n
          \t\t\t\t<br />\n
          This SystemVerilog standard (IEEE Std 1800) is a Unified Hardware Design, Specification, and Verification language. IEEE Std 1364TM-2005 Verilog is a design language. Both standards were approved by the IEEE-SASB in November 2005. This standard creates new revisions of the IEEE 1364 Verilog and IEEE 1800 SystemVerilog standards, which include errata fixes and resolutions, enhancements, enhanced assertion language, merger of Verilog Language Reference Manual (LRM) and SystemVerilog 1800 LRM into a single LRM, integration with Verilog-AMS, and ensures interoperability with other languages such as SystemC and VHDL.<br />\n
          The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a solid and well-defined IEEE Unified Hardware Design, Specification and Verification standard language, while resolving errata and developing enhancements to the current IEEE 1800 SystemVerilog standard. The language is designed to co-exist, be interoperable, possibly merge, and enhance those hardware description languages presently used by designers.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106828 …}
    #channels: Doctrine\ORM\PersistentCollection {#106822 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106826 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106824 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106838 …}
    -apiLastModifiedAt: DateTime @1754517600 {#106805
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1613602800 {#106844
      date: 2021-02-18 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1260486000 {#106843
      date: 2009-12-11 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1285
    -documents: Doctrine\ORM\PersistentCollection {#106835 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106833 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductMostRecent App\Twig\Components\ProductMostRecent 88.0 MiB 0.57 ms
Input props 
[
  "product" => App\Entity\Product\Product {#106837
    #id: 10248
    #code: "IEEE00003989"
    #attributes: Doctrine\ORM\PersistentCollection {#106820 …}
    #variants: Doctrine\ORM\PersistentCollection {#106817 …}
    #options: Doctrine\ORM\PersistentCollection {#106813 …}
    #associations: Doctrine\ORM\PersistentCollection {#106815 …}
    #createdAt: DateTime @1751038925 {#106845
      date: 2025-06-27 17:42:05.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#106818
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106831 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#106863
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106837}
        #id: 36001
        #name: "IEEE 1800:2009"
        #slug: "ieee-1800-2009-ieee00003989-241900"
        #description: """
          Revision Standard - Superseded.<br />\n
          This standard represents a merger of two previous standards: IEEE Std 1364(TM)-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document.<br />\n
          (IEEE Std1800-2009 was a revision of both IEEE Std1364-2005 and IEEE Std1800-2005.)<br />\n
          \t\t\t\t<br />\n
          This SystemVerilog standard (IEEE Std 1800) is a Unified Hardware Design, Specification, and Verification language. IEEE Std 1364TM-2005 Verilog is a design language. Both standards were approved by the IEEE-SASB in November 2005. This standard creates new revisions of the IEEE 1364 Verilog and IEEE 1800 SystemVerilog standards, which include errata fixes and resolutions, enhancements, enhanced assertion language, merger of Verilog Language Reference Manual (LRM) and SystemVerilog 1800 LRM into a single LRM, integration with Verilog-AMS, and ensures interoperability with other languages such as SystemC and VHDL.<br />\n
          The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a solid and well-defined IEEE Unified Hardware Design, Specification and Verification standard language, while resolving errata and developing enhancements to the current IEEE 1800 SystemVerilog standard. The language is designed to co-exist, be interoperable, possibly merge, and enhance those hardware description languages presently used by designers.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106828 …}
    #channels: Doctrine\ORM\PersistentCollection {#106822 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106826 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106824 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106838 …}
    -apiLastModifiedAt: DateTime @1754517600 {#106805
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1613602800 {#106844
      date: 2021-02-18 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1260486000 {#106843
      date: 2009-12-11 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1285
    -documents: Doctrine\ORM\PersistentCollection {#106835 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106833 …}
  }
]
Attributes 
[]
Component 
App\Twig\Components\ProductMostRecent {#113701
  +product: App\Entity\Product\Product {#106837
    #id: 10248
    #code: "IEEE00003989"
    #attributes: Doctrine\ORM\PersistentCollection {#106820 …}
    #variants: Doctrine\ORM\PersistentCollection {#106817 …}
    #options: Doctrine\ORM\PersistentCollection {#106813 …}
    #associations: Doctrine\ORM\PersistentCollection {#106815 …}
    #createdAt: DateTime @1751038925 {#106845
      date: 2025-06-27 17:42:05.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#106818
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106831 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#106863
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106837}
        #id: 36001
        #name: "IEEE 1800:2009"
        #slug: "ieee-1800-2009-ieee00003989-241900"
        #description: """
          Revision Standard - Superseded.<br />\n
          This standard represents a merger of two previous standards: IEEE Std 1364(TM)-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document.<br />\n
          (IEEE Std1800-2009 was a revision of both IEEE Std1364-2005 and IEEE Std1800-2005.)<br />\n
          \t\t\t\t<br />\n
          This SystemVerilog standard (IEEE Std 1800) is a Unified Hardware Design, Specification, and Verification language. IEEE Std 1364TM-2005 Verilog is a design language. Both standards were approved by the IEEE-SASB in November 2005. This standard creates new revisions of the IEEE 1364 Verilog and IEEE 1800 SystemVerilog standards, which include errata fixes and resolutions, enhancements, enhanced assertion language, merger of Verilog Language Reference Manual (LRM) and SystemVerilog 1800 LRM into a single LRM, integration with Verilog-AMS, and ensures interoperability with other languages such as SystemC and VHDL.<br />\n
          The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a solid and well-defined IEEE Unified Hardware Design, Specification and Verification standard language, while resolving errata and developing enhancements to the current IEEE 1800 SystemVerilog standard. The language is designed to co-exist, be interoperable, possibly merge, and enhance those hardware description languages presently used by designers.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106828 …}
    #channels: Doctrine\ORM\PersistentCollection {#106822 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106826 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106824 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106838 …}
    -apiLastModifiedAt: DateTime @1754517600 {#106805
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1613602800 {#106844
      date: 2021-02-18 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1260486000 {#106843
      date: 2009-12-11 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1285
    -documents: Doctrine\ORM\PersistentCollection {#106835 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106833 …}
  }
  +label: "Historical"
  +icon: "historical"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductState App\Twig\Components\ProductState 88.0 MiB 0.14 ms
Input props 
[
  "product" => App\Entity\Product\Product {#113389
    #id: 10090
    #code: "IEEE00003617"
    #attributes: Doctrine\ORM\PersistentCollection {#113405 …}
    #variants: Doctrine\ORM\PersistentCollection {#113407 …}
    #options: Doctrine\ORM\PersistentCollection {#113411 …}
    #associations: Doctrine\ORM\PersistentCollection {#113409 …}
    #createdAt: DateTime @1751038807 {#113380
      date: 2025-06-27 17:40:07.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#113378
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#113395 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#113767
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#113389}
        #id: 35369
        #name: "IEEE 1800:2005"
        #slug: "ieee-1800-2005-ieee00003617-241742"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          This standard represents a merger of two previous standards: IEEE 1364-2005 Verilog hardware description language (HDL) and IEEE 1800-2005 SystemVerilog unified hardware design, specification and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard enables users to have all information regarding syntax and semantics in a single document.<br />\n
          \t\t\t\t<br />\n
          SystemVerilog is a Unified Hardware Design, Specification and Verification language that is based on the work done by Accellera, a consortium of Electronic Design Automation (EDA), semiconductor, and system companies. The proposed project will create an IEEE standard that is leveraged from Accellera SystemVerilog 3.1a. The new standard will include design specification methods, embedded assertions language, test bench language including coverage and assertions API, and a direct programming interface. The proposed SystemVerilog standard enables a productivity boost in design and validation, and covers design, simulation, validation, and formal assertion based verification flows.<br />\n
          The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a well-defined and official IEEE Unified Hardware Design, Specification and Verification standard language. The language is designed to co-exist and enhance those hardware description languages presently used by designers while providing the capabilities lacking in those languages.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog: Unified Hardware Design, Specification and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#113397 …}
    #channels: Doctrine\ORM\PersistentCollection {#113403 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#113399 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#113401 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#113388 …}
    -apiLastModifiedAt: DateTime @1754517600 {#113381
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#113374
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1132614000 {#113371
      date: 2005-11-22 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 648
    -documents: Doctrine\ORM\PersistentCollection {#113391 …}
    -favorites: Doctrine\ORM\PersistentCollection {#113393 …}
  }
  "showFullLabel" => "true"
]
Attributes 
[
  "showFullLabel" => "true"
]
Component 
App\Twig\Components\ProductState {#113782
  +product: App\Entity\Product\Product {#113389
    #id: 10090
    #code: "IEEE00003617"
    #attributes: Doctrine\ORM\PersistentCollection {#113405 …}
    #variants: Doctrine\ORM\PersistentCollection {#113407 …}
    #options: Doctrine\ORM\PersistentCollection {#113411 …}
    #associations: Doctrine\ORM\PersistentCollection {#113409 …}
    #createdAt: DateTime @1751038807 {#113380
      date: 2025-06-27 17:40:07.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#113378
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#113395 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#113767
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#113389}
        #id: 35369
        #name: "IEEE 1800:2005"
        #slug: "ieee-1800-2005-ieee00003617-241742"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          This standard represents a merger of two previous standards: IEEE 1364-2005 Verilog hardware description language (HDL) and IEEE 1800-2005 SystemVerilog unified hardware design, specification and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard enables users to have all information regarding syntax and semantics in a single document.<br />\n
          \t\t\t\t<br />\n
          SystemVerilog is a Unified Hardware Design, Specification and Verification language that is based on the work done by Accellera, a consortium of Electronic Design Automation (EDA), semiconductor, and system companies. The proposed project will create an IEEE standard that is leveraged from Accellera SystemVerilog 3.1a. The new standard will include design specification methods, embedded assertions language, test bench language including coverage and assertions API, and a direct programming interface. The proposed SystemVerilog standard enables a productivity boost in design and validation, and covers design, simulation, validation, and formal assertion based verification flows.<br />\n
          The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a well-defined and official IEEE Unified Hardware Design, Specification and Verification standard language. The language is designed to co-exist and enhance those hardware description languages presently used by designers while providing the capabilities lacking in those languages.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog: Unified Hardware Design, Specification and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#113397 …}
    #channels: Doctrine\ORM\PersistentCollection {#113403 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#113399 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#113401 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#113388 …}
    -apiLastModifiedAt: DateTime @1754517600 {#113381
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#113374
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1132614000 {#113371
      date: 2005-11-22 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 648
    -documents: Doctrine\ORM\PersistentCollection {#113391 …}
    -favorites: Doctrine\ORM\PersistentCollection {#113393 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductMostRecent App\Twig\Components\ProductMostRecent 88.0 MiB 0.59 ms
Input props 
[
  "product" => App\Entity\Product\Product {#113389
    #id: 10090
    #code: "IEEE00003617"
    #attributes: Doctrine\ORM\PersistentCollection {#113405 …}
    #variants: Doctrine\ORM\PersistentCollection {#113407 …}
    #options: Doctrine\ORM\PersistentCollection {#113411 …}
    #associations: Doctrine\ORM\PersistentCollection {#113409 …}
    #createdAt: DateTime @1751038807 {#113380
      date: 2025-06-27 17:40:07.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#113378
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#113395 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#113767
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#113389}
        #id: 35369
        #name: "IEEE 1800:2005"
        #slug: "ieee-1800-2005-ieee00003617-241742"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          This standard represents a merger of two previous standards: IEEE 1364-2005 Verilog hardware description language (HDL) and IEEE 1800-2005 SystemVerilog unified hardware design, specification and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard enables users to have all information regarding syntax and semantics in a single document.<br />\n
          \t\t\t\t<br />\n
          SystemVerilog is a Unified Hardware Design, Specification and Verification language that is based on the work done by Accellera, a consortium of Electronic Design Automation (EDA), semiconductor, and system companies. The proposed project will create an IEEE standard that is leveraged from Accellera SystemVerilog 3.1a. The new standard will include design specification methods, embedded assertions language, test bench language including coverage and assertions API, and a direct programming interface. The proposed SystemVerilog standard enables a productivity boost in design and validation, and covers design, simulation, validation, and formal assertion based verification flows.<br />\n
          The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a well-defined and official IEEE Unified Hardware Design, Specification and Verification standard language. The language is designed to co-exist and enhance those hardware description languages presently used by designers while providing the capabilities lacking in those languages.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog: Unified Hardware Design, Specification and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#113397 …}
    #channels: Doctrine\ORM\PersistentCollection {#113403 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#113399 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#113401 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#113388 …}
    -apiLastModifiedAt: DateTime @1754517600 {#113381
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#113374
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1132614000 {#113371
      date: 2005-11-22 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 648
    -documents: Doctrine\ORM\PersistentCollection {#113391 …}
    -favorites: Doctrine\ORM\PersistentCollection {#113393 …}
  }
]
Attributes 
[]
Component 
App\Twig\Components\ProductMostRecent {#113834
  +product: App\Entity\Product\Product {#113389
    #id: 10090
    #code: "IEEE00003617"
    #attributes: Doctrine\ORM\PersistentCollection {#113405 …}
    #variants: Doctrine\ORM\PersistentCollection {#113407 …}
    #options: Doctrine\ORM\PersistentCollection {#113411 …}
    #associations: Doctrine\ORM\PersistentCollection {#113409 …}
    #createdAt: DateTime @1751038807 {#113380
      date: 2025-06-27 17:40:07.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#113378
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#113395 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#113767
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#113389}
        #id: 35369
        #name: "IEEE 1800:2005"
        #slug: "ieee-1800-2005-ieee00003617-241742"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          This standard represents a merger of two previous standards: IEEE 1364-2005 Verilog hardware description language (HDL) and IEEE 1800-2005 SystemVerilog unified hardware design, specification and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard enables users to have all information regarding syntax and semantics in a single document.<br />\n
          \t\t\t\t<br />\n
          SystemVerilog is a Unified Hardware Design, Specification and Verification language that is based on the work done by Accellera, a consortium of Electronic Design Automation (EDA), semiconductor, and system companies. The proposed project will create an IEEE standard that is leveraged from Accellera SystemVerilog 3.1a. The new standard will include design specification methods, embedded assertions language, test bench language including coverage and assertions API, and a direct programming interface. The proposed SystemVerilog standard enables a productivity boost in design and validation, and covers design, simulation, validation, and formal assertion based verification flows.<br />\n
          The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a well-defined and official IEEE Unified Hardware Design, Specification and Verification standard language. The language is designed to co-exist and enhance those hardware description languages presently used by designers while providing the capabilities lacking in those languages.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog: Unified Hardware Design, Specification and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#113397 …}
    #channels: Doctrine\ORM\PersistentCollection {#113403 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#113399 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#113401 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#113388 …}
    -apiLastModifiedAt: DateTime @1754517600 {#113381
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#113374
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1132614000 {#113371
      date: 2005-11-22 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 648
    -documents: Doctrine\ORM\PersistentCollection {#113391 …}
    -favorites: Doctrine\ORM\PersistentCollection {#113393 …}
  }
  +label: "Historical"
  +icon: "historical"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductCard App\Twig\Components\ProductCard 110.0 MiB 8.99 ms
Input props 
[
  "product" => App\Entity\Product\Product {#135324
    #id: 10346
    #code: "IEEE00004211"
    #attributes: Doctrine\ORM\PersistentCollection {#135348 …}
    #variants: Doctrine\ORM\PersistentCollection {#135346 …}
    #options: Doctrine\ORM\PersistentCollection {#135341 …}
    #associations: Doctrine\ORM\PersistentCollection {#135344 …}
    #createdAt: DateTime @1751039004 {#135337
      date: 2025-06-27 17:43:24.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969918 {#135330
      date: 2025-07-31 15:51:58.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#135359 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#135455
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#135324}
        #id: 36393
        #name: "IEEE 754:2008"
        #slug: "ieee-754-2008-ieee00004211-241998"
        #description: """
          Revision Standard - Superseded.<br />\n
          This standard specifies formats and methods for floating-point arithmetic in computer systems: standard and extended functions with single, double, extended, and extendable precision, and recommends formats for data interchange. Exception conditions are defined and standard handling of these conditions is specified.<br />\n
          \t\t\t\t<br />\n
          This standard specifies formats and methods for floating-point arithmetic in computer systems — standard and extended functions with single, double, extended, and extendable precision — and recommends formats for data interchange. Exception conditions are defined and standard handling of these conditions is specified.<br />\n
          This standard provides a method for computation with floating-point numbers that will yield the same result whether the processing is done in hardware, software, or a combination of the two. The results of the computation will be identical, independent of implementation, given the same input data. Errors, and error conditions, in the mathematical processing will be reported in a consistent manner regardless of implementation.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Floating-Point Arithmetic"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#135357 …}
    #channels: Doctrine\ORM\PersistentCollection {#135350 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#135354 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#135352 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#135364 …}
    -apiLastModifiedAt: DateTime @1743289200 {#135323
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1613602800 {#135372
      date: 2021-02-18 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1219960800 {#135343
      date: 2008-08-29 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "754"
    -bookCollection: ""
    -pageCount: 70
    -documents: Doctrine\ORM\PersistentCollection {#135363 …}
    -favorites: Doctrine\ORM\PersistentCollection {#135361 …}
  }
  "layout" => "vertical"
  "showPrice" => true
  "showStatusBadges" => true
  "additionalClasses" => "product__teaser--with-grey-border"
  "hasStretchedLink" => true
  "hoverType" => "shadow"
  "linkLabel" => "See more"
]
Attributes 
[]
Component 
App\Twig\Components\ProductCard {#135416
  +product: App\Entity\Product\Product {#135324
    #id: 10346
    #code: "IEEE00004211"
    #attributes: Doctrine\ORM\PersistentCollection {#135348 …}
    #variants: Doctrine\ORM\PersistentCollection {#135346 …}
    #options: Doctrine\ORM\PersistentCollection {#135341 …}
    #associations: Doctrine\ORM\PersistentCollection {#135344 …}
    #createdAt: DateTime @1751039004 {#135337
      date: 2025-06-27 17:43:24.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969918 {#135330
      date: 2025-07-31 15:51:58.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#135359 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#135455
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#135324}
        #id: 36393
        #name: "IEEE 754:2008"
        #slug: "ieee-754-2008-ieee00004211-241998"
        #description: """
          Revision Standard - Superseded.<br />\n
          This standard specifies formats and methods for floating-point arithmetic in computer systems: standard and extended functions with single, double, extended, and extendable precision, and recommends formats for data interchange. Exception conditions are defined and standard handling of these conditions is specified.<br />\n
          \t\t\t\t<br />\n
          This standard specifies formats and methods for floating-point arithmetic in computer systems — standard and extended functions with single, double, extended, and extendable precision — and recommends formats for data interchange. Exception conditions are defined and standard handling of these conditions is specified.<br />\n
          This standard provides a method for computation with floating-point numbers that will yield the same result whether the processing is done in hardware, software, or a combination of the two. The results of the computation will be identical, independent of implementation, given the same input data. Errors, and error conditions, in the mathematical processing will be reported in a consistent manner regardless of implementation.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Floating-Point Arithmetic"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#135357 …}
    #channels: Doctrine\ORM\PersistentCollection {#135350 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#135354 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#135352 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#135364 …}
    -apiLastModifiedAt: DateTime @1743289200 {#135323
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1613602800 {#135372
      date: 2021-02-18 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1219960800 {#135343
      date: 2008-08-29 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "754"
    -bookCollection: ""
    -pageCount: 70
    -documents: Doctrine\ORM\PersistentCollection {#135363 …}
    -favorites: Doctrine\ORM\PersistentCollection {#135361 …}
  }
  +layout: "vertical"
  +showPrice: true
  +showStatusBadges: true
  +additionalClasses: "product__teaser--with-grey-border"
  +linkLabel: "See more"
  +imageFilter: "product_thumbnail_teaser"
  +hasStretchedLink: true
  +backgroundColor: "white"
  +hoverType: "shadow"
}
ProductState App\Twig\Components\ProductState 110.0 MiB 0.16 ms
Input props 
[
  "product" => App\Entity\Product\Product {#135324
    #id: 10346
    #code: "IEEE00004211"
    #attributes: Doctrine\ORM\PersistentCollection {#135348 …}
    #variants: Doctrine\ORM\PersistentCollection {#135346 …}
    #options: Doctrine\ORM\PersistentCollection {#135341 …}
    #associations: Doctrine\ORM\PersistentCollection {#135344 …}
    #createdAt: DateTime @1751039004 {#135337
      date: 2025-06-27 17:43:24.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969918 {#135330
      date: 2025-07-31 15:51:58.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#135359 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#135455
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#135324}
        #id: 36393
        #name: "IEEE 754:2008"
        #slug: "ieee-754-2008-ieee00004211-241998"
        #description: """
          Revision Standard - Superseded.<br />\n
          This standard specifies formats and methods for floating-point arithmetic in computer systems: standard and extended functions with single, double, extended, and extendable precision, and recommends formats for data interchange. Exception conditions are defined and standard handling of these conditions is specified.<br />\n
          \t\t\t\t<br />\n
          This standard specifies formats and methods for floating-point arithmetic in computer systems — standard and extended functions with single, double, extended, and extendable precision — and recommends formats for data interchange. Exception conditions are defined and standard handling of these conditions is specified.<br />\n
          This standard provides a method for computation with floating-point numbers that will yield the same result whether the processing is done in hardware, software, or a combination of the two. The results of the computation will be identical, independent of implementation, given the same input data. Errors, and error conditions, in the mathematical processing will be reported in a consistent manner regardless of implementation.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Floating-Point Arithmetic"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#135357 …}
    #channels: Doctrine\ORM\PersistentCollection {#135350 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#135354 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#135352 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#135364 …}
    -apiLastModifiedAt: DateTime @1743289200 {#135323
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1613602800 {#135372
      date: 2021-02-18 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1219960800 {#135343
      date: 2008-08-29 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "754"
    -bookCollection: ""
    -pageCount: 70
    -documents: Doctrine\ORM\PersistentCollection {#135363 …}
    -favorites: Doctrine\ORM\PersistentCollection {#135361 …}
  }
]
Attributes 
[
  "showFullLabel" => false
]
Component 
App\Twig\Components\ProductState {#135457
  +product: App\Entity\Product\Product {#135324
    #id: 10346
    #code: "IEEE00004211"
    #attributes: Doctrine\ORM\PersistentCollection {#135348 …}
    #variants: Doctrine\ORM\PersistentCollection {#135346 …}
    #options: Doctrine\ORM\PersistentCollection {#135341 …}
    #associations: Doctrine\ORM\PersistentCollection {#135344 …}
    #createdAt: DateTime @1751039004 {#135337
      date: 2025-06-27 17:43:24.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969918 {#135330
      date: 2025-07-31 15:51:58.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#135359 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#135455
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#135324}
        #id: 36393
        #name: "IEEE 754:2008"
        #slug: "ieee-754-2008-ieee00004211-241998"
        #description: """
          Revision Standard - Superseded.<br />\n
          This standard specifies formats and methods for floating-point arithmetic in computer systems: standard and extended functions with single, double, extended, and extendable precision, and recommends formats for data interchange. Exception conditions are defined and standard handling of these conditions is specified.<br />\n
          \t\t\t\t<br />\n
          This standard specifies formats and methods for floating-point arithmetic in computer systems — standard and extended functions with single, double, extended, and extendable precision — and recommends formats for data interchange. Exception conditions are defined and standard handling of these conditions is specified.<br />\n
          This standard provides a method for computation with floating-point numbers that will yield the same result whether the processing is done in hardware, software, or a combination of the two. The results of the computation will be identical, independent of implementation, given the same input data. Errors, and error conditions, in the mathematical processing will be reported in a consistent manner regardless of implementation.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Floating-Point Arithmetic"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#135357 …}
    #channels: Doctrine\ORM\PersistentCollection {#135350 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#135354 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#135352 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#135364 …}
    -apiLastModifiedAt: DateTime @1743289200 {#135323
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1613602800 {#135372
      date: 2021-02-18 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1219960800 {#135343
      date: 2008-08-29 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "754"
    -bookCollection: ""
    -pageCount: 70
    -documents: Doctrine\ORM\PersistentCollection {#135363 …}
    -favorites: Doctrine\ORM\PersistentCollection {#135361 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductMostRecent App\Twig\Components\ProductMostRecent 110.0 MiB 0.62 ms
Input props 
[
  "product" => App\Entity\Product\Product {#135324
    #id: 10346
    #code: "IEEE00004211"
    #attributes: Doctrine\ORM\PersistentCollection {#135348 …}
    #variants: Doctrine\ORM\PersistentCollection {#135346 …}
    #options: Doctrine\ORM\PersistentCollection {#135341 …}
    #associations: Doctrine\ORM\PersistentCollection {#135344 …}
    #createdAt: DateTime @1751039004 {#135337
      date: 2025-06-27 17:43:24.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969918 {#135330
      date: 2025-07-31 15:51:58.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#135359 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#135455
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#135324}
        #id: 36393
        #name: "IEEE 754:2008"
        #slug: "ieee-754-2008-ieee00004211-241998"
        #description: """
          Revision Standard - Superseded.<br />\n
          This standard specifies formats and methods for floating-point arithmetic in computer systems: standard and extended functions with single, double, extended, and extendable precision, and recommends formats for data interchange. Exception conditions are defined and standard handling of these conditions is specified.<br />\n
          \t\t\t\t<br />\n
          This standard specifies formats and methods for floating-point arithmetic in computer systems — standard and extended functions with single, double, extended, and extendable precision — and recommends formats for data interchange. Exception conditions are defined and standard handling of these conditions is specified.<br />\n
          This standard provides a method for computation with floating-point numbers that will yield the same result whether the processing is done in hardware, software, or a combination of the two. The results of the computation will be identical, independent of implementation, given the same input data. Errors, and error conditions, in the mathematical processing will be reported in a consistent manner regardless of implementation.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Floating-Point Arithmetic"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#135357 …}
    #channels: Doctrine\ORM\PersistentCollection {#135350 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#135354 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#135352 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#135364 …}
    -apiLastModifiedAt: DateTime @1743289200 {#135323
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1613602800 {#135372
      date: 2021-02-18 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1219960800 {#135343
      date: 2008-08-29 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "754"
    -bookCollection: ""
    -pageCount: 70
    -documents: Doctrine\ORM\PersistentCollection {#135363 …}
    -favorites: Doctrine\ORM\PersistentCollection {#135361 …}
  }
]
Attributes 
[]
Component 
App\Twig\Components\ProductMostRecent {#135534
  +product: App\Entity\Product\Product {#135324
    #id: 10346
    #code: "IEEE00004211"
    #attributes: Doctrine\ORM\PersistentCollection {#135348 …}
    #variants: Doctrine\ORM\PersistentCollection {#135346 …}
    #options: Doctrine\ORM\PersistentCollection {#135341 …}
    #associations: Doctrine\ORM\PersistentCollection {#135344 …}
    #createdAt: DateTime @1751039004 {#135337
      date: 2025-06-27 17:43:24.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969918 {#135330
      date: 2025-07-31 15:51:58.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#135359 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#135455
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#135324}
        #id: 36393
        #name: "IEEE 754:2008"
        #slug: "ieee-754-2008-ieee00004211-241998"
        #description: """
          Revision Standard - Superseded.<br />\n
          This standard specifies formats and methods for floating-point arithmetic in computer systems: standard and extended functions with single, double, extended, and extendable precision, and recommends formats for data interchange. Exception conditions are defined and standard handling of these conditions is specified.<br />\n
          \t\t\t\t<br />\n
          This standard specifies formats and methods for floating-point arithmetic in computer systems — standard and extended functions with single, double, extended, and extendable precision — and recommends formats for data interchange. Exception conditions are defined and standard handling of these conditions is specified.<br />\n
          This standard provides a method for computation with floating-point numbers that will yield the same result whether the processing is done in hardware, software, or a combination of the two. The results of the computation will be identical, independent of implementation, given the same input data. Errors, and error conditions, in the mathematical processing will be reported in a consistent manner regardless of implementation.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Floating-Point Arithmetic"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#135357 …}
    #channels: Doctrine\ORM\PersistentCollection {#135350 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#135354 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#135352 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#135364 …}
    -apiLastModifiedAt: DateTime @1743289200 {#135323
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1613602800 {#135372
      date: 2021-02-18 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1219960800 {#135343
      date: 2008-08-29 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "754"
    -bookCollection: ""
    -pageCount: 70
    -documents: Doctrine\ORM\PersistentCollection {#135363 …}
    -favorites: Doctrine\ORM\PersistentCollection {#135361 …}
  }
  +label: "Historical"
  +icon: "historical"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}