Components
4
Twig Components
8
Render Count
9
ms
Render Time
286.0
MiB
Memory Usage
Components
| Name | Metadata | Render Count | Render Time |
|---|---|---|---|
| ProductState |
"App\Twig\Components\ProductState"components/ProductState.html.twig |
3 | 0.71ms |
| ProductMostRecent |
"App\Twig\Components\ProductMostRecent"components/ProductMostRecent.html.twig |
3 | 2.19ms |
| ProductType |
"App\Twig\Components\ProductType"components/ProductType.html.twig |
1 | 0.22ms |
| ProductCard |
"App\Twig\Components\ProductCard"components/ProductCard.html.twig |
1 | 6.98ms |
Render calls
| ProductState | App\Twig\Components\ProductState | 286.0 MiB | 0.33 ms | |
|---|---|---|---|---|
| Input props | [ "product" => App\Entity\Product\Product {#7310 #id: 13057 #code: "IEEE00011429" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 …} #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751040833 {#7274 : 2025-06-27 18:13:53.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608621 {#7322 : 2025-08-08 01:17:01.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 47237 #name: "IEEE/IEC 62530-2:2023" #slug: "ieee-iec-62530-2-2023-ieee00011429-244716" #description: """ Adoption Standard - Active.<br />\n The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.<br />\n \t\t\t\t<br />\n This standard establishes the Universal Verification Methodology (UVM), a set of application programming interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog, IEEE Std 1800™.<br />\n Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting intellectual property (IP) for each new project or electronic design automation (EDA) tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE/IEC International Standard--SystemVerilog--Part 2: Universal Verification Methodology Language Reference Manual" -notes: "Active" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1697493600 {#7292 : 2023-10-17 00:00:00.0 Europe/Paris (+02:00) } -author: "" -publishedAt: DateTime @1697666400 {#7318 : 2023-10-19 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "62530-2" -bookCollection: "" -pageCount: 461 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } "showFullLabel" => "true" ] |
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| Attributes | [ "showFullLabel" => "true" ] |
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| Component | App\Twig\Components\ProductState {#93054 +product: App\Entity\Product\Product {#7310 #id: 13057 #code: "IEEE00011429" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 …} #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751040833 {#7274 : 2025-06-27 18:13:53.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608621 {#7322 : 2025-08-08 01:17:01.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 47237 #name: "IEEE/IEC 62530-2:2023" #slug: "ieee-iec-62530-2-2023-ieee00011429-244716" #description: """ Adoption Standard - Active.<br />\n The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.<br />\n \t\t\t\t<br />\n This standard establishes the Universal Verification Methodology (UVM), a set of application programming interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog, IEEE Std 1800™.<br />\n Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting intellectual property (IP) for each new project or electronic design automation (EDA) tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE/IEC International Standard--SystemVerilog--Part 2: Universal Verification Methodology Language Reference Manual" -notes: "Active" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1697493600 {#7292 : 2023-10-17 00:00:00.0 Europe/Paris (+02:00) } -author: "" -publishedAt: DateTime @1697666400 {#7318 : 2023-10-19 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "62530-2" -bookCollection: "" -pageCount: 461 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } +appearance: "state-active" +labels: [ "Active" ] -stateAttributeCode: "state" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …} } |
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| ProductType | App\Twig\Components\ProductType | 286.0 MiB | 0.22 ms | |
|---|---|---|---|---|
| Input props | [ "product" => App\Entity\Product\Product {#7310 #id: 13057 #code: "IEEE00011429" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 …} #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751040833 {#7274 : 2025-06-27 18:13:53.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608621 {#7322 : 2025-08-08 01:17:01.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 47237 #name: "IEEE/IEC 62530-2:2023" #slug: "ieee-iec-62530-2-2023-ieee00011429-244716" #description: """ Adoption Standard - Active.<br />\n The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.<br />\n \t\t\t\t<br />\n This standard establishes the Universal Verification Methodology (UVM), a set of application programming interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog, IEEE Std 1800™.<br />\n Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting intellectual property (IP) for each new project or electronic design automation (EDA) tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE/IEC International Standard--SystemVerilog--Part 2: Universal Verification Methodology Language Reference Manual" -notes: "Active" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1697493600 {#7292 : 2023-10-17 00:00:00.0 Europe/Paris (+02:00) } -author: "" -publishedAt: DateTime @1697666400 {#7318 : 2023-10-19 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "62530-2" -bookCollection: "" -pageCount: 461 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } ] |
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| Attributes | [] |
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| Component | App\Twig\Components\ProductType {#93234 +product: App\Entity\Product\Product {#7310 #id: 13057 #code: "IEEE00011429" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 …} #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751040833 {#7274 : 2025-06-27 18:13:53.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608621 {#7322 : 2025-08-08 01:17:01.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 47237 #name: "IEEE/IEC 62530-2:2023" #slug: "ieee-iec-62530-2-2023-ieee00011429-244716" #description: """ Adoption Standard - Active.<br />\n The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.<br />\n \t\t\t\t<br />\n This standard establishes the Universal Verification Methodology (UVM), a set of application programming interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog, IEEE Std 1800™.<br />\n Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting intellectual property (IP) for each new project or electronic design automation (EDA) tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE/IEC International Standard--SystemVerilog--Part 2: Universal Verification Methodology Language Reference Manual" -notes: "Active" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1697493600 {#7292 : 2023-10-17 00:00:00.0 Europe/Paris (+02:00) } -author: "" -publishedAt: DateTime @1697666400 {#7318 : 2023-10-19 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "62530-2" -bookCollection: "" -pageCount: 461 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } +label: "Standard" -typeAttributeCode: "type" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …} } |
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| ProductMostRecent | App\Twig\Components\ProductMostRecent | 286.0 MiB | 0.71 ms | |
|---|---|---|---|---|
| Input props | [ "product" => App\Entity\Product\Product {#7310 #id: 13057 #code: "IEEE00011429" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 …} #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751040833 {#7274 : 2025-06-27 18:13:53.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608621 {#7322 : 2025-08-08 01:17:01.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 47237 #name: "IEEE/IEC 62530-2:2023" #slug: "ieee-iec-62530-2-2023-ieee00011429-244716" #description: """ Adoption Standard - Active.<br />\n The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.<br />\n \t\t\t\t<br />\n This standard establishes the Universal Verification Methodology (UVM), a set of application programming interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog, IEEE Std 1800™.<br />\n Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting intellectual property (IP) for each new project or electronic design automation (EDA) tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE/IEC International Standard--SystemVerilog--Part 2: Universal Verification Methodology Language Reference Manual" -notes: "Active" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1697493600 {#7292 : 2023-10-17 00:00:00.0 Europe/Paris (+02:00) } -author: "" -publishedAt: DateTime @1697666400 {#7318 : 2023-10-19 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "62530-2" -bookCollection: "" -pageCount: 461 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } ] |
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| Attributes | [] |
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| Component | App\Twig\Components\ProductMostRecent {#93309 +product: App\Entity\Product\Product {#7310 #id: 13057 #code: "IEEE00011429" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 …} #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751040833 {#7274 : 2025-06-27 18:13:53.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608621 {#7322 : 2025-08-08 01:17:01.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 47237 #name: "IEEE/IEC 62530-2:2023" #slug: "ieee-iec-62530-2-2023-ieee00011429-244716" #description: """ Adoption Standard - Active.<br />\n The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.<br />\n \t\t\t\t<br />\n This standard establishes the Universal Verification Methodology (UVM), a set of application programming interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog, IEEE Std 1800™.<br />\n Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting intellectual property (IP) for each new project or electronic design automation (EDA) tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE/IEC International Standard--SystemVerilog--Part 2: Universal Verification Methodology Language Reference Manual" -notes: "Active" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1697493600 {#7292 : 2023-10-17 00:00:00.0 Europe/Paris (+02:00) } -author: "" -publishedAt: DateTime @1697666400 {#7318 : 2023-10-19 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "62530-2" -bookCollection: "" -pageCount: 461 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } +label: "Most Recent" +icon: "check-xs" -mostRecentAttributeCode: "most_recent" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …} } |
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| ProductState | App\Twig\Components\ProductState | 286.0 MiB | 0.20 ms | |
|---|---|---|---|---|
| Input props | [ "product" => App\Entity\Product\Product {#7310 #id: 13057 #code: "IEEE00011429" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 …} #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751040833 {#7274 : 2025-06-27 18:13:53.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608621 {#7322 : 2025-08-08 01:17:01.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 47237 #name: "IEEE/IEC 62530-2:2023" #slug: "ieee-iec-62530-2-2023-ieee00011429-244716" #description: """ Adoption Standard - Active.<br />\n The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.<br />\n \t\t\t\t<br />\n This standard establishes the Universal Verification Methodology (UVM), a set of application programming interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog, IEEE Std 1800™.<br />\n Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting intellectual property (IP) for each new project or electronic design automation (EDA) tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE/IEC International Standard--SystemVerilog--Part 2: Universal Verification Methodology Language Reference Manual" -notes: "Active" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1697493600 {#7292 : 2023-10-17 00:00:00.0 Europe/Paris (+02:00) } -author: "" -publishedAt: DateTime @1697666400 {#7318 : 2023-10-19 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "62530-2" -bookCollection: "" -pageCount: 461 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } "showFullLabel" => "true" ] |
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| Attributes | [ "showFullLabel" => "true" ] |
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| Component | App\Twig\Components\ProductState {#100265 +product: App\Entity\Product\Product {#7310 #id: 13057 #code: "IEEE00011429" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 …} #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751040833 {#7274 : 2025-06-27 18:13:53.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608621 {#7322 : 2025-08-08 01:17:01.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 47237 #name: "IEEE/IEC 62530-2:2023" #slug: "ieee-iec-62530-2-2023-ieee00011429-244716" #description: """ Adoption Standard - Active.<br />\n The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.<br />\n \t\t\t\t<br />\n This standard establishes the Universal Verification Methodology (UVM), a set of application programming interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog, IEEE Std 1800™.<br />\n Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting intellectual property (IP) for each new project or electronic design automation (EDA) tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE/IEC International Standard--SystemVerilog--Part 2: Universal Verification Methodology Language Reference Manual" -notes: "Active" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1697493600 {#7292 : 2023-10-17 00:00:00.0 Europe/Paris (+02:00) } -author: "" -publishedAt: DateTime @1697666400 {#7318 : 2023-10-19 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "62530-2" -bookCollection: "" -pageCount: 461 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } +appearance: "state-active" +labels: [ "Active" ] -stateAttributeCode: "state" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …} } |
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| ProductMostRecent | App\Twig\Components\ProductMostRecent | 286.0 MiB | 0.70 ms | |
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| ProductCard | App\Twig\Components\ProductCard | 286.0 MiB | 6.98 ms | |
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| Input props | [ "product" => App\Entity\Product\Product {#121578 #id: 11861 #code: "IEEE00006700" #attributes: Doctrine\ORM\PersistentCollection {#121602 …} #variants: Doctrine\ORM\PersistentCollection {#121600 …} #options: Doctrine\ORM\PersistentCollection {#121595 …} #associations: Doctrine\ORM\PersistentCollection {#121598 …} #createdAt: DateTime @1751040040 {#121591 : 2025-06-27 18:00:40.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608621 {#121584 : 2025-08-08 01:17:01.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#121613 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#121711 #locale: "en_US" #translatable: App\Entity\Product\Product {#121578} #id: 42453 #name: "IEEE 1800:2017" #slug: "ieee-1800-2017-ieee00006700-243513" #description: """ Revision Standard - Superseded.<br />\n The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.<br />\n \t\t\t\t<br />\n This standard provides the definition of the language syntax and semantics for the IEEE 1800(TM) SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#121611 …} #channels: Doctrine\ORM\PersistentCollection {#121604 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#121608 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#121606 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#121618 …} -apiLastModifiedAt: DateTime @1754517600 {#121577 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1709074800 {#121626 : 2024-02-28 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1519254000 {#121597 : 2018-02-22 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1800" -bookCollection: "" -pageCount: 1315 -documents: Doctrine\ORM\PersistentCollection {#121617 …} -favorites: Doctrine\ORM\PersistentCollection {#121615 …} } "layout" => "vertical" "showPrice" => true "showStatusBadges" => true "additionalClasses" => "product__teaser--with-grey-border" "hasStretchedLink" => true "hoverType" => "shadow" "linkLabel" => "See more" ] |
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| Component | App\Twig\Components\ProductCard {#121670 +product: App\Entity\Product\Product {#121578 #id: 11861 #code: "IEEE00006700" #attributes: Doctrine\ORM\PersistentCollection {#121602 …} #variants: Doctrine\ORM\PersistentCollection {#121600 …} #options: Doctrine\ORM\PersistentCollection {#121595 …} #associations: Doctrine\ORM\PersistentCollection {#121598 …} #createdAt: DateTime @1751040040 {#121591 : 2025-06-27 18:00:40.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608621 {#121584 : 2025-08-08 01:17:01.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#121613 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#121711 #locale: "en_US" #translatable: App\Entity\Product\Product {#121578} #id: 42453 #name: "IEEE 1800:2017" #slug: "ieee-1800-2017-ieee00006700-243513" #description: """ Revision Standard - Superseded.<br />\n The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.<br />\n \t\t\t\t<br />\n This standard provides the definition of the language syntax and semantics for the IEEE 1800(TM) SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#121611 …} #channels: Doctrine\ORM\PersistentCollection {#121604 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#121608 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#121606 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#121618 …} -apiLastModifiedAt: DateTime @1754517600 {#121577 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1709074800 {#121626 : 2024-02-28 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1519254000 {#121597 : 2018-02-22 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1800" -bookCollection: "" -pageCount: 1315 -documents: Doctrine\ORM\PersistentCollection {#121617 …} -favorites: Doctrine\ORM\PersistentCollection {#121615 …} } +layout: "vertical" +showPrice: true +showStatusBadges: true +additionalClasses: "product__teaser--with-grey-border" +linkLabel: "See more" +imageFilter: "product_thumbnail_teaser" +hasStretchedLink: true +backgroundColor: "white" +hoverType: "shadow" } |
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| ProductState | App\Twig\Components\ProductState | 286.0 MiB | 0.18 ms | |
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| Input props | [ "product" => App\Entity\Product\Product {#121578 #id: 11861 #code: "IEEE00006700" #attributes: Doctrine\ORM\PersistentCollection {#121602 …} #variants: Doctrine\ORM\PersistentCollection {#121600 …} #options: Doctrine\ORM\PersistentCollection {#121595 …} #associations: Doctrine\ORM\PersistentCollection {#121598 …} #createdAt: DateTime @1751040040 {#121591 : 2025-06-27 18:00:40.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608621 {#121584 : 2025-08-08 01:17:01.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#121613 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#121711 #locale: "en_US" #translatable: App\Entity\Product\Product {#121578} #id: 42453 #name: "IEEE 1800:2017" #slug: "ieee-1800-2017-ieee00006700-243513" #description: """ Revision Standard - Superseded.<br />\n The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.<br />\n \t\t\t\t<br />\n This standard provides the definition of the language syntax and semantics for the IEEE 1800(TM) SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#121611 …} #channels: Doctrine\ORM\PersistentCollection {#121604 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#121608 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#121606 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#121618 …} -apiLastModifiedAt: DateTime @1754517600 {#121577 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1709074800 {#121626 : 2024-02-28 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1519254000 {#121597 : 2018-02-22 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1800" -bookCollection: "" -pageCount: 1315 -documents: Doctrine\ORM\PersistentCollection {#121617 …} -favorites: Doctrine\ORM\PersistentCollection {#121615 …} } ] |
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| Component | App\Twig\Components\ProductState {#121713 +product: App\Entity\Product\Product {#121578 #id: 11861 #code: "IEEE00006700" #attributes: Doctrine\ORM\PersistentCollection {#121602 …} #variants: Doctrine\ORM\PersistentCollection {#121600 …} #options: Doctrine\ORM\PersistentCollection {#121595 …} #associations: Doctrine\ORM\PersistentCollection {#121598 …} #createdAt: DateTime @1751040040 {#121591 : 2025-06-27 18:00:40.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608621 {#121584 : 2025-08-08 01:17:01.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#121613 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#121711 #locale: "en_US" #translatable: App\Entity\Product\Product {#121578} #id: 42453 #name: "IEEE 1800:2017" #slug: "ieee-1800-2017-ieee00006700-243513" #description: """ Revision Standard - Superseded.<br />\n The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.<br />\n \t\t\t\t<br />\n This standard provides the definition of the language syntax and semantics for the IEEE 1800(TM) SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#121611 …} #channels: Doctrine\ORM\PersistentCollection {#121604 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#121608 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#121606 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#121618 …} -apiLastModifiedAt: DateTime @1754517600 {#121577 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1709074800 {#121626 : 2024-02-28 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1519254000 {#121597 : 2018-02-22 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1800" -bookCollection: "" -pageCount: 1315 -documents: Doctrine\ORM\PersistentCollection {#121617 …} -favorites: Doctrine\ORM\PersistentCollection {#121615 …} } +appearance: "state-suspended" +labels: [ "Superseded" ] -stateAttributeCode: "state" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …} } |
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| ProductMostRecent | App\Twig\Components\ProductMostRecent | 286.0 MiB | 0.79 ms | |
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| Input props | [ "product" => App\Entity\Product\Product {#121578 #id: 11861 #code: "IEEE00006700" #attributes: Doctrine\ORM\PersistentCollection {#121602 …} #variants: Doctrine\ORM\PersistentCollection {#121600 …} #options: Doctrine\ORM\PersistentCollection {#121595 …} #associations: Doctrine\ORM\PersistentCollection {#121598 …} #createdAt: DateTime @1751040040 {#121591 : 2025-06-27 18:00:40.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608621 {#121584 : 2025-08-08 01:17:01.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#121613 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#121711 #locale: "en_US" #translatable: App\Entity\Product\Product {#121578} #id: 42453 #name: "IEEE 1800:2017" #slug: "ieee-1800-2017-ieee00006700-243513" #description: """ Revision Standard - Superseded.<br />\n The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.<br />\n \t\t\t\t<br />\n This standard provides the definition of the language syntax and semantics for the IEEE 1800(TM) SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#121611 …} #channels: Doctrine\ORM\PersistentCollection {#121604 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#121608 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#121606 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#121618 …} -apiLastModifiedAt: DateTime @1754517600 {#121577 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1709074800 {#121626 : 2024-02-28 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1519254000 {#121597 : 2018-02-22 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1800" -bookCollection: "" -pageCount: 1315 -documents: Doctrine\ORM\PersistentCollection {#121617 …} -favorites: Doctrine\ORM\PersistentCollection {#121615 …} } ] |
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