Forms
sylius_add_to_cart
Errors
This form has no errors.
Default Data
| Property | Value |
|---|---|
| Model Format | same as normalized format |
| Normalized Format | Sylius\Bundle\OrderBundle\Controller\AddToCartCommand {#120433 -cart: App\Entity\Order\Order {#13330 …} -cartItem: App\Entity\Order\OrderItem {#120421 #id: null #order: null #quantity: 1 #unitPrice: 0 #originalUnitPrice: 0 #total: 0 #immutable: false #units: Doctrine\Common\Collections\ArrayCollection {#120445 …} #unitsTotal: 0 #adjustments: Doctrine\Common\Collections\ArrayCollection {#120446 …} #adjustmentsTotal: 0 #version: 1 #variant: App\Entity\Product\ProductVariant {#8099 #id: 3198 #code: "IEEE00002052PDF" #product: App\Entity\Product\Product {#7310 #id: 9318 #code: "IEEE00002052" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …} #initialized: true -snapshot: [ …4] -owner: App\Entity\Product\Product {#7310} -association: [ …21] -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …} -backRefFieldName: null -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#276079 …} -isDirty: false } #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751038164 {#7274 : 2025-06-27 17:29:24.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1753969444 {#7322 : 2025-07-31 15:44:04.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 32281 #name: "IEEE 1364:2001" #slug: "ieee-1364-2001-ieee00002052-240970" #description: """ Revision Standard - Superseded.<br />\n Supersedes 1364-1995. The Verilog(R) Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable,it supports the development,verification, synthesis,and testing of hardware designs; the communication of hardware design data; and the maintenance,modification,and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.<br />\n \t\t\t\t<br />\n Verilog is a Hardware Description Language which was standardized as IEEE 1364-1995. It is currently used by integrated circuit designers to specify their designs at the switch, gate and RTL levels. The proposed project will revise Verilog 1364 to include new constructs which improve the utility of the language both at the detailed physical level and at high levels of abstraction to meet industry needs for improved design technology.<br />\n To provide an industry standard based on the Verilog Hardware Description Language. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard Verilog Hardware Description Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1743289200 {#7317 : 2025-03-30 00:00:00.0 Europe/Paris (+01:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1001628000 {#7318 : 2001-09-28 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1364" -bookCollection: "" -pageCount: 792 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } #optionValues: Doctrine\ORM\PersistentCollection {#8315 …} #position: 0 #createdAt: DateTime @1751041154 {#7283 : 2025-06-27 18:19:14.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1755611970 {#8116 : 2025-08-19 15:59:30.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#8259 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductVariantTranslation {#93321 #locale: "en_US" #translatable: App\Entity\Product\ProductVariant {#8099} #id: 3216 #name: null -shortDescription: null -description: null -notes: null -shippingInformation: "Instant download" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #version: 9 #onHold: 0 #onHand: 0 #tracked: false #weight: 0.0 #width: null #height: null #depth: null #taxCategory: Proxies\__CG__\App\Entity\Taxation\TaxCategory {#8131 …} #shippingCategory: null #channelPricings: Doctrine\ORM\PersistentCollection {#8293 …} #shippingRequired: true #images: Doctrine\ORM\PersistentCollection {#8290 …} -apiLastModifiedAt: DateTime @1753740000 {#8098 : 2025-07-29 00:00:00.0 Europe/Paris (+02:00) } -publishedAt: null -isbn: "978-0-7381-2827-6" -ean: "9780738128276" -numberOfUsers: 1 -physicalProduct: false -downloadableImmediately: true -downloadable: true -drmViewerUrl: "https://online-viewer.normadoc.com/2pKfCZ" -sellable: true -documents: Doctrine\ORM\PersistentCollection {#8127 …} -drmTokens: Doctrine\ORM\PersistentCollection {#8119 …} -enabledForSubscribers: true -currentAreaContext: null } #productName: null #variantName: null } } |
| View Format | same as normalized format |
Submitted Data
This form was not submitted.
Passed Options
| Option | Passed Value | Resolved Value |
|---|---|---|
| data | Sylius\Bundle\OrderBundle\Controller\AddToCartCommand {#120433 -cart: App\Entity\Order\Order {#13330 …} -cartItem: App\Entity\Order\OrderItem {#120421 #id: null #order: null #quantity: 1 #unitPrice: 0 #originalUnitPrice: 0 #total: 0 #immutable: false #units: Doctrine\Common\Collections\ArrayCollection {#120445 …} #unitsTotal: 0 #adjustments: Doctrine\Common\Collections\ArrayCollection {#120446 …} #adjustmentsTotal: 0 #version: 1 #variant: App\Entity\Product\ProductVariant {#8099 #id: 3198 #code: "IEEE00002052PDF" #product: App\Entity\Product\Product {#7310 #id: 9318 #code: "IEEE00002052" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …} #initialized: true -snapshot: [ …4] -owner: App\Entity\Product\Product {#7310} -association: [ …21] -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …} -backRefFieldName: null -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#276079 …} -isDirty: false } #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751038164 {#7274 : 2025-06-27 17:29:24.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1753969444 {#7322 : 2025-07-31 15:44:04.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 32281 #name: "IEEE 1364:2001" #slug: "ieee-1364-2001-ieee00002052-240970" #description: """ Revision Standard - Superseded.<br />\n Supersedes 1364-1995. The Verilog(R) Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable,it supports the development,verification, synthesis,and testing of hardware designs; the communication of hardware design data; and the maintenance,modification,and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.<br />\n \t\t\t\t<br />\n Verilog is a Hardware Description Language which was standardized as IEEE 1364-1995. It is currently used by integrated circuit designers to specify their designs at the switch, gate and RTL levels. The proposed project will revise Verilog 1364 to include new constructs which improve the utility of the language both at the detailed physical level and at high levels of abstraction to meet industry needs for improved design technology.<br />\n To provide an industry standard based on the Verilog Hardware Description Language. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard Verilog Hardware Description Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1743289200 {#7317 : 2025-03-30 00:00:00.0 Europe/Paris (+01:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1001628000 {#7318 : 2001-09-28 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1364" -bookCollection: "" -pageCount: 792 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } #optionValues: Doctrine\ORM\PersistentCollection {#8315 …} #position: 0 #createdAt: DateTime @1751041154 {#7283 : 2025-06-27 18:19:14.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1755611970 {#8116 : 2025-08-19 15:59:30.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#8259 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductVariantTranslation {#93321 #locale: "en_US" #translatable: App\Entity\Product\ProductVariant {#8099} #id: 3216 #name: null -shortDescription: null -description: null -notes: null -shippingInformation: "Instant download" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #version: 9 #onHold: 0 #onHand: 0 #tracked: false #weight: 0.0 #width: null #height: null #depth: null #taxCategory: Proxies\__CG__\App\Entity\Taxation\TaxCategory {#8131 …} #shippingCategory: null #channelPricings: Doctrine\ORM\PersistentCollection {#8293 …} #shippingRequired: true #images: Doctrine\ORM\PersistentCollection {#8290 …} -apiLastModifiedAt: DateTime @1753740000 {#8098 : 2025-07-29 00:00:00.0 Europe/Paris (+02:00) } -publishedAt: null -isbn: "978-0-7381-2827-6" -ean: "9780738128276" -numberOfUsers: 1 -physicalProduct: false -downloadableImmediately: true -downloadable: true -drmViewerUrl: "https://online-viewer.normadoc.com/2pKfCZ" -sellable: true -documents: Doctrine\ORM\PersistentCollection {#8127 …} -drmTokens: Doctrine\ORM\PersistentCollection {#8119 …} -enabledForSubscribers: true -currentAreaContext: null } #productName: null #variantName: null } } |
same as passed value |
| product | App\Entity\Product\Product {#7310 #id: 9318 #code: "IEEE00002052" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …} #initialized: true -snapshot: [ …4] -owner: App\Entity\Product\Product {#7310} -association: [ …21] -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …} -backRefFieldName: null -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#276079 …} -isDirty: false } #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751038164 {#7274 : 2025-06-27 17:29:24.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1753969444 {#7322 : 2025-07-31 15:44:04.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 32281 #name: "IEEE 1364:2001" #slug: "ieee-1364-2001-ieee00002052-240970" #description: """ Revision Standard - Superseded.<br />\n Supersedes 1364-1995. The Verilog(R) Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable,it supports the development,verification, synthesis,and testing of hardware designs; the communication of hardware design data; and the maintenance,modification,and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.<br />\n \t\t\t\t<br />\n Verilog is a Hardware Description Language which was standardized as IEEE 1364-1995. It is currently used by integrated circuit designers to specify their designs at the switch, gate and RTL levels. The proposed project will revise Verilog 1364 to include new constructs which improve the utility of the language both at the detailed physical level and at high levels of abstraction to meet industry needs for improved design technology.<br />\n To provide an industry standard based on the Verilog Hardware Description Language. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard Verilog Hardware Description Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1743289200 {#7317 : 2025-03-30 00:00:00.0 Europe/Paris (+01:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1001628000 {#7318 : 2001-09-28 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1364" -bookCollection: "" -pageCount: 792 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } |
same as passed value |
Resolved Options
| Option | Value |
|---|---|
| action | "" |
| allow_extra_fields | false |
| allow_file_upload | false |
| attr | [] |
| attr_translation_parameters | [] |
| auto_initialize | true |
| block_name | null |
| block_prefix | null |
| by_reference | true |
| compound | true |
| constraints | [] |
| csrf_field_name | "_token" |
| csrf_message | "The CSRF token is invalid. Please try to resubmit the form." |
| csrf_protection | true |
| csrf_token_id | null |
| csrf_token_manager | Symfony\Component\Security\Csrf\CsrfTokenManager {#120453 -generator: Symfony\Component\Security\Csrf\TokenGenerator\UriSafeTokenGenerator {#120454 …} -storage: Symfony\Component\Security\Csrf\TokenStorage\SessionTokenStorage {#120455 …} -namespace: Closure() {#120457 …} } |
| data | Sylius\Bundle\OrderBundle\Controller\AddToCartCommand {#120433 -cart: App\Entity\Order\Order {#13330 …} -cartItem: App\Entity\Order\OrderItem {#120421 #id: null #order: null #quantity: 1 #unitPrice: 0 #originalUnitPrice: 0 #total: 0 #immutable: false #units: Doctrine\Common\Collections\ArrayCollection {#120445 …} #unitsTotal: 0 #adjustments: Doctrine\Common\Collections\ArrayCollection {#120446 …} #adjustmentsTotal: 0 #version: 1 #variant: App\Entity\Product\ProductVariant {#8099 #id: 3198 #code: "IEEE00002052PDF" #product: App\Entity\Product\Product {#7310 #id: 9318 #code: "IEEE00002052" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …} #initialized: true -snapshot: [ …4] -owner: App\Entity\Product\Product {#7310} -association: [ …21] -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …} -backRefFieldName: null -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#276079 …} -isDirty: false } #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751038164 {#7274 : 2025-06-27 17:29:24.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1753969444 {#7322 : 2025-07-31 15:44:04.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 32281 #name: "IEEE 1364:2001" #slug: "ieee-1364-2001-ieee00002052-240970" #description: """ Revision Standard - Superseded.<br />\n Supersedes 1364-1995. The Verilog(R) Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable,it supports the development,verification, synthesis,and testing of hardware designs; the communication of hardware design data; and the maintenance,modification,and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.<br />\n \t\t\t\t<br />\n Verilog is a Hardware Description Language which was standardized as IEEE 1364-1995. It is currently used by integrated circuit designers to specify their designs at the switch, gate and RTL levels. The proposed project will revise Verilog 1364 to include new constructs which improve the utility of the language both at the detailed physical level and at high levels of abstraction to meet industry needs for improved design technology.<br />\n To provide an industry standard based on the Verilog Hardware Description Language. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard Verilog Hardware Description Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1743289200 {#7317 : 2025-03-30 00:00:00.0 Europe/Paris (+01:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1001628000 {#7318 : 2001-09-28 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1364" -bookCollection: "" -pageCount: 792 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } #optionValues: Doctrine\ORM\PersistentCollection {#8315 …} #position: 0 #createdAt: DateTime @1751041154 {#7283 : 2025-06-27 18:19:14.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1755611970 {#8116 : 2025-08-19 15:59:30.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#8259 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductVariantTranslation {#93321 #locale: "en_US" #translatable: App\Entity\Product\ProductVariant {#8099} #id: 3216 #name: null -shortDescription: null -description: null -notes: null -shippingInformation: "Instant download" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #version: 9 #onHold: 0 #onHand: 0 #tracked: false #weight: 0.0 #width: null #height: null #depth: null #taxCategory: Proxies\__CG__\App\Entity\Taxation\TaxCategory {#8131 …} #shippingCategory: null #channelPricings: Doctrine\ORM\PersistentCollection {#8293 …} #shippingRequired: true #images: Doctrine\ORM\PersistentCollection {#8290 …} -apiLastModifiedAt: DateTime @1753740000 {#8098 : 2025-07-29 00:00:00.0 Europe/Paris (+02:00) } -publishedAt: null -isbn: "978-0-7381-2827-6" -ean: "9780738128276" -numberOfUsers: 1 -physicalProduct: false -downloadableImmediately: true -downloadable: true -drmViewerUrl: "https://online-viewer.normadoc.com/2pKfCZ" -sellable: true -documents: Doctrine\ORM\PersistentCollection {#8127 …} -drmTokens: Doctrine\ORM\PersistentCollection {#8119 …} -enabledForSubscribers: true -currentAreaContext: null } #productName: null #variantName: null } } |
| data_class | "Sylius\Bundle\OrderBundle\Controller\AddToCartCommand" |
| disabled | false |
| empty_data | Closure(FormInterface $form) {#120480 : "Symfony\Component\Form\Extension\Core\Type\FormType" : { : "Sylius\Bundle\OrderBundle\Controller\AddToCartCommand" } } |
| error_bubbling | true |
| error_mapping | [] |
| extra_fields_message | "This form should not contain extra fields." |
| form_attr | false |
| getter | null |
| help | null |
| help_attr | [] |
| help_html | false |
| help_translation_parameters | [] |
| inherit_data | false |
| invalid_message | "This value is not valid." |
| invalid_message_parameters | [] |
| is_empty_callback | null |
| label | null |
| label_attr | [] |
| label_format | null |
| label_html | false |
| label_translation_parameters | [] |
| mapped | true |
| method | "POST" |
| post_max_size_message | "The uploaded file was too large. Please try to upload a smaller file." |
| priority | 0 |
| product | App\Entity\Product\Product {#7310 #id: 9318 #code: "IEEE00002052" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …} #initialized: true -snapshot: [ …4] -owner: App\Entity\Product\Product {#7310} -association: [ …21] -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …} -backRefFieldName: null -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#276079 …} -isDirty: false } #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751038164 {#7274 : 2025-06-27 17:29:24.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1753969444 {#7322 : 2025-07-31 15:44:04.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 32281 #name: "IEEE 1364:2001" #slug: "ieee-1364-2001-ieee00002052-240970" #description: """ Revision Standard - Superseded.<br />\n Supersedes 1364-1995. The Verilog(R) Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable,it supports the development,verification, synthesis,and testing of hardware designs; the communication of hardware design data; and the maintenance,modification,and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.<br />\n \t\t\t\t<br />\n Verilog is a Hardware Description Language which was standardized as IEEE 1364-1995. It is currently used by integrated circuit designers to specify their designs at the switch, gate and RTL levels. The proposed project will revise Verilog 1364 to include new constructs which improve the utility of the language both at the detailed physical level and at high levels of abstraction to meet industry needs for improved design technology.<br />\n To provide an industry standard based on the Verilog Hardware Description Language. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard Verilog Hardware Description Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1743289200 {#7317 : 2025-03-30 00:00:00.0 Europe/Paris (+01:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1001628000 {#7318 : 2001-09-28 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1364" -bookCollection: "" -pageCount: 792 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } |
| property_path | null |
| required | true |
| row_attr | [] |
| setter | null |
| translation_domain | null |
| trim | true |
| upload_max_size_message | Closure() {#120482 : "Symfony\Component\Form\Extension\Validator\Type\UploadValidatorExtension" : { : Symfony\Component\Translation\DataCollectorTranslator {#2251 …} : Closure() {#120481 …} : "validators" } } |
| validation_groups | [
"sylius"
] |
View Vars
| Variable | Value |
|---|---|
| action | "" |
| attr | [] |
| attr_translation_parameters | [] |
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| errors | Symfony\Component\Form\FormErrorIterator {#120507 -form: Symfony\Component\Form\Form {#120512 …} -errors: [] } |
| form | Symfony\Component\Form\FormView {#120483 …5} |
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| help_attr | [] |
| help_html | false |
| help_translation_parameters | [] |
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| label_attr | [] |
| label_format | null |
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| label_translation_parameters | [] |
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| multipart | false |
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| required | true |
| row_attr | [] |
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| translation_domain | null |
| unique_block_prefix | "_sylius_add_to_cart" |
| valid | true |
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