Symfony Profiler

Components

3 Twig Components

5 Render Count

2 ms Render Time

78.0 MiB Memory Usage

Components

Name	Metadata	Render Count	Render Time
ProductState	"App\Twig\Components\ProductState" components/ProductState.html.twig	2	0.54ms
ProductMostRecent	"App\Twig\Components\ProductMostRecent" components/ProductMostRecent.html.twig	2	1.56ms
ProductType	"App\Twig\Components\ProductType" components/ProductType.html.twig	1	0.22ms

Render calls

ProductState	App\Twig\Components\ProductState	78.0 MiB	0.32 ms
Input props	["product" => App\Entity\Product\Product {#7309 #id: 9272 #code: "IEEE00001971" #attributes: Doctrine\ORM\PersistentCollection {#7702 …} #variants: Doctrine\ORM\PersistentCollection {#7745 …} #options: Doctrine\ORM\PersistentCollection {#7917 …} #associations: Doctrine\ORM\PersistentCollection {#7901 …} #createdAt: DateTime @1751038125 {#7274 date: 2025-06-27 17:28:45.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607004 {#7322 date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7923 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7922 #locale: "en_US" #translatable: App\Entity\Product\Product {#7309} #id: 32097 #name: "IEEE 1296:1987 (R1994)" #slug: "ieee-1296-1987-r1994-ieee00001971-240924" #description: """ New IEEE Standard - Inactive-Withdrawn.<br />\n This standard describes a high-performance backplane bus intended for use in multiple processor systems. The bus incorporates synchronous, 32-bit multiplexed addreddata, with error detection and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of cost-effective high performance VLSI for the bus interface. The standard defines memory, I/O, message, and geographic address spaces. The memory space supports single and block transfers. The message space defines a high-level protocol for transferring blocks of data (messages) as multiple packets of data (small data bursts; e.g., 32 bytes in one microsecond) over the bus. This provides a highperformance (e.g., 32 megabytes/second) interprocessor communication transfers among many different processors on the bus. Error detection and retry is provided for messages. This message passing design also allows a VLSI implementation, such that virtually all modules on the bus will utilize the bus at its highest performance - 32 to 40 megabytes/second. The standard provides geographic addressing for ease of configurability, initialization, and diagnostics.<br />\n \t\t\t\t<br />\n This document defines the operation, functions, and attributes of the IEEE 1296 bus standard.<br />\n (1) This standard defines a high-performance 32-bit synchronous bus standard.<br />\n (2) The bus standard must have a design-in lifetime of 10 years with backward compatibility.<br />\n (3) The standard is intended for general purpose applications to optimize block transfers, including protocol for message passing. For real-time applications, the bus will provide a means of ensuring an upper limit to message delivery time.<br />\n (4) The standard is intended to be compatible with existing IEC [I], [2], [3] mechanical standards with recognition of the need for special front panels to address ESD, EMI, and RFI requirements.<br />\n (5) Options within the standard will be clearly identified.<br />\n (6) The standard is intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system.<br />\n (7) The standard is intended to support heterogeneous processor types in the same system.<br />\n (8) Message passing format and protocol is intended for future migration to a serial system bus. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for a High-Performance Synchronous 32-Bit Bus: MULTIBUS II" -notes: "Inactive-Withdrawn" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7535 …} #channels: Doctrine\ORM\PersistentCollection {#7629 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7308 …} #reviews: Doctrine\ORM\PersistentCollection {#7614 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7646 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7422 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7420 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @586562400 {#7318 date: 1988-08-03 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: DateTime @763858800 {#7316 date: 1994-03-17 00:00:00.0 Europe/Paris (+01:00) } -canceledAt: DateTime @1010617200 {#7315 date: 2002-01-10 00:00:00.0 Europe/Paris (+01:00) } -edition: null -coreDocument: "1296" -bookCollection: "" -pageCount: 260 -documents: Doctrine\ORM\PersistentCollection {#7466 …} -favorites: Doctrine\ORM\PersistentCollection {#7501 …} } "showFullLabel" => "true"]
Attributes	[`"showFullLabel" => "true"`]
Component	App\Twig\Components\ProductState {#93009+product: App\Entity\Product\Product {#7309 #id: 9272 #code: "IEEE00001971" #attributes: Doctrine\ORM\PersistentCollection {#7702 …} #variants: Doctrine\ORM\PersistentCollection {#7745 …} #options: Doctrine\ORM\PersistentCollection {#7917 …} #associations: Doctrine\ORM\PersistentCollection {#7901 …} #createdAt: DateTime @1751038125 {#7274 date: 2025-06-27 17:28:45.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607004 {#7322 date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7923 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7922 #locale: "en_US" #translatable: App\Entity\Product\Product {#7309} #id: 32097 #name: "IEEE 1296:1987 (R1994)" #slug: "ieee-1296-1987-r1994-ieee00001971-240924" #description: """ New IEEE Standard - Inactive-Withdrawn.<br />\n This standard describes a high-performance backplane bus intended for use in multiple processor systems. The bus incorporates synchronous, 32-bit multiplexed addreddata, with error detection and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of cost-effective high performance VLSI for the bus interface. The standard defines memory, I/O, message, and geographic address spaces. The memory space supports single and block transfers. The message space defines a high-level protocol for transferring blocks of data (messages) as multiple packets of data (small data bursts; e.g., 32 bytes in one microsecond) over the bus. This provides a highperformance (e.g., 32 megabytes/second) interprocessor communication transfers among many different processors on the bus. Error detection and retry is provided for messages. This message passing design also allows a VLSI implementation, such that virtually all modules on the bus will utilize the bus at its highest performance - 32 to 40 megabytes/second. The standard provides geographic addressing for ease of configurability, initialization, and diagnostics.<br />\n \t\t\t\t<br />\n This document defines the operation, functions, and attributes of the IEEE 1296 bus standard.<br />\n (1) This standard defines a high-performance 32-bit synchronous bus standard.<br />\n (2) The bus standard must have a design-in lifetime of 10 years with backward compatibility.<br />\n (3) The standard is intended for general purpose applications to optimize block transfers, including protocol for message passing. For real-time applications, the bus will provide a means of ensuring an upper limit to message delivery time.<br />\n (4) The standard is intended to be compatible with existing IEC [I], [2], [3] mechanical standards with recognition of the need for special front panels to address ESD, EMI, and RFI requirements.<br />\n (5) Options within the standard will be clearly identified.<br />\n (6) The standard is intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system.<br />\n (7) The standard is intended to support heterogeneous processor types in the same system.<br />\n (8) Message passing format and protocol is intended for future migration to a serial system bus. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for a High-Performance Synchronous 32-Bit Bus: MULTIBUS II" -notes: "Inactive-Withdrawn" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7535 …} #channels: Doctrine\ORM\PersistentCollection {#7629 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7308 …} #reviews: Doctrine\ORM\PersistentCollection {#7614 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7646 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7422 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7420 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @586562400 {#7318 date: 1988-08-03 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: DateTime @763858800 {#7316 date: 1994-03-17 00:00:00.0 Europe/Paris (+01:00) } -canceledAt: DateTime @1010617200 {#7315 date: 2002-01-10 00:00:00.0 Europe/Paris (+01:00) } -edition: null -coreDocument: "1296" -bookCollection: "" -pageCount: 260 -documents: Doctrine\ORM\PersistentCollection {#7466 …} -favorites: Doctrine\ORM\PersistentCollection {#7501 …} } +appearance: "state-withdrawn" +labels: [ "Withdrawn" "Confirmed" ] -stateAttributeCode: "state" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}}

ProductState

App\Twig\Components\ProductState

78.0 MiB

0.32 ms

Input props

[
  "product" => App\Entity\Product\Product {#7309
    #id: 9272
    #code: "IEEE00001971"
    #attributes: Doctrine\ORM\PersistentCollection {#7702 …}
    #variants: Doctrine\ORM\PersistentCollection {#7745 …}
    #options: Doctrine\ORM\PersistentCollection {#7917 …}
    #associations: Doctrine\ORM\PersistentCollection {#7901 …}
    #createdAt: DateTime @1751038125 {#7274
      date: 2025-06-27 17:28:45.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#7322
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7923 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7922
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7309}
        #id: 32097
        #name: "IEEE 1296:1987 (R1994)"
        #slug: "ieee-1296-1987-r1994-ieee00001971-240924"
        #description: """
          New IEEE Standard - Inactive-Withdrawn.<br />\n
          This standard describes a high-performance backplane bus intended for use in multiple processor systems. The bus incorporates synchronous, 32-bit multiplexed addreddata, with error detection and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of cost-effective high performance VLSI for the bus interface. The standard defines memory, I/O, message, and geographic address spaces. The memory space supports single and block transfers. The message space defines a high-level protocol for transferring blocks of data (messages) as multiple packets of data (small data bursts; e.g., 32 bytes in one microsecond) over the bus. This provides a highperformance (e.g., 32 megabytes/second) interprocessor communication transfers among many different processors on the bus. Error detection and retry is provided for messages. This message passing design also allows a VLSI implementation, such that virtually all modules on the bus will utilize the bus at its highest performance - 32 to 40 megabytes/second. The standard provides geographic addressing for ease of configurability, initialization, and diagnostics.<br />\n
          \t\t\t\t<br />\n
          This document defines the operation, functions, and attributes of the IEEE 1296 bus standard.<br />\n
          (1) This standard defines a high-performance 32-bit synchronous bus standard.<br />\n
          (2) The bus standard must have a design-in lifetime of 10 years with backward compatibility.<br />\n
          (3) The standard is intended for general purpose applications to optimize block transfers, including protocol for message passing. For real-time applications, the bus will provide a means of ensuring an upper limit to message delivery time.<br />\n
          (4) The standard is intended to be compatible with existing IEC [I], [2], [3] mechanical standards with recognition of the need for special front panels to address ESD, EMI, and RFI requirements.<br />\n
          (5) Options within the standard will be clearly identified.<br />\n
          (6) The standard is intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system.<br />\n
          (7) The standard is intended to support heterogeneous processor types in the same system.<br />\n
          (8) Message passing format and protocol is intended for future migration to a serial system bus.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for a High-Performance Synchronous 32-Bit Bus: MULTIBUS II"
        -notes: "Inactive-Withdrawn"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7535 …}
    #channels: Doctrine\ORM\PersistentCollection {#7629 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7308 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7614 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7646 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7422 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7420 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @586562400 {#7318
      date: 1988-08-03 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: DateTime @763858800 {#7316
      date: 1994-03-17 00:00:00.0 Europe/Paris (+01:00)
    }
    -canceledAt: DateTime @1010617200 {#7315
      date: 2002-01-10 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1296"
    -bookCollection: ""
    -pageCount: 260
    -documents: Doctrine\ORM\PersistentCollection {#7466 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7501 …}
  }
  "showFullLabel" => "true"
]

Attributes

[
  "showFullLabel" => "true"
]

Component

App\Twig\Components\ProductState {#93009
  +product: App\Entity\Product\Product {#7309
    #id: 9272
    #code: "IEEE00001971"
    #attributes: Doctrine\ORM\PersistentCollection {#7702 …}
    #variants: Doctrine\ORM\PersistentCollection {#7745 …}
    #options: Doctrine\ORM\PersistentCollection {#7917 …}
    #associations: Doctrine\ORM\PersistentCollection {#7901 …}
    #createdAt: DateTime @1751038125 {#7274
      date: 2025-06-27 17:28:45.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#7322
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7923 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7922
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7309}
        #id: 32097
        #name: "IEEE 1296:1987 (R1994)"
        #slug: "ieee-1296-1987-r1994-ieee00001971-240924"
        #description: """
          New IEEE Standard - Inactive-Withdrawn.<br />\n
          This standard describes a high-performance backplane bus intended for use in multiple processor systems. The bus incorporates synchronous, 32-bit multiplexed addreddata, with error detection and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of cost-effective high performance VLSI for the bus interface. The standard defines memory, I/O, message, and geographic address spaces. The memory space supports single and block transfers. The message space defines a high-level protocol for transferring blocks of data (messages) as multiple packets of data (small data bursts; e.g., 32 bytes in one microsecond) over the bus. This provides a highperformance (e.g., 32 megabytes/second) interprocessor communication transfers among many different processors on the bus. Error detection and retry is provided for messages. This message passing design also allows a VLSI implementation, such that virtually all modules on the bus will utilize the bus at its highest performance - 32 to 40 megabytes/second. The standard provides geographic addressing for ease of configurability, initialization, and diagnostics.<br />\n
          \t\t\t\t<br />\n
          This document defines the operation, functions, and attributes of the IEEE 1296 bus standard.<br />\n
          (1) This standard defines a high-performance 32-bit synchronous bus standard.<br />\n
          (2) The bus standard must have a design-in lifetime of 10 years with backward compatibility.<br />\n
          (3) The standard is intended for general purpose applications to optimize block transfers, including protocol for message passing. For real-time applications, the bus will provide a means of ensuring an upper limit to message delivery time.<br />\n
          (4) The standard is intended to be compatible with existing IEC [I], [2], [3] mechanical standards with recognition of the need for special front panels to address ESD, EMI, and RFI requirements.<br />\n
          (5) Options within the standard will be clearly identified.<br />\n
          (6) The standard is intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system.<br />\n
          (7) The standard is intended to support heterogeneous processor types in the same system.<br />\n
          (8) Message passing format and protocol is intended for future migration to a serial system bus.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for a High-Performance Synchronous 32-Bit Bus: MULTIBUS II"
        -notes: "Inactive-Withdrawn"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7535 …}
    #channels: Doctrine\ORM\PersistentCollection {#7629 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7308 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7614 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7646 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7422 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7420 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @586562400 {#7318
      date: 1988-08-03 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: DateTime @763858800 {#7316
      date: 1994-03-17 00:00:00.0 Europe/Paris (+01:00)
    }
    -canceledAt: DateTime @1010617200 {#7315
      date: 2002-01-10 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1296"
    -bookCollection: ""
    -pageCount: 260
    -documents: Doctrine\ORM\PersistentCollection {#7466 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7501 …}
  }
  +appearance: "state-withdrawn"
  +labels: [
    "Withdrawn"
    "Confirmed"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

ProductType	App\Twig\Components\ProductType	78.0 MiB	0.22 ms
Input props	["product" => App\Entity\Product\Product {#7309 #id: 9272 #code: "IEEE00001971" #attributes: Doctrine\ORM\PersistentCollection {#7702 …} #variants: Doctrine\ORM\PersistentCollection {#7745 …} #options: Doctrine\ORM\PersistentCollection {#7917 …} #associations: Doctrine\ORM\PersistentCollection {#7901 …} #createdAt: DateTime @1751038125 {#7274 date: 2025-06-27 17:28:45.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607004 {#7322 date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7923 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7922 #locale: "en_US" #translatable: App\Entity\Product\Product {#7309} #id: 32097 #name: "IEEE 1296:1987 (R1994)" #slug: "ieee-1296-1987-r1994-ieee00001971-240924" #description: """ New IEEE Standard - Inactive-Withdrawn.<br />\n This standard describes a high-performance backplane bus intended for use in multiple processor systems. The bus incorporates synchronous, 32-bit multiplexed addreddata, with error detection and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of cost-effective high performance VLSI for the bus interface. The standard defines memory, I/O, message, and geographic address spaces. The memory space supports single and block transfers. The message space defines a high-level protocol for transferring blocks of data (messages) as multiple packets of data (small data bursts; e.g., 32 bytes in one microsecond) over the bus. This provides a highperformance (e.g., 32 megabytes/second) interprocessor communication transfers among many different processors on the bus. Error detection and retry is provided for messages. This message passing design also allows a VLSI implementation, such that virtually all modules on the bus will utilize the bus at its highest performance - 32 to 40 megabytes/second. The standard provides geographic addressing for ease of configurability, initialization, and diagnostics.<br />\n \t\t\t\t<br />\n This document defines the operation, functions, and attributes of the IEEE 1296 bus standard.<br />\n (1) This standard defines a high-performance 32-bit synchronous bus standard.<br />\n (2) The bus standard must have a design-in lifetime of 10 years with backward compatibility.<br />\n (3) The standard is intended for general purpose applications to optimize block transfers, including protocol for message passing. For real-time applications, the bus will provide a means of ensuring an upper limit to message delivery time.<br />\n (4) The standard is intended to be compatible with existing IEC [I], [2], [3] mechanical standards with recognition of the need for special front panels to address ESD, EMI, and RFI requirements.<br />\n (5) Options within the standard will be clearly identified.<br />\n (6) The standard is intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system.<br />\n (7) The standard is intended to support heterogeneous processor types in the same system.<br />\n (8) Message passing format and protocol is intended for future migration to a serial system bus. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for a High-Performance Synchronous 32-Bit Bus: MULTIBUS II" -notes: "Inactive-Withdrawn" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7535 …} #channels: Doctrine\ORM\PersistentCollection {#7629 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7308 …} #reviews: Doctrine\ORM\PersistentCollection {#7614 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7646 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7422 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7420 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @586562400 {#7318 date: 1988-08-03 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: DateTime @763858800 {#7316 date: 1994-03-17 00:00:00.0 Europe/Paris (+01:00) } -canceledAt: DateTime @1010617200 {#7315 date: 2002-01-10 00:00:00.0 Europe/Paris (+01:00) } -edition: null -coreDocument: "1296" -bookCollection: "" -pageCount: 260 -documents: Doctrine\ORM\PersistentCollection {#7466 …} -favorites: Doctrine\ORM\PersistentCollection {#7501 …} }]
Attributes	[]
Component	App\Twig\Components\ProductType {#93202+product: App\Entity\Product\Product {#7309 #id: 9272 #code: "IEEE00001971" #attributes: Doctrine\ORM\PersistentCollection {#7702 …} #variants: Doctrine\ORM\PersistentCollection {#7745 …} #options: Doctrine\ORM\PersistentCollection {#7917 …} #associations: Doctrine\ORM\PersistentCollection {#7901 …} #createdAt: DateTime @1751038125 {#7274 date: 2025-06-27 17:28:45.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607004 {#7322 date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7923 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7922 #locale: "en_US" #translatable: App\Entity\Product\Product {#7309} #id: 32097 #name: "IEEE 1296:1987 (R1994)" #slug: "ieee-1296-1987-r1994-ieee00001971-240924" #description: """ New IEEE Standard - Inactive-Withdrawn.<br />\n This standard describes a high-performance backplane bus intended for use in multiple processor systems. The bus incorporates synchronous, 32-bit multiplexed addreddata, with error detection and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of cost-effective high performance VLSI for the bus interface. The standard defines memory, I/O, message, and geographic address spaces. The memory space supports single and block transfers. The message space defines a high-level protocol for transferring blocks of data (messages) as multiple packets of data (small data bursts; e.g., 32 bytes in one microsecond) over the bus. This provides a highperformance (e.g., 32 megabytes/second) interprocessor communication transfers among many different processors on the bus. Error detection and retry is provided for messages. This message passing design also allows a VLSI implementation, such that virtually all modules on the bus will utilize the bus at its highest performance - 32 to 40 megabytes/second. The standard provides geographic addressing for ease of configurability, initialization, and diagnostics.<br />\n \t\t\t\t<br />\n This document defines the operation, functions, and attributes of the IEEE 1296 bus standard.<br />\n (1) This standard defines a high-performance 32-bit synchronous bus standard.<br />\n (2) The bus standard must have a design-in lifetime of 10 years with backward compatibility.<br />\n (3) The standard is intended for general purpose applications to optimize block transfers, including protocol for message passing. For real-time applications, the bus will provide a means of ensuring an upper limit to message delivery time.<br />\n (4) The standard is intended to be compatible with existing IEC [I], [2], [3] mechanical standards with recognition of the need for special front panels to address ESD, EMI, and RFI requirements.<br />\n (5) Options within the standard will be clearly identified.<br />\n (6) The standard is intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system.<br />\n (7) The standard is intended to support heterogeneous processor types in the same system.<br />\n (8) Message passing format and protocol is intended for future migration to a serial system bus. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for a High-Performance Synchronous 32-Bit Bus: MULTIBUS II" -notes: "Inactive-Withdrawn" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7535 …} #channels: Doctrine\ORM\PersistentCollection {#7629 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7308 …} #reviews: Doctrine\ORM\PersistentCollection {#7614 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7646 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7422 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7420 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @586562400 {#7318 date: 1988-08-03 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: DateTime @763858800 {#7316 date: 1994-03-17 00:00:00.0 Europe/Paris (+01:00) } -canceledAt: DateTime @1010617200 {#7315 date: 2002-01-10 00:00:00.0 Europe/Paris (+01:00) } -edition: null -coreDocument: "1296" -bookCollection: "" -pageCount: 260 -documents: Doctrine\ORM\PersistentCollection {#7466 …} -favorites: Doctrine\ORM\PersistentCollection {#7501 …} } +label: "Standard" -typeAttributeCode: "type" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}}

ProductType

App\Twig\Components\ProductType

78.0 MiB

0.22 ms

Input props

[
  "product" => App\Entity\Product\Product {#7309
    #id: 9272
    #code: "IEEE00001971"
    #attributes: Doctrine\ORM\PersistentCollection {#7702 …}
    #variants: Doctrine\ORM\PersistentCollection {#7745 …}
    #options: Doctrine\ORM\PersistentCollection {#7917 …}
    #associations: Doctrine\ORM\PersistentCollection {#7901 …}
    #createdAt: DateTime @1751038125 {#7274
      date: 2025-06-27 17:28:45.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#7322
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7923 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7922
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7309}
        #id: 32097
        #name: "IEEE 1296:1987 (R1994)"
        #slug: "ieee-1296-1987-r1994-ieee00001971-240924"
        #description: """
          New IEEE Standard - Inactive-Withdrawn.<br />\n
          This standard describes a high-performance backplane bus intended for use in multiple processor systems. The bus incorporates synchronous, 32-bit multiplexed addreddata, with error detection and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of cost-effective high performance VLSI for the bus interface. The standard defines memory, I/O, message, and geographic address spaces. The memory space supports single and block transfers. The message space defines a high-level protocol for transferring blocks of data (messages) as multiple packets of data (small data bursts; e.g., 32 bytes in one microsecond) over the bus. This provides a highperformance (e.g., 32 megabytes/second) interprocessor communication transfers among many different processors on the bus. Error detection and retry is provided for messages. This message passing design also allows a VLSI implementation, such that virtually all modules on the bus will utilize the bus at its highest performance - 32 to 40 megabytes/second. The standard provides geographic addressing for ease of configurability, initialization, and diagnostics.<br />\n
          \t\t\t\t<br />\n
          This document defines the operation, functions, and attributes of the IEEE 1296 bus standard.<br />\n
          (1) This standard defines a high-performance 32-bit synchronous bus standard.<br />\n
          (2) The bus standard must have a design-in lifetime of 10 years with backward compatibility.<br />\n
          (3) The standard is intended for general purpose applications to optimize block transfers, including protocol for message passing. For real-time applications, the bus will provide a means of ensuring an upper limit to message delivery time.<br />\n
          (4) The standard is intended to be compatible with existing IEC [I], [2], [3] mechanical standards with recognition of the need for special front panels to address ESD, EMI, and RFI requirements.<br />\n
          (5) Options within the standard will be clearly identified.<br />\n
          (6) The standard is intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system.<br />\n
          (7) The standard is intended to support heterogeneous processor types in the same system.<br />\n
          (8) Message passing format and protocol is intended for future migration to a serial system bus.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for a High-Performance Synchronous 32-Bit Bus: MULTIBUS II"
        -notes: "Inactive-Withdrawn"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7535 …}
    #channels: Doctrine\ORM\PersistentCollection {#7629 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7308 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7614 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7646 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7422 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7420 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @586562400 {#7318
      date: 1988-08-03 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: DateTime @763858800 {#7316
      date: 1994-03-17 00:00:00.0 Europe/Paris (+01:00)
    }
    -canceledAt: DateTime @1010617200 {#7315
      date: 2002-01-10 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1296"
    -bookCollection: ""
    -pageCount: 260
    -documents: Doctrine\ORM\PersistentCollection {#7466 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7501 …}
  }
]

Attributes

[]

Component

App\Twig\Components\ProductType {#93202
  +product: App\Entity\Product\Product {#7309
    #id: 9272
    #code: "IEEE00001971"
    #attributes: Doctrine\ORM\PersistentCollection {#7702 …}
    #variants: Doctrine\ORM\PersistentCollection {#7745 …}
    #options: Doctrine\ORM\PersistentCollection {#7917 …}
    #associations: Doctrine\ORM\PersistentCollection {#7901 …}
    #createdAt: DateTime @1751038125 {#7274
      date: 2025-06-27 17:28:45.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#7322
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7923 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7922
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7309}
        #id: 32097
        #name: "IEEE 1296:1987 (R1994)"
        #slug: "ieee-1296-1987-r1994-ieee00001971-240924"
        #description: """
          New IEEE Standard - Inactive-Withdrawn.<br />\n
          This standard describes a high-performance backplane bus intended for use in multiple processor systems. The bus incorporates synchronous, 32-bit multiplexed addreddata, with error detection and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of cost-effective high performance VLSI for the bus interface. The standard defines memory, I/O, message, and geographic address spaces. The memory space supports single and block transfers. The message space defines a high-level protocol for transferring blocks of data (messages) as multiple packets of data (small data bursts; e.g., 32 bytes in one microsecond) over the bus. This provides a highperformance (e.g., 32 megabytes/second) interprocessor communication transfers among many different processors on the bus. Error detection and retry is provided for messages. This message passing design also allows a VLSI implementation, such that virtually all modules on the bus will utilize the bus at its highest performance - 32 to 40 megabytes/second. The standard provides geographic addressing for ease of configurability, initialization, and diagnostics.<br />\n
          \t\t\t\t<br />\n
          This document defines the operation, functions, and attributes of the IEEE 1296 bus standard.<br />\n
          (1) This standard defines a high-performance 32-bit synchronous bus standard.<br />\n
          (2) The bus standard must have a design-in lifetime of 10 years with backward compatibility.<br />\n
          (3) The standard is intended for general purpose applications to optimize block transfers, including protocol for message passing. For real-time applications, the bus will provide a means of ensuring an upper limit to message delivery time.<br />\n
          (4) The standard is intended to be compatible with existing IEC [I], [2], [3] mechanical standards with recognition of the need for special front panels to address ESD, EMI, and RFI requirements.<br />\n
          (5) Options within the standard will be clearly identified.<br />\n
          (6) The standard is intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system.<br />\n
          (7) The standard is intended to support heterogeneous processor types in the same system.<br />\n
          (8) Message passing format and protocol is intended for future migration to a serial system bus.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for a High-Performance Synchronous 32-Bit Bus: MULTIBUS II"
        -notes: "Inactive-Withdrawn"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7535 …}
    #channels: Doctrine\ORM\PersistentCollection {#7629 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7308 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7614 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7646 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7422 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7420 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @586562400 {#7318
      date: 1988-08-03 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: DateTime @763858800 {#7316
      date: 1994-03-17 00:00:00.0 Europe/Paris (+01:00)
    }
    -canceledAt: DateTime @1010617200 {#7315
      date: 2002-01-10 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1296"
    -bookCollection: ""
    -pageCount: 260
    -documents: Doctrine\ORM\PersistentCollection {#7466 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7501 …}
  }
  +label: "Standard"
  -typeAttributeCode: "type"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

ProductMostRecent	App\Twig\Components\ProductMostRecent	78.0 MiB	0.69 ms
Input props	["product" => App\Entity\Product\Product {#7309 #id: 9272 #code: "IEEE00001971" #attributes: Doctrine\ORM\PersistentCollection {#7702 …} #variants: Doctrine\ORM\PersistentCollection {#7745 …} #options: Doctrine\ORM\PersistentCollection {#7917 …} #associations: Doctrine\ORM\PersistentCollection {#7901 …} #createdAt: DateTime @1751038125 {#7274 date: 2025-06-27 17:28:45.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607004 {#7322 date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7923 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7922 #locale: "en_US" #translatable: App\Entity\Product\Product {#7309} #id: 32097 #name: "IEEE 1296:1987 (R1994)" #slug: "ieee-1296-1987-r1994-ieee00001971-240924" #description: """ New IEEE Standard - Inactive-Withdrawn.<br />\n This standard describes a high-performance backplane bus intended for use in multiple processor systems. The bus incorporates synchronous, 32-bit multiplexed addreddata, with error detection and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of cost-effective high performance VLSI for the bus interface. The standard defines memory, I/O, message, and geographic address spaces. The memory space supports single and block transfers. The message space defines a high-level protocol for transferring blocks of data (messages) as multiple packets of data (small data bursts; e.g., 32 bytes in one microsecond) over the bus. This provides a highperformance (e.g., 32 megabytes/second) interprocessor communication transfers among many different processors on the bus. Error detection and retry is provided for messages. This message passing design also allows a VLSI implementation, such that virtually all modules on the bus will utilize the bus at its highest performance - 32 to 40 megabytes/second. The standard provides geographic addressing for ease of configurability, initialization, and diagnostics.<br />\n \t\t\t\t<br />\n This document defines the operation, functions, and attributes of the IEEE 1296 bus standard.<br />\n (1) This standard defines a high-performance 32-bit synchronous bus standard.<br />\n (2) The bus standard must have a design-in lifetime of 10 years with backward compatibility.<br />\n (3) The standard is intended for general purpose applications to optimize block transfers, including protocol for message passing. For real-time applications, the bus will provide a means of ensuring an upper limit to message delivery time.<br />\n (4) The standard is intended to be compatible with existing IEC [I], [2], [3] mechanical standards with recognition of the need for special front panels to address ESD, EMI, and RFI requirements.<br />\n (5) Options within the standard will be clearly identified.<br />\n (6) The standard is intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system.<br />\n (7) The standard is intended to support heterogeneous processor types in the same system.<br />\n (8) Message passing format and protocol is intended for future migration to a serial system bus. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for a High-Performance Synchronous 32-Bit Bus: MULTIBUS II" -notes: "Inactive-Withdrawn" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7535 …} #channels: Doctrine\ORM\PersistentCollection {#7629 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7308 …} #reviews: Doctrine\ORM\PersistentCollection {#7614 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7646 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7422 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7420 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @586562400 {#7318 date: 1988-08-03 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: DateTime @763858800 {#7316 date: 1994-03-17 00:00:00.0 Europe/Paris (+01:00) } -canceledAt: DateTime @1010617200 {#7315 date: 2002-01-10 00:00:00.0 Europe/Paris (+01:00) } -edition: null -coreDocument: "1296" -bookCollection: "" -pageCount: 260 -documents: Doctrine\ORM\PersistentCollection {#7466 …} -favorites: Doctrine\ORM\PersistentCollection {#7501 …} }]
Attributes	[]
Component	App\Twig\Components\ProductMostRecent {#93277+product: App\Entity\Product\Product {#7309 #id: 9272 #code: "IEEE00001971" #attributes: Doctrine\ORM\PersistentCollection {#7702 …} #variants: Doctrine\ORM\PersistentCollection {#7745 …} #options: Doctrine\ORM\PersistentCollection {#7917 …} #associations: Doctrine\ORM\PersistentCollection {#7901 …} #createdAt: DateTime @1751038125 {#7274 date: 2025-06-27 17:28:45.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607004 {#7322 date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7923 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7922 #locale: "en_US" #translatable: App\Entity\Product\Product {#7309} #id: 32097 #name: "IEEE 1296:1987 (R1994)" #slug: "ieee-1296-1987-r1994-ieee00001971-240924" #description: """ New IEEE Standard - Inactive-Withdrawn.<br />\n This standard describes a high-performance backplane bus intended for use in multiple processor systems. The bus incorporates synchronous, 32-bit multiplexed addreddata, with error detection and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of cost-effective high performance VLSI for the bus interface. The standard defines memory, I/O, message, and geographic address spaces. The memory space supports single and block transfers. The message space defines a high-level protocol for transferring blocks of data (messages) as multiple packets of data (small data bursts; e.g., 32 bytes in one microsecond) over the bus. This provides a highperformance (e.g., 32 megabytes/second) interprocessor communication transfers among many different processors on the bus. Error detection and retry is provided for messages. This message passing design also allows a VLSI implementation, such that virtually all modules on the bus will utilize the bus at its highest performance - 32 to 40 megabytes/second. The standard provides geographic addressing for ease of configurability, initialization, and diagnostics.<br />\n \t\t\t\t<br />\n This document defines the operation, functions, and attributes of the IEEE 1296 bus standard.<br />\n (1) This standard defines a high-performance 32-bit synchronous bus standard.<br />\n (2) The bus standard must have a design-in lifetime of 10 years with backward compatibility.<br />\n (3) The standard is intended for general purpose applications to optimize block transfers, including protocol for message passing. For real-time applications, the bus will provide a means of ensuring an upper limit to message delivery time.<br />\n (4) The standard is intended to be compatible with existing IEC [I], [2], [3] mechanical standards with recognition of the need for special front panels to address ESD, EMI, and RFI requirements.<br />\n (5) Options within the standard will be clearly identified.<br />\n (6) The standard is intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system.<br />\n (7) The standard is intended to support heterogeneous processor types in the same system.<br />\n (8) Message passing format and protocol is intended for future migration to a serial system bus. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for a High-Performance Synchronous 32-Bit Bus: MULTIBUS II" -notes: "Inactive-Withdrawn" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7535 …} #channels: Doctrine\ORM\PersistentCollection {#7629 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7308 …} #reviews: Doctrine\ORM\PersistentCollection {#7614 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7646 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7422 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7420 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @586562400 {#7318 date: 1988-08-03 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: DateTime @763858800 {#7316 date: 1994-03-17 00:00:00.0 Europe/Paris (+01:00) } -canceledAt: DateTime @1010617200 {#7315 date: 2002-01-10 00:00:00.0 Europe/Paris (+01:00) } -edition: null -coreDocument: "1296" -bookCollection: "" -pageCount: 260 -documents: Doctrine\ORM\PersistentCollection {#7466 …} -favorites: Doctrine\ORM\PersistentCollection {#7501 …} } +label: "Most Recent" +icon: "check-xs" -mostRecentAttributeCode: "most_recent" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}}

ProductMostRecent

App\Twig\Components\ProductMostRecent

78.0 MiB

0.69 ms

Input props

[
  "product" => App\Entity\Product\Product {#7309
    #id: 9272
    #code: "IEEE00001971"
    #attributes: Doctrine\ORM\PersistentCollection {#7702 …}
    #variants: Doctrine\ORM\PersistentCollection {#7745 …}
    #options: Doctrine\ORM\PersistentCollection {#7917 …}
    #associations: Doctrine\ORM\PersistentCollection {#7901 …}
    #createdAt: DateTime @1751038125 {#7274
      date: 2025-06-27 17:28:45.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#7322
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7923 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7922
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7309}
        #id: 32097
        #name: "IEEE 1296:1987 (R1994)"
        #slug: "ieee-1296-1987-r1994-ieee00001971-240924"
        #description: """
          New IEEE Standard - Inactive-Withdrawn.<br />\n
          This standard describes a high-performance backplane bus intended for use in multiple processor systems. The bus incorporates synchronous, 32-bit multiplexed addreddata, with error detection and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of cost-effective high performance VLSI for the bus interface. The standard defines memory, I/O, message, and geographic address spaces. The memory space supports single and block transfers. The message space defines a high-level protocol for transferring blocks of data (messages) as multiple packets of data (small data bursts; e.g., 32 bytes in one microsecond) over the bus. This provides a highperformance (e.g., 32 megabytes/second) interprocessor communication transfers among many different processors on the bus. Error detection and retry is provided for messages. This message passing design also allows a VLSI implementation, such that virtually all modules on the bus will utilize the bus at its highest performance - 32 to 40 megabytes/second. The standard provides geographic addressing for ease of configurability, initialization, and diagnostics.<br />\n
          \t\t\t\t<br />\n
          This document defines the operation, functions, and attributes of the IEEE 1296 bus standard.<br />\n
          (1) This standard defines a high-performance 32-bit synchronous bus standard.<br />\n
          (2) The bus standard must have a design-in lifetime of 10 years with backward compatibility.<br />\n
          (3) The standard is intended for general purpose applications to optimize block transfers, including protocol for message passing. For real-time applications, the bus will provide a means of ensuring an upper limit to message delivery time.<br />\n
          (4) The standard is intended to be compatible with existing IEC [I], [2], [3] mechanical standards with recognition of the need for special front panels to address ESD, EMI, and RFI requirements.<br />\n
          (5) Options within the standard will be clearly identified.<br />\n
          (6) The standard is intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system.<br />\n
          (7) The standard is intended to support heterogeneous processor types in the same system.<br />\n
          (8) Message passing format and protocol is intended for future migration to a serial system bus.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for a High-Performance Synchronous 32-Bit Bus: MULTIBUS II"
        -notes: "Inactive-Withdrawn"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7535 …}
    #channels: Doctrine\ORM\PersistentCollection {#7629 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7308 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7614 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7646 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7422 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7420 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @586562400 {#7318
      date: 1988-08-03 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: DateTime @763858800 {#7316
      date: 1994-03-17 00:00:00.0 Europe/Paris (+01:00)
    }
    -canceledAt: DateTime @1010617200 {#7315
      date: 2002-01-10 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1296"
    -bookCollection: ""
    -pageCount: 260
    -documents: Doctrine\ORM\PersistentCollection {#7466 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7501 …}
  }
]

Attributes

[]

Component

App\Twig\Components\ProductMostRecent {#93277
  +product: App\Entity\Product\Product {#7309
    #id: 9272
    #code: "IEEE00001971"
    #attributes: Doctrine\ORM\PersistentCollection {#7702 …}
    #variants: Doctrine\ORM\PersistentCollection {#7745 …}
    #options: Doctrine\ORM\PersistentCollection {#7917 …}
    #associations: Doctrine\ORM\PersistentCollection {#7901 …}
    #createdAt: DateTime @1751038125 {#7274
      date: 2025-06-27 17:28:45.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#7322
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7923 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7922
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7309}
        #id: 32097
        #name: "IEEE 1296:1987 (R1994)"
        #slug: "ieee-1296-1987-r1994-ieee00001971-240924"
        #description: """
          New IEEE Standard - Inactive-Withdrawn.<br />\n
          This standard describes a high-performance backplane bus intended for use in multiple processor systems. The bus incorporates synchronous, 32-bit multiplexed addreddata, with error detection and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of cost-effective high performance VLSI for the bus interface. The standard defines memory, I/O, message, and geographic address spaces. The memory space supports single and block transfers. The message space defines a high-level protocol for transferring blocks of data (messages) as multiple packets of data (small data bursts; e.g., 32 bytes in one microsecond) over the bus. This provides a highperformance (e.g., 32 megabytes/second) interprocessor communication transfers among many different processors on the bus. Error detection and retry is provided for messages. This message passing design also allows a VLSI implementation, such that virtually all modules on the bus will utilize the bus at its highest performance - 32 to 40 megabytes/second. The standard provides geographic addressing for ease of configurability, initialization, and diagnostics.<br />\n
          \t\t\t\t<br />\n
          This document defines the operation, functions, and attributes of the IEEE 1296 bus standard.<br />\n
          (1) This standard defines a high-performance 32-bit synchronous bus standard.<br />\n
          (2) The bus standard must have a design-in lifetime of 10 years with backward compatibility.<br />\n
          (3) The standard is intended for general purpose applications to optimize block transfers, including protocol for message passing. For real-time applications, the bus will provide a means of ensuring an upper limit to message delivery time.<br />\n
          (4) The standard is intended to be compatible with existing IEC [I], [2], [3] mechanical standards with recognition of the need for special front panels to address ESD, EMI, and RFI requirements.<br />\n
          (5) Options within the standard will be clearly identified.<br />\n
          (6) The standard is intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system.<br />\n
          (7) The standard is intended to support heterogeneous processor types in the same system.<br />\n
          (8) Message passing format and protocol is intended for future migration to a serial system bus.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for a High-Performance Synchronous 32-Bit Bus: MULTIBUS II"
        -notes: "Inactive-Withdrawn"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7535 …}
    #channels: Doctrine\ORM\PersistentCollection {#7629 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7308 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7614 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7646 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7422 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7420 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @586562400 {#7318
      date: 1988-08-03 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: DateTime @763858800 {#7316
      date: 1994-03-17 00:00:00.0 Europe/Paris (+01:00)
    }
    -canceledAt: DateTime @1010617200 {#7315
      date: 2002-01-10 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1296"
    -bookCollection: ""
    -pageCount: 260
    -documents: Doctrine\ORM\PersistentCollection {#7466 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7501 …}
  }
  +label: "Most Recent"
  +icon: "check-xs"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

ProductState	App\Twig\Components\ProductState	78.0 MiB	0.21 ms
Input props	["product" => App\Entity\Product\Product {#7309 #id: 9272 #code: "IEEE00001971" #attributes: Doctrine\ORM\PersistentCollection {#7702 …} #variants: Doctrine\ORM\PersistentCollection {#7745 …} #options: Doctrine\ORM\PersistentCollection {#7917 …} #associations: Doctrine\ORM\PersistentCollection {#7901 …} #createdAt: DateTime @1751038125 {#7274 date: 2025-06-27 17:28:45.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607004 {#7322 date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7923 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7922 #locale: "en_US" #translatable: App\Entity\Product\Product {#7309} #id: 32097 #name: "IEEE 1296:1987 (R1994)" #slug: "ieee-1296-1987-r1994-ieee00001971-240924" #description: """ New IEEE Standard - Inactive-Withdrawn.<br />\n This standard describes a high-performance backplane bus intended for use in multiple processor systems. The bus incorporates synchronous, 32-bit multiplexed addreddata, with error detection and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of cost-effective high performance VLSI for the bus interface. The standard defines memory, I/O, message, and geographic address spaces. The memory space supports single and block transfers. The message space defines a high-level protocol for transferring blocks of data (messages) as multiple packets of data (small data bursts; e.g., 32 bytes in one microsecond) over the bus. This provides a highperformance (e.g., 32 megabytes/second) interprocessor communication transfers among many different processors on the bus. Error detection and retry is provided for messages. This message passing design also allows a VLSI implementation, such that virtually all modules on the bus will utilize the bus at its highest performance - 32 to 40 megabytes/second. The standard provides geographic addressing for ease of configurability, initialization, and diagnostics.<br />\n \t\t\t\t<br />\n This document defines the operation, functions, and attributes of the IEEE 1296 bus standard.<br />\n (1) This standard defines a high-performance 32-bit synchronous bus standard.<br />\n (2) The bus standard must have a design-in lifetime of 10 years with backward compatibility.<br />\n (3) The standard is intended for general purpose applications to optimize block transfers, including protocol for message passing. For real-time applications, the bus will provide a means of ensuring an upper limit to message delivery time.<br />\n (4) The standard is intended to be compatible with existing IEC [I], [2], [3] mechanical standards with recognition of the need for special front panels to address ESD, EMI, and RFI requirements.<br />\n (5) Options within the standard will be clearly identified.<br />\n (6) The standard is intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system.<br />\n (7) The standard is intended to support heterogeneous processor types in the same system.<br />\n (8) Message passing format and protocol is intended for future migration to a serial system bus. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for a High-Performance Synchronous 32-Bit Bus: MULTIBUS II" -notes: "Inactive-Withdrawn" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7535 …} #channels: Doctrine\ORM\PersistentCollection {#7629 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7308 …} #reviews: Doctrine\ORM\PersistentCollection {#7614 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7646 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7422 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7420 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @586562400 {#7318 date: 1988-08-03 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: DateTime @763858800 {#7316 date: 1994-03-17 00:00:00.0 Europe/Paris (+01:00) } -canceledAt: DateTime @1010617200 {#7315 date: 2002-01-10 00:00:00.0 Europe/Paris (+01:00) } -edition: null -coreDocument: "1296" -bookCollection: "" -pageCount: 260 -documents: Doctrine\ORM\PersistentCollection {#7466 …} -favorites: Doctrine\ORM\PersistentCollection {#7501 …} } "showFullLabel" => "true"]
Attributes	[`"showFullLabel" => "true"`]
Component	App\Twig\Components\ProductState {#100206+product: App\Entity\Product\Product {#7309 #id: 9272 #code: "IEEE00001971" #attributes: Doctrine\ORM\PersistentCollection {#7702 …} #variants: Doctrine\ORM\PersistentCollection {#7745 …} #options: Doctrine\ORM\PersistentCollection {#7917 …} #associations: Doctrine\ORM\PersistentCollection {#7901 …} #createdAt: DateTime @1751038125 {#7274 date: 2025-06-27 17:28:45.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607004 {#7322 date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7923 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7922 #locale: "en_US" #translatable: App\Entity\Product\Product {#7309} #id: 32097 #name: "IEEE 1296:1987 (R1994)" #slug: "ieee-1296-1987-r1994-ieee00001971-240924" #description: """ New IEEE Standard - Inactive-Withdrawn.<br />\n This standard describes a high-performance backplane bus intended for use in multiple processor systems. The bus incorporates synchronous, 32-bit multiplexed addreddata, with error detection and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of cost-effective high performance VLSI for the bus interface. The standard defines memory, I/O, message, and geographic address spaces. The memory space supports single and block transfers. The message space defines a high-level protocol for transferring blocks of data (messages) as multiple packets of data (small data bursts; e.g., 32 bytes in one microsecond) over the bus. This provides a highperformance (e.g., 32 megabytes/second) interprocessor communication transfers among many different processors on the bus. Error detection and retry is provided for messages. This message passing design also allows a VLSI implementation, such that virtually all modules on the bus will utilize the bus at its highest performance - 32 to 40 megabytes/second. The standard provides geographic addressing for ease of configurability, initialization, and diagnostics.<br />\n \t\t\t\t<br />\n This document defines the operation, functions, and attributes of the IEEE 1296 bus standard.<br />\n (1) This standard defines a high-performance 32-bit synchronous bus standard.<br />\n (2) The bus standard must have a design-in lifetime of 10 years with backward compatibility.<br />\n (3) The standard is intended for general purpose applications to optimize block transfers, including protocol for message passing. For real-time applications, the bus will provide a means of ensuring an upper limit to message delivery time.<br />\n (4) The standard is intended to be compatible with existing IEC [I], [2], [3] mechanical standards with recognition of the need for special front panels to address ESD, EMI, and RFI requirements.<br />\n (5) Options within the standard will be clearly identified.<br />\n (6) The standard is intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system.<br />\n (7) The standard is intended to support heterogeneous processor types in the same system.<br />\n (8) Message passing format and protocol is intended for future migration to a serial system bus. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for a High-Performance Synchronous 32-Bit Bus: MULTIBUS II" -notes: "Inactive-Withdrawn" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7535 …} #channels: Doctrine\ORM\PersistentCollection {#7629 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7308 …} #reviews: Doctrine\ORM\PersistentCollection {#7614 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7646 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7422 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7420 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @586562400 {#7318 date: 1988-08-03 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: DateTime @763858800 {#7316 date: 1994-03-17 00:00:00.0 Europe/Paris (+01:00) } -canceledAt: DateTime @1010617200 {#7315 date: 2002-01-10 00:00:00.0 Europe/Paris (+01:00) } -edition: null -coreDocument: "1296" -bookCollection: "" -pageCount: 260 -documents: Doctrine\ORM\PersistentCollection {#7466 …} -favorites: Doctrine\ORM\PersistentCollection {#7501 …} } +appearance: "state-withdrawn" +labels: [ "Withdrawn" "Confirmed" ] -stateAttributeCode: "state" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}}

ProductState

App\Twig\Components\ProductState

78.0 MiB

0.21 ms

Input props

[
  "product" => App\Entity\Product\Product {#7309
    #id: 9272
    #code: "IEEE00001971"
    #attributes: Doctrine\ORM\PersistentCollection {#7702 …}
    #variants: Doctrine\ORM\PersistentCollection {#7745 …}
    #options: Doctrine\ORM\PersistentCollection {#7917 …}
    #associations: Doctrine\ORM\PersistentCollection {#7901 …}
    #createdAt: DateTime @1751038125 {#7274
      date: 2025-06-27 17:28:45.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#7322
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7923 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7922
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7309}
        #id: 32097
        #name: "IEEE 1296:1987 (R1994)"
        #slug: "ieee-1296-1987-r1994-ieee00001971-240924"
        #description: """
          New IEEE Standard - Inactive-Withdrawn.<br />\n
          This standard describes a high-performance backplane bus intended for use in multiple processor systems. The bus incorporates synchronous, 32-bit multiplexed addreddata, with error detection and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of cost-effective high performance VLSI for the bus interface. The standard defines memory, I/O, message, and geographic address spaces. The memory space supports single and block transfers. The message space defines a high-level protocol for transferring blocks of data (messages) as multiple packets of data (small data bursts; e.g., 32 bytes in one microsecond) over the bus. This provides a highperformance (e.g., 32 megabytes/second) interprocessor communication transfers among many different processors on the bus. Error detection and retry is provided for messages. This message passing design also allows a VLSI implementation, such that virtually all modules on the bus will utilize the bus at its highest performance - 32 to 40 megabytes/second. The standard provides geographic addressing for ease of configurability, initialization, and diagnostics.<br />\n
          \t\t\t\t<br />\n
          This document defines the operation, functions, and attributes of the IEEE 1296 bus standard.<br />\n
          (1) This standard defines a high-performance 32-bit synchronous bus standard.<br />\n
          (2) The bus standard must have a design-in lifetime of 10 years with backward compatibility.<br />\n
          (3) The standard is intended for general purpose applications to optimize block transfers, including protocol for message passing. For real-time applications, the bus will provide a means of ensuring an upper limit to message delivery time.<br />\n
          (4) The standard is intended to be compatible with existing IEC [I], [2], [3] mechanical standards with recognition of the need for special front panels to address ESD, EMI, and RFI requirements.<br />\n
          (5) Options within the standard will be clearly identified.<br />\n
          (6) The standard is intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system.<br />\n
          (7) The standard is intended to support heterogeneous processor types in the same system.<br />\n
          (8) Message passing format and protocol is intended for future migration to a serial system bus.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for a High-Performance Synchronous 32-Bit Bus: MULTIBUS II"
        -notes: "Inactive-Withdrawn"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7535 …}
    #channels: Doctrine\ORM\PersistentCollection {#7629 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7308 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7614 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7646 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7422 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7420 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @586562400 {#7318
      date: 1988-08-03 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: DateTime @763858800 {#7316
      date: 1994-03-17 00:00:00.0 Europe/Paris (+01:00)
    }
    -canceledAt: DateTime @1010617200 {#7315
      date: 2002-01-10 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1296"
    -bookCollection: ""
    -pageCount: 260
    -documents: Doctrine\ORM\PersistentCollection {#7466 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7501 …}
  }
  "showFullLabel" => "true"
]

Attributes

[
  "showFullLabel" => "true"
]

Component

App\Twig\Components\ProductState {#100206
  +product: App\Entity\Product\Product {#7309
    #id: 9272
    #code: "IEEE00001971"
    #attributes: Doctrine\ORM\PersistentCollection {#7702 …}
    #variants: Doctrine\ORM\PersistentCollection {#7745 …}
    #options: Doctrine\ORM\PersistentCollection {#7917 …}
    #associations: Doctrine\ORM\PersistentCollection {#7901 …}
    #createdAt: DateTime @1751038125 {#7274
      date: 2025-06-27 17:28:45.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#7322
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7923 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7922
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7309}
        #id: 32097
        #name: "IEEE 1296:1987 (R1994)"
        #slug: "ieee-1296-1987-r1994-ieee00001971-240924"
        #description: """
          New IEEE Standard - Inactive-Withdrawn.<br />\n
          This standard describes a high-performance backplane bus intended for use in multiple processor systems. The bus incorporates synchronous, 32-bit multiplexed addreddata, with error detection and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of cost-effective high performance VLSI for the bus interface. The standard defines memory, I/O, message, and geographic address spaces. The memory space supports single and block transfers. The message space defines a high-level protocol for transferring blocks of data (messages) as multiple packets of data (small data bursts; e.g., 32 bytes in one microsecond) over the bus. This provides a highperformance (e.g., 32 megabytes/second) interprocessor communication transfers among many different processors on the bus. Error detection and retry is provided for messages. This message passing design also allows a VLSI implementation, such that virtually all modules on the bus will utilize the bus at its highest performance - 32 to 40 megabytes/second. The standard provides geographic addressing for ease of configurability, initialization, and diagnostics.<br />\n
          \t\t\t\t<br />\n
          This document defines the operation, functions, and attributes of the IEEE 1296 bus standard.<br />\n
          (1) This standard defines a high-performance 32-bit synchronous bus standard.<br />\n
          (2) The bus standard must have a design-in lifetime of 10 years with backward compatibility.<br />\n
          (3) The standard is intended for general purpose applications to optimize block transfers, including protocol for message passing. For real-time applications, the bus will provide a means of ensuring an upper limit to message delivery time.<br />\n
          (4) The standard is intended to be compatible with existing IEC [I], [2], [3] mechanical standards with recognition of the need for special front panels to address ESD, EMI, and RFI requirements.<br />\n
          (5) Options within the standard will be clearly identified.<br />\n
          (6) The standard is intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system.<br />\n
          (7) The standard is intended to support heterogeneous processor types in the same system.<br />\n
          (8) Message passing format and protocol is intended for future migration to a serial system bus.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for a High-Performance Synchronous 32-Bit Bus: MULTIBUS II"
        -notes: "Inactive-Withdrawn"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7535 …}
    #channels: Doctrine\ORM\PersistentCollection {#7629 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7308 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7614 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7646 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7422 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7420 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @586562400 {#7318
      date: 1988-08-03 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: DateTime @763858800 {#7316
      date: 1994-03-17 00:00:00.0 Europe/Paris (+01:00)
    }
    -canceledAt: DateTime @1010617200 {#7315
      date: 2002-01-10 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1296"
    -bookCollection: ""
    -pageCount: 260
    -documents: Doctrine\ORM\PersistentCollection {#7466 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7501 …}
  }
  +appearance: "state-withdrawn"
  +labels: [
    "Withdrawn"
    "Confirmed"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

ProductMostRecent	App\Twig\Components\ProductMostRecent	78.0 MiB	0.86 ms
Input props	["product" => App\Entity\Product\Product {#7309 #id: 9272 #code: "IEEE00001971" #attributes: Doctrine\ORM\PersistentCollection {#7702 …} #variants: Doctrine\ORM\PersistentCollection {#7745 …} #options: Doctrine\ORM\PersistentCollection {#7917 …} #associations: Doctrine\ORM\PersistentCollection {#7901 …} #createdAt: DateTime @1751038125 {#7274 date: 2025-06-27 17:28:45.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607004 {#7322 date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7923 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7922 #locale: "en_US" #translatable: App\Entity\Product\Product {#7309} #id: 32097 #name: "IEEE 1296:1987 (R1994)" #slug: "ieee-1296-1987-r1994-ieee00001971-240924" #description: """ New IEEE Standard - Inactive-Withdrawn.<br />\n This standard describes a high-performance backplane bus intended for use in multiple processor systems. The bus incorporates synchronous, 32-bit multiplexed addreddata, with error detection and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of cost-effective high performance VLSI for the bus interface. The standard defines memory, I/O, message, and geographic address spaces. The memory space supports single and block transfers. The message space defines a high-level protocol for transferring blocks of data (messages) as multiple packets of data (small data bursts; e.g., 32 bytes in one microsecond) over the bus. This provides a highperformance (e.g., 32 megabytes/second) interprocessor communication transfers among many different processors on the bus. Error detection and retry is provided for messages. This message passing design also allows a VLSI implementation, such that virtually all modules on the bus will utilize the bus at its highest performance - 32 to 40 megabytes/second. The standard provides geographic addressing for ease of configurability, initialization, and diagnostics.<br />\n \t\t\t\t<br />\n This document defines the operation, functions, and attributes of the IEEE 1296 bus standard.<br />\n (1) This standard defines a high-performance 32-bit synchronous bus standard.<br />\n (2) The bus standard must have a design-in lifetime of 10 years with backward compatibility.<br />\n (3) The standard is intended for general purpose applications to optimize block transfers, including protocol for message passing. For real-time applications, the bus will provide a means of ensuring an upper limit to message delivery time.<br />\n (4) The standard is intended to be compatible with existing IEC [I], [2], [3] mechanical standards with recognition of the need for special front panels to address ESD, EMI, and RFI requirements.<br />\n (5) Options within the standard will be clearly identified.<br />\n (6) The standard is intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system.<br />\n (7) The standard is intended to support heterogeneous processor types in the same system.<br />\n (8) Message passing format and protocol is intended for future migration to a serial system bus. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for a High-Performance Synchronous 32-Bit Bus: MULTIBUS II" -notes: "Inactive-Withdrawn" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7535 …} #channels: Doctrine\ORM\PersistentCollection {#7629 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7308 …} #reviews: Doctrine\ORM\PersistentCollection {#7614 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7646 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7422 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7420 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @586562400 {#7318 date: 1988-08-03 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: DateTime @763858800 {#7316 date: 1994-03-17 00:00:00.0 Europe/Paris (+01:00) } -canceledAt: DateTime @1010617200 {#7315 date: 2002-01-10 00:00:00.0 Europe/Paris (+01:00) } -edition: null -coreDocument: "1296" -bookCollection: "" -pageCount: 260 -documents: Doctrine\ORM\PersistentCollection {#7466 …} -favorites: Doctrine\ORM\PersistentCollection {#7501 …} }]
Attributes	[]
Component	App\Twig\Components\ProductMostRecent {#100290+product: App\Entity\Product\Product {#7309 #id: 9272 #code: "IEEE00001971" #attributes: Doctrine\ORM\PersistentCollection {#7702 …} #variants: Doctrine\ORM\PersistentCollection {#7745 …} #options: Doctrine\ORM\PersistentCollection {#7917 …} #associations: Doctrine\ORM\PersistentCollection {#7901 …} #createdAt: DateTime @1751038125 {#7274 date: 2025-06-27 17:28:45.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607004 {#7322 date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7923 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7922 #locale: "en_US" #translatable: App\Entity\Product\Product {#7309} #id: 32097 #name: "IEEE 1296:1987 (R1994)" #slug: "ieee-1296-1987-r1994-ieee00001971-240924" #description: """ New IEEE Standard - Inactive-Withdrawn.<br />\n This standard describes a high-performance backplane bus intended for use in multiple processor systems. The bus incorporates synchronous, 32-bit multiplexed addreddata, with error detection and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of cost-effective high performance VLSI for the bus interface. The standard defines memory, I/O, message, and geographic address spaces. The memory space supports single and block transfers. The message space defines a high-level protocol for transferring blocks of data (messages) as multiple packets of data (small data bursts; e.g., 32 bytes in one microsecond) over the bus. This provides a highperformance (e.g., 32 megabytes/second) interprocessor communication transfers among many different processors on the bus. Error detection and retry is provided for messages. This message passing design also allows a VLSI implementation, such that virtually all modules on the bus will utilize the bus at its highest performance - 32 to 40 megabytes/second. The standard provides geographic addressing for ease of configurability, initialization, and diagnostics.<br />\n \t\t\t\t<br />\n This document defines the operation, functions, and attributes of the IEEE 1296 bus standard.<br />\n (1) This standard defines a high-performance 32-bit synchronous bus standard.<br />\n (2) The bus standard must have a design-in lifetime of 10 years with backward compatibility.<br />\n (3) The standard is intended for general purpose applications to optimize block transfers, including protocol for message passing. For real-time applications, the bus will provide a means of ensuring an upper limit to message delivery time.<br />\n (4) The standard is intended to be compatible with existing IEC [I], [2], [3] mechanical standards with recognition of the need for special front panels to address ESD, EMI, and RFI requirements.<br />\n (5) Options within the standard will be clearly identified.<br />\n (6) The standard is intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system.<br />\n (7) The standard is intended to support heterogeneous processor types in the same system.<br />\n (8) Message passing format and protocol is intended for future migration to a serial system bus. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for a High-Performance Synchronous 32-Bit Bus: MULTIBUS II" -notes: "Inactive-Withdrawn" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7535 …} #channels: Doctrine\ORM\PersistentCollection {#7629 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7308 …} #reviews: Doctrine\ORM\PersistentCollection {#7614 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7646 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7422 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7420 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @586562400 {#7318 date: 1988-08-03 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: DateTime @763858800 {#7316 date: 1994-03-17 00:00:00.0 Europe/Paris (+01:00) } -canceledAt: DateTime @1010617200 {#7315 date: 2002-01-10 00:00:00.0 Europe/Paris (+01:00) } -edition: null -coreDocument: "1296" -bookCollection: "" -pageCount: 260 -documents: Doctrine\ORM\PersistentCollection {#7466 …} -favorites: Doctrine\ORM\PersistentCollection {#7501 …} } +label: "Most Recent" +icon: "check-xs" -mostRecentAttributeCode: "most_recent" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}}

ProductMostRecent

App\Twig\Components\ProductMostRecent

78.0 MiB

0.86 ms

Input props

[
  "product" => App\Entity\Product\Product {#7309
    #id: 9272
    #code: "IEEE00001971"
    #attributes: Doctrine\ORM\PersistentCollection {#7702 …}
    #variants: Doctrine\ORM\PersistentCollection {#7745 …}
    #options: Doctrine\ORM\PersistentCollection {#7917 …}
    #associations: Doctrine\ORM\PersistentCollection {#7901 …}
    #createdAt: DateTime @1751038125 {#7274
      date: 2025-06-27 17:28:45.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#7322
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7923 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7922
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7309}
        #id: 32097
        #name: "IEEE 1296:1987 (R1994)"
        #slug: "ieee-1296-1987-r1994-ieee00001971-240924"
        #description: """
          New IEEE Standard - Inactive-Withdrawn.<br />\n
          This standard describes a high-performance backplane bus intended for use in multiple processor systems. The bus incorporates synchronous, 32-bit multiplexed addreddata, with error detection and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of cost-effective high performance VLSI for the bus interface. The standard defines memory, I/O, message, and geographic address spaces. The memory space supports single and block transfers. The message space defines a high-level protocol for transferring blocks of data (messages) as multiple packets of data (small data bursts; e.g., 32 bytes in one microsecond) over the bus. This provides a highperformance (e.g., 32 megabytes/second) interprocessor communication transfers among many different processors on the bus. Error detection and retry is provided for messages. This message passing design also allows a VLSI implementation, such that virtually all modules on the bus will utilize the bus at its highest performance - 32 to 40 megabytes/second. The standard provides geographic addressing for ease of configurability, initialization, and diagnostics.<br />\n
          \t\t\t\t<br />\n
          This document defines the operation, functions, and attributes of the IEEE 1296 bus standard.<br />\n
          (1) This standard defines a high-performance 32-bit synchronous bus standard.<br />\n
          (2) The bus standard must have a design-in lifetime of 10 years with backward compatibility.<br />\n
          (3) The standard is intended for general purpose applications to optimize block transfers, including protocol for message passing. For real-time applications, the bus will provide a means of ensuring an upper limit to message delivery time.<br />\n
          (4) The standard is intended to be compatible with existing IEC [I], [2], [3] mechanical standards with recognition of the need for special front panels to address ESD, EMI, and RFI requirements.<br />\n
          (5) Options within the standard will be clearly identified.<br />\n
          (6) The standard is intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system.<br />\n
          (7) The standard is intended to support heterogeneous processor types in the same system.<br />\n
          (8) Message passing format and protocol is intended for future migration to a serial system bus.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for a High-Performance Synchronous 32-Bit Bus: MULTIBUS II"
        -notes: "Inactive-Withdrawn"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7535 …}
    #channels: Doctrine\ORM\PersistentCollection {#7629 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7308 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7614 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7646 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7422 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7420 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @586562400 {#7318
      date: 1988-08-03 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: DateTime @763858800 {#7316
      date: 1994-03-17 00:00:00.0 Europe/Paris (+01:00)
    }
    -canceledAt: DateTime @1010617200 {#7315
      date: 2002-01-10 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1296"
    -bookCollection: ""
    -pageCount: 260
    -documents: Doctrine\ORM\PersistentCollection {#7466 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7501 …}
  }
]

Attributes

[]

Component

App\Twig\Components\ProductMostRecent {#100290
  +product: App\Entity\Product\Product {#7309
    #id: 9272
    #code: "IEEE00001971"
    #attributes: Doctrine\ORM\PersistentCollection {#7702 …}
    #variants: Doctrine\ORM\PersistentCollection {#7745 …}
    #options: Doctrine\ORM\PersistentCollection {#7917 …}
    #associations: Doctrine\ORM\PersistentCollection {#7901 …}
    #createdAt: DateTime @1751038125 {#7274
      date: 2025-06-27 17:28:45.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#7322
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7923 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7922
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7309}
        #id: 32097
        #name: "IEEE 1296:1987 (R1994)"
        #slug: "ieee-1296-1987-r1994-ieee00001971-240924"
        #description: """
          New IEEE Standard - Inactive-Withdrawn.<br />\n
          This standard describes a high-performance backplane bus intended for use in multiple processor systems. The bus incorporates synchronous, 32-bit multiplexed addreddata, with error detection and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of cost-effective high performance VLSI for the bus interface. The standard defines memory, I/O, message, and geographic address spaces. The memory space supports single and block transfers. The message space defines a high-level protocol for transferring blocks of data (messages) as multiple packets of data (small data bursts; e.g., 32 bytes in one microsecond) over the bus. This provides a highperformance (e.g., 32 megabytes/second) interprocessor communication transfers among many different processors on the bus. Error detection and retry is provided for messages. This message passing design also allows a VLSI implementation, such that virtually all modules on the bus will utilize the bus at its highest performance - 32 to 40 megabytes/second. The standard provides geographic addressing for ease of configurability, initialization, and diagnostics.<br />\n
          \t\t\t\t<br />\n
          This document defines the operation, functions, and attributes of the IEEE 1296 bus standard.<br />\n
          (1) This standard defines a high-performance 32-bit synchronous bus standard.<br />\n
          (2) The bus standard must have a design-in lifetime of 10 years with backward compatibility.<br />\n
          (3) The standard is intended for general purpose applications to optimize block transfers, including protocol for message passing. For real-time applications, the bus will provide a means of ensuring an upper limit to message delivery time.<br />\n
          (4) The standard is intended to be compatible with existing IEC [I], [2], [3] mechanical standards with recognition of the need for special front panels to address ESD, EMI, and RFI requirements.<br />\n
          (5) Options within the standard will be clearly identified.<br />\n
          (6) The standard is intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system.<br />\n
          (7) The standard is intended to support heterogeneous processor types in the same system.<br />\n
          (8) Message passing format and protocol is intended for future migration to a serial system bus.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for a High-Performance Synchronous 32-Bit Bus: MULTIBUS II"
        -notes: "Inactive-Withdrawn"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7535 …}
    #channels: Doctrine\ORM\PersistentCollection {#7629 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7308 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7614 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7646 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7422 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7420 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @586562400 {#7318
      date: 1988-08-03 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: DateTime @763858800 {#7316
      date: 1994-03-17 00:00:00.0 Europe/Paris (+01:00)
    }
    -canceledAt: DateTime @1010617200 {#7315
      date: 2002-01-10 00:00:00.0 Europe/Paris (+01:00)
    }
    -edition: null
    -coreDocument: "1296"
    -bookCollection: ""
    -pageCount: 260
    -documents: Doctrine\ORM\PersistentCollection {#7466 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7501 …}
  }
  +label: "Most Recent"
  +icon: "check-xs"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

Symfony Profiler

GET https://dev.normadoc.fr/products/ieee-1296-1987-r1994-ieee00001971-240924

Configuration Settings

Theme

Page Width

Components

Components

Render calls