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Components

3 Twig Components
5 Render Count
3 ms Render Time
226.0 MiB Memory Usage

Components

Name Metadata Render Count Render Time
ProductState 
"App\Twig\Components\ProductState"
components/ProductState.html.twig 		2 0.64ms
ProductMostRecent 
"App\Twig\Components\ProductMostRecent"
components/ProductMostRecent.html.twig 		2 1.73ms
ProductType 
"App\Twig\Components\ProductType"
components/ProductType.html.twig 		1 0.29ms

Render calls

ProductState App\Twig\Components\ProductState 226.0 MiB 0.44 ms
Input props 
[
  "product" => App\Entity\Product\Product {#7311
    #id: 9431
    #code: "IEEE00002318"
    #attributes: Doctrine\ORM\PersistentCollection {#7701 …}
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      date: 2025-06-27 17:30:58.0 Europe/Paris (+02:00)
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        #description: """
          New IEEE Standard - Inactive-Withdrawn.<br />\n
          A high-bandwidth interface optimized for interchanging data between a memory controller and one or more dynamic RAMs is specified. RamLink is an applicable interface for other RAM-like devices as well.<br />\n
          \t\t\t\t<br />\n
          Define a high-bandwidth interface that will permit access to the large internal bandwidth already available in dynamic memory chips. The goal is to increase the performance and reduce the complexity of memory systems by using a subset of SCI protocols. Hierarchical memory systems will be considered, from multi-level caches to main-memory systems. The interface specification will apply to individual memory chips as well as their controllers. The interface should be applicable to commodity parts that will fulfilll the requirements of near-future (3-5 years) and subsequent generations of computor systems.<br />\n
          The performance of microprocessors doubles every 2-3 years. The density of main memory components used within these systems also doubles, but memory-access bandwidth has lagged behind. To meet their memory-access bandwidth requirements, designers currently build complex interleaved memory systems, which use 30-40 components. Application of SCI concepts will break through the performance of high-end workstations as well as the entry for low-end computers.
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    #reviews: Doctrine\ORM\PersistentCollection {#7613 …}
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Component 
App\Twig\Components\ProductState {#93008
  +product: App\Entity\Product\Product {#7311
    #id: 9431
    #code: "IEEE00002318"
    #attributes: Doctrine\ORM\PersistentCollection {#7701 …}
    #variants: Doctrine\ORM\PersistentCollection {#7744 …}
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      "en_US" => App\Entity\Product\ProductTranslation {#7921
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        #id: 32733
        #name: "IEEE 1596.4:1996"
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        #description: """
          New IEEE Standard - Inactive-Withdrawn.<br />\n
          A high-bandwidth interface optimized for interchanging data between a memory controller and one or more dynamic RAMs is specified. RamLink is an applicable interface for other RAM-like devices as well.<br />\n
          \t\t\t\t<br />\n
          Define a high-bandwidth interface that will permit access to the large internal bandwidth already available in dynamic memory chips. The goal is to increase the performance and reduce the complexity of memory systems by using a subset of SCI protocols. Hierarchical memory systems will be considered, from multi-level caches to main-memory systems. The interface specification will apply to individual memory chips as well as their controllers. The interface should be applicable to commodity parts that will fulfilll the requirements of near-future (3-5 years) and subsequent generations of computor systems.<br />\n
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    -favorites: Doctrine\ORM\PersistentCollection {#7500 …}
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ProductType App\Twig\Components\ProductType 226.0 MiB 0.29 ms
Input props 
[
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    #id: 9431
    #code: "IEEE00002318"
    #attributes: Doctrine\ORM\PersistentCollection {#7701 …}
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    #options: Doctrine\ORM\PersistentCollection {#7916 …}
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    #enabled: true
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      "en_US" => App\Entity\Product\ProductTranslation {#7921
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        #translatable: App\Entity\Product\Product {#7311}
        #id: 32733
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        #description: """
          New IEEE Standard - Inactive-Withdrawn.<br />\n
          A high-bandwidth interface optimized for interchanging data between a memory controller and one or more dynamic RAMs is specified. RamLink is an applicable interface for other RAM-like devices as well.<br />\n
          \t\t\t\t<br />\n
          Define a high-bandwidth interface that will permit access to the large internal bandwidth already available in dynamic memory chips. The goal is to increase the performance and reduce the complexity of memory systems by using a subset of SCI protocols. Hierarchical memory systems will be considered, from multi-level caches to main-memory systems. The interface specification will apply to individual memory chips as well as their controllers. The interface should be applicable to commodity parts that will fulfilll the requirements of near-future (3-5 years) and subsequent generations of computor systems.<br />\n
          The performance of microprocessors doubles every 2-3 years. The density of main memory components used within these systems also doubles, but memory-access bandwidth has lagged behind. To meet their memory-access bandwidth requirements, designers currently build complex interleaved memory systems, which use 30-40 components. Application of SCI concepts will break through the performance of high-end workstations as well as the entry for low-end computers.
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Attributes 
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Component 
App\Twig\Components\ProductType {#93188
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        #id: 32733
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          New IEEE Standard - Inactive-Withdrawn.<br />\n
          A high-bandwidth interface optimized for interchanging data between a memory controller and one or more dynamic RAMs is specified. RamLink is an applicable interface for other RAM-like devices as well.<br />\n
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          Define a high-bandwidth interface that will permit access to the large internal bandwidth already available in dynamic memory chips. The goal is to increase the performance and reduce the complexity of memory systems by using a subset of SCI protocols. Hierarchical memory systems will be considered, from multi-level caches to main-memory systems. The interface specification will apply to individual memory chips as well as their controllers. The interface should be applicable to commodity parts that will fulfilll the requirements of near-future (3-5 years) and subsequent generations of computor systems.<br />\n
          The performance of microprocessors doubles every 2-3 years. The density of main memory components used within these systems also doubles, but memory-access bandwidth has lagged behind. To meet their memory-access bandwidth requirements, designers currently build complex interleaved memory systems, which use 30-40 components. Application of SCI concepts will break through the performance of high-end workstations as well as the entry for low-end computers.
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ProductMostRecent App\Twig\Components\ProductMostRecent 226.0 MiB 1.00 ms
Input props 
[
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    #id: 9431
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          New IEEE Standard - Inactive-Withdrawn.<br />\n
          A high-bandwidth interface optimized for interchanging data between a memory controller and one or more dynamic RAMs is specified. RamLink is an applicable interface for other RAM-like devices as well.<br />\n
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Attributes 
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Component 
App\Twig\Components\ProductMostRecent {#93263
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          New IEEE Standard - Inactive-Withdrawn.<br />\n
          A high-bandwidth interface optimized for interchanging data between a memory controller and one or more dynamic RAMs is specified. RamLink is an applicable interface for other RAM-like devices as well.<br />\n
          \t\t\t\t<br />\n
          Define a high-bandwidth interface that will permit access to the large internal bandwidth already available in dynamic memory chips. The goal is to increase the performance and reduce the complexity of memory systems by using a subset of SCI protocols. Hierarchical memory systems will be considered, from multi-level caches to main-memory systems. The interface specification will apply to individual memory chips as well as their controllers. The interface should be applicable to commodity parts that will fulfilll the requirements of near-future (3-5 years) and subsequent generations of computor systems.<br />\n
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ProductState App\Twig\Components\ProductState 226.0 MiB 0.20 ms
Input props 
[
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