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          Electronic systems are integrated circuits (ICs), boards, or modules combining multiple ICs together, along with optional embedded processors and software components. Electronic systems are built to specifications that anticipate the environment in which such systems are expected to function and define the expected system functionality. Functional verification measures how well a system meets its specification. Even with moderately complex systems this question cannot be answered by inspection. For all modern electronic systems, a sophisticated verification process needs to accompany the design process to ensure compliance with the specification. Many electronic design automation (EDA) tools are used to carry out the functional verification process. The most prominent functional verification method, used to verify virtually all system designs, is called dynamic verification or simulation-based verification . Simulation-based verification makes use of a functional model of the system being designed. The functional model is simulated in the context of a mockup of the anticipated system environment. This mock-up is called the verification environment.<br />\n
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          The scope of this standard is the definition of the e functional verification language. The e functional verification language is an application-specific programming language, aimed at automating the task of verifying electronic designs with respect to their specifications. This standard aims to serve as an authoritative source for the definition of the following: a) syntax and semantics of e language constructs b) the e language interaction with standard simulation languages c) e language libraries<br />\n
          Electronic systems are integrated circuits (ICs), boards, or modules combining multiple ICs together, along with optional embedded processors and software components. Electronic systems are built to specifications that anticipate the environment in which such systems are expected to function and define the expected system functionality. Functional verification measures how well a system meets its specification. Even with moderately complex systems this question cannot be answered by inspection. For all modern electronic systems, a sophisticated verification process needs to accompany the design process to ensure compliance with the specification. Many electronic design automation (EDA) tools are used to carry out the functional verification process. The most prominent functional verification method, used to verify virtually all system designs, is called dynamic verification or simulation-based verification . Simulation-based verification makes use of a functional model of the system being designed. The functional model is simulated in the context of a mockup of the anticipated system environment. This mock-up is called the verification environment.<br />\n
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          — It needs to collect the output from the system being verified, as well as the state of selected internal nodes.<br />\n
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          — It needs to measure functional coverage : the extent to which functions of the system being verified have been exercised by the verification environment.<br />\n
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