GET https://dev.normadoc.fr/products/ieee-1076-2008-ieee00003666-241766

Response
200 OK
IP
216.73.216.146
Profiled on
Token
19d428

Forms

  • sylius_add_to_cart
    • cartItem
    • _token

sylius_add_to_cart

Form type: 
"Sylius\Bundle\CoreBundle\Form\Type\Order\AddToCartType"

Errors

This form has no errors.

Default Data

Property Value
Model Format same as normalized format
Normalized Format 
Sylius\Bundle\OrderBundle\Controller\AddToCartCommand {#123204
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          -snapshot: [ …4]
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        }
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        #enabled: true
        #translations: Doctrine\ORM\PersistentCollection {#8627 …}
        #translationsCache: [
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            #locale: "en_US"
            #translatable: App\Entity\Product\Product {#7520}
            #id: 35465
            #name: "IEEE 1076:2008"
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              Revision Standard - Superseded.<br />\n
              VHSIC Hardware Description Language (VHDL) is defined. VHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. Its primary audiences are the implementors of tools supporting the language and the advanced users of the language. (Additional downloads are available for this standard at https://standards.ieee.org/content/dam/ieee-standards/standards/web/download/1076-2008_downloads.zip)<br />\n
              \t\t\t\t<br />\n
              This standard revises and enhances the VHDL language reference manual (LRM) by including a standard C language interface specification; specifications from previously separate, but related, standards IEEE Std 1164 -1993,1 IEEE Std 1076.2 -1996, and IEEE Std 1076.3-1997; and general language enhancements in the areas of design and verification of electronic systems.<br />\n
              The VHDL language was defined for use in the design and documentation of electronics systems. It is revised to incorporate capabilities that improve the language's usefulness for its intended purpose as well as extend it to address design verification methodologies that have developed in industry. These new design and verification capabilities are required to ensure VHDL remains relevant and valuable for use in electronic systems design and verification. Incorporation of previously separate, but related standards, simplifies the maintenance of the specifications.
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            #metaKeywords: null
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        -lastUpdatedAt: DateTime @1613602800 {#7496
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        -author: ""
        -publishedAt: DateTime @1232924400 {#7531
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      }
      #updatedAt: DateTime @1755611983 {#8956
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      }
      #enabled: true
      #translations: Doctrine\ORM\PersistentCollection {#9244 …}
      #translationsCache: [
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          #translatable: App\Entity\Product\ProductVariant {#8931}
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      #currentLocale: "en_US"
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      #taxCategory: Proxies\__CG__\App\Entity\Taxation\TaxCategory {#8961 …}
      #shippingCategory: null
      #channelPricings: Doctrine\ORM\PersistentCollection {#9324 …}
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      #images: Doctrine\ORM\PersistentCollection {#9252 …}
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      -publishedAt: null
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View Format same as normalized format

Submitted Data

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Passed Options

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data 
Sylius\Bundle\OrderBundle\Controller\AddToCartCommand {#123204
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        #translationsCache: [
          "en_US" => App\Entity\Product\ProductTranslation {#8612
            #locale: "en_US"
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              Revision Standard - Superseded.<br />\n
              VHSIC Hardware Description Language (VHDL) is defined. VHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. Its primary audiences are the implementors of tools supporting the language and the advanced users of the language. (Additional downloads are available for this standard at https://standards.ieee.org/content/dam/ieee-standards/standards/web/download/1076-2008_downloads.zip)<br />\n
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              This standard revises and enhances the VHDL language reference manual (LRM) by including a standard C language interface specification; specifications from previously separate, but related, standards IEEE Std 1164 -1993,1 IEEE Std 1076.2 -1996, and IEEE Std 1076.3-1997; and general language enhancements in the areas of design and verification of electronic systems.<br />\n
              The VHDL language was defined for use in the design and documentation of electronics systems. It is revised to incorporate capabilities that improve the language's usefulness for its intended purpose as well as extend it to address design verification methodologies that have developed in industry. These new design and verification capabilities are required to ensure VHDL remains relevant and valuable for use in electronic systems design and verification. Incorporation of previously separate, but related standards, simplifies the maintenance of the specifications.
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            #metaKeywords: null
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        #reviews: Doctrine\ORM\PersistentCollection {#8066 …}
        #averageRating: 0.0
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        -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7681 …}
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        -apiLastModifiedAt: DateTime @1754517600 {#7530
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        }
        -lastUpdatedAt: DateTime @1613602800 {#7496
          date: 2021-02-18 00:00:00.0 Europe/Paris (+01:00)
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        -author: ""
        -publishedAt: DateTime @1232924400 {#7531
          date: 2009-01-26 00:00:00.0 Europe/Paris (+01:00)
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      #position: 0
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      }
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      }
      #enabled: true
      #translations: Doctrine\ORM\PersistentCollection {#9244 …}
      #translationsCache: [
        "en_US" => App\Entity\Product\ProductVariantTranslation {#95363
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      -sellable: true
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 same as passed value
product 
App\Entity\Product\Product {#7520
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  #variants: Doctrine\ORM\PersistentCollection {#8289 …}
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    -isDirty: false
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  #associations: Doctrine\ORM\PersistentCollection {#8585 …}
  #createdAt: DateTime @1751038826 {#7536
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  }
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  #translations: Doctrine\ORM\PersistentCollection {#8627 …}
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    "en_US" => App\Entity\Product\ProductTranslation {#8612
      #locale: "en_US"
      #translatable: App\Entity\Product\Product {#7520}
      #id: 35465
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        Revision Standard - Superseded.<br />\n
        VHSIC Hardware Description Language (VHDL) is defined. VHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. Its primary audiences are the implementors of tools supporting the language and the advanced users of the language. (Additional downloads are available for this standard at https://standards.ieee.org/content/dam/ieee-standards/standards/web/download/1076-2008_downloads.zip)<br />\n
        \t\t\t\t<br />\n
        This standard revises and enhances the VHDL language reference manual (LRM) by including a standard C language interface specification; specifications from previously separate, but related, standards IEEE Std 1164 -1993,1 IEEE Std 1076.2 -1996, and IEEE Std 1076.3-1997; and general language enhancements in the areas of design and verification of electronic systems.<br />\n
        The VHDL language was defined for use in the design and documentation of electronics systems. It is revised to incorporate capabilities that improve the language's usefulness for its intended purpose as well as extend it to address design verification methodologies that have developed in industry. These new design and verification capabilities are required to ensure VHDL remains relevant and valuable for use in electronic systems design and verification. Incorporation of previously separate, but related standards, simplifies the maintenance of the specifications.
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  #productTaxons: Doctrine\ORM\PersistentCollection {#7943 …}
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}
 same as passed value

Resolved Options

Option Value
action 
""
allow_extra_fields 
false
allow_file_upload 
false
attr 
[]
attr_translation_parameters 
[]
auto_initialize 
true
block_name 
null
block_prefix 
null
by_reference 
true
compound 
true
constraints 
[]
csrf_field_name 
"_token"
csrf_message 
"The CSRF token is invalid. Please try to resubmit the form."
csrf_protection 
true
csrf_token_id 
null
csrf_token_manager 
Symfony\Component\Security\Csrf\CsrfTokenManager {#123224
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  -namespace: Closure() {#123228 …}
}
data 
Sylius\Bundle\OrderBundle\Controller\AddToCartCommand {#123204
  -cart: App\Entity\Order\Order {#15353 …}
  -cartItem: App\Entity\Order\OrderItem {#123192
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    #order: null
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    #immutable: false
    #units: Doctrine\Common\Collections\ArrayCollection {#123216 …}
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    #adjustments: Doctrine\Common\Collections\ArrayCollection {#123217 …}
    #adjustmentsTotal: 0
    #version: 1
    #variant: App\Entity\Product\ProductVariant {#8931
      #id: 4155
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          -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#281974 …}
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        }
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        #translationsCache: [
          "en_US" => App\Entity\Product\ProductTranslation {#8612
            #locale: "en_US"
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            #name: "IEEE 1076:2008"
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              Revision Standard - Superseded.<br />\n
              VHSIC Hardware Description Language (VHDL) is defined. VHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. Its primary audiences are the implementors of tools supporting the language and the advanced users of the language. (Additional downloads are available for this standard at https://standards.ieee.org/content/dam/ieee-standards/standards/web/download/1076-2008_downloads.zip)<br />\n
              \t\t\t\t<br />\n
              This standard revises and enhances the VHDL language reference manual (LRM) by including a standard C language interface specification; specifications from previously separate, but related, standards IEEE Std 1164 -1993,1 IEEE Std 1076.2 -1996, and IEEE Std 1076.3-1997; and general language enhancements in the areas of design and verification of electronic systems.<br />\n
              The VHDL language was defined for use in the design and documentation of electronics systems. It is revised to incorporate capabilities that improve the language's usefulness for its intended purpose as well as extend it to address design verification methodologies that have developed in industry. These new design and verification capabilities are required to ensure VHDL remains relevant and valuable for use in electronic systems design and verification. Incorporation of previously separate, but related standards, simplifies the maintenance of the specifications.
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            #metaKeywords: null
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        #variantSelectionMethod: "match"
        #productTaxons: Doctrine\ORM\PersistentCollection {#7943 …}
        #channels: Doctrine\ORM\PersistentCollection {#8104 …}
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        #reviews: Doctrine\ORM\PersistentCollection {#8066 …}
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        -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7681 …}
        -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7746 …}
        -apiLastModifiedAt: DateTime @1754517600 {#7530
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        -lastUpdatedAt: DateTime @1613602800 {#7496
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        -author: ""
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      #optionValues: Doctrine\ORM\PersistentCollection {#9323 …}
      #position: 0
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      }
      #updatedAt: DateTime @1755611983 {#8956
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      }
      #enabled: true
      #translations: Doctrine\ORM\PersistentCollection {#9244 …}
      #translationsCache: [
        "en_US" => App\Entity\Product\ProductVariantTranslation {#95363
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