Components
4
Twig Components
10
Render Count
9
ms
Render Time
150.0
MiB
Memory Usage
Components
| Name | Metadata | Render Count | Render Time |
|---|---|---|---|
| ProductState |
"App\Twig\Components\ProductState"components/ProductState.html.twig |
4 | 1.02ms |
| ProductMostRecent |
"App\Twig\Components\ProductMostRecent"components/ProductMostRecent.html.twig |
4 | 2.76ms |
| ProductType |
"App\Twig\Components\ProductType"components/ProductType.html.twig |
1 | 0.22ms |
| ProductCard |
"App\Twig\Components\ProductCard"components/ProductCard.html.twig |
1 | 6.07ms |
Render calls
| ProductState | App\Twig\Components\ProductState | 150.0 MiB | 0.43 ms | |
|---|---|---|---|---|
| Input props | [ "product" => App\Entity\Product\Product {#7311 #id: 10224 #code: "IEEE00003936" #attributes: Doctrine\ORM\PersistentCollection {#7701 …} #variants: Doctrine\ORM\PersistentCollection {#7744 …} #options: Doctrine\ORM\PersistentCollection {#7916 …} #associations: Doctrine\ORM\PersistentCollection {#7900 …} #createdAt: DateTime @1751038910 {#7274 : 2025-06-27 17:41:50.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608190 {#7322 : 2025-08-08 01:09:50.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7922 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7921 #locale: "en_US" #translatable: App\Entity\Product\Product {#7311} #id: 35905 #name: "IEEE 1149.7:2009" #slug: "ieee-1149-7-2009-ieee00003936-241876" #description: """ New IEEE Standard - Inactive-Reserved.<br />\n This specification describes circuitry that may be added to an integrated circuit to provide access to on-chip Test Access Ports (TAPs) specified by IEEE Std 1149.1TM-2001. The circuitry uses IEEE 1149.1-2001 as its foundation, providing complete backward compatibility, while aggressively adding features to support test and applications debug. It defines six classes of 1149.7 Test Access Ports (TAP.7s), T0-T5, with each class providing incremental capability, building on that of the lower level classes. Class T0 provides the behavior specified by 1149.1 from startup when there are multiple on-chip TAPs. Class T1 adds common debug functions and features to minimize power consumption. Class T2 adds operating modes that maximize scan performance. It also provides an optional hot-connection capability to prevent system corruption when a connection is made to a powered system. Class T3 supports operation in either a fourwire Series or Star Scan Topology. Class T4 provides for communication with either a two-pin or four-pin interface. The two-pin operation serializes 1149.1 transactions and provides for higher Test Clock rates. Class T5 adds the ability to perform data transfers concurrent with scan, supports utilization of functions other than scan, and provides control of TAP.7 pins to custom debug technologies in a manner that ensures current and future interoperability.<br />\n \t\t\t\t<br />\n The standard will define a link between IEEE 1149.1 interfaces in Debug and Test Systems (DTS) and IEEE 1149.1 (JTAG) interfaces in Target Systems (TS). The link defined by this standard introduces an additional layer between these legacy interfaces. This layer may be viewed as an adapter that provides new functionality and features while preserving all elements of the original IEEE 1149.1 (JTAG) interfaces. The standard will define the link behavior (including timing characteristics of signals), protocols, and functionality of the adapters deployed within the DTS and TS. The standard will not modify or create inconsistencies with IEEE 1149.1 (JTAG). The standard will define a superset of the IEEE 1149.1 specification and achieve compliance with IEEE Std 1149.1TM-2001.<br />\n The purpose of the standard is to define a debug and test interface that meets an expanding set of challenges facing Debug and Test Systems (many of which have emerged since the inception of the original IEEE Std 1149.1) while preserving the hardware and software investments of the many industries currently using IEEE Std 1149.1-2001. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture" -notes: "Inactive-Reserved" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …} #channels: Doctrine\ORM\PersistentCollection {#7628 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#7613 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7645 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1698706800 {#7292 : 2023-10-31 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1265756400 {#7318 : 2010-02-10 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1616626800 {#7316 : 2021-03-25 00:00:00.0 Europe/Paris (+01:00) } -edition: null -coreDocument: "1149.7" -bookCollection: "" -pageCount: 985 -documents: Doctrine\ORM\PersistentCollection {#7465 …} -favorites: Doctrine\ORM\PersistentCollection {#7500 …} } "showFullLabel" => "true" ] |
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| Attributes | [ "showFullLabel" => "true" ] |
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| Component | App\Twig\Components\ProductState {#93008 +product: App\Entity\Product\Product {#7311 #id: 10224 #code: "IEEE00003936" #attributes: Doctrine\ORM\PersistentCollection {#7701 …} #variants: Doctrine\ORM\PersistentCollection {#7744 …} #options: Doctrine\ORM\PersistentCollection {#7916 …} #associations: Doctrine\ORM\PersistentCollection {#7900 …} #createdAt: DateTime @1751038910 {#7274 : 2025-06-27 17:41:50.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608190 {#7322 : 2025-08-08 01:09:50.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7922 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7921 #locale: "en_US" #translatable: App\Entity\Product\Product {#7311} #id: 35905 #name: "IEEE 1149.7:2009" #slug: "ieee-1149-7-2009-ieee00003936-241876" #description: """ New IEEE Standard - Inactive-Reserved.<br />\n This specification describes circuitry that may be added to an integrated circuit to provide access to on-chip Test Access Ports (TAPs) specified by IEEE Std 1149.1TM-2001. The circuitry uses IEEE 1149.1-2001 as its foundation, providing complete backward compatibility, while aggressively adding features to support test and applications debug. It defines six classes of 1149.7 Test Access Ports (TAP.7s), T0-T5, with each class providing incremental capability, building on that of the lower level classes. Class T0 provides the behavior specified by 1149.1 from startup when there are multiple on-chip TAPs. Class T1 adds common debug functions and features to minimize power consumption. Class T2 adds operating modes that maximize scan performance. It also provides an optional hot-connection capability to prevent system corruption when a connection is made to a powered system. Class T3 supports operation in either a fourwire Series or Star Scan Topology. Class T4 provides for communication with either a two-pin or four-pin interface. The two-pin operation serializes 1149.1 transactions and provides for higher Test Clock rates. Class T5 adds the ability to perform data transfers concurrent with scan, supports utilization of functions other than scan, and provides control of TAP.7 pins to custom debug technologies in a manner that ensures current and future interoperability.<br />\n \t\t\t\t<br />\n The standard will define a link between IEEE 1149.1 interfaces in Debug and Test Systems (DTS) and IEEE 1149.1 (JTAG) interfaces in Target Systems (TS). The link defined by this standard introduces an additional layer between these legacy interfaces. This layer may be viewed as an adapter that provides new functionality and features while preserving all elements of the original IEEE 1149.1 (JTAG) interfaces. The standard will define the link behavior (including timing characteristics of signals), protocols, and functionality of the adapters deployed within the DTS and TS. The standard will not modify or create inconsistencies with IEEE 1149.1 (JTAG). The standard will define a superset of the IEEE 1149.1 specification and achieve compliance with IEEE Std 1149.1TM-2001.<br />\n The purpose of the standard is to define a debug and test interface that meets an expanding set of challenges facing Debug and Test Systems (many of which have emerged since the inception of the original IEEE Std 1149.1) while preserving the hardware and software investments of the many industries currently using IEEE Std 1149.1-2001. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture" -notes: "Inactive-Reserved" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …} #channels: Doctrine\ORM\PersistentCollection {#7628 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#7613 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7645 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1698706800 {#7292 : 2023-10-31 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1265756400 {#7318 : 2010-02-10 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1616626800 {#7316 : 2021-03-25 00:00:00.0 Europe/Paris (+01:00) } -edition: null -coreDocument: "1149.7" -bookCollection: "" -pageCount: 985 -documents: Doctrine\ORM\PersistentCollection {#7465 …} -favorites: Doctrine\ORM\PersistentCollection {#7500 …} } +appearance: "state-withdrawn" +labels: [ "Withdrawn" ] -stateAttributeCode: "state" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …} } |
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| ProductType | App\Twig\Components\ProductType | 150.0 MiB | 0.22 ms | |
|---|---|---|---|---|
| Input props | [ "product" => App\Entity\Product\Product {#7311 #id: 10224 #code: "IEEE00003936" #attributes: Doctrine\ORM\PersistentCollection {#7701 …} #variants: Doctrine\ORM\PersistentCollection {#7744 …} #options: Doctrine\ORM\PersistentCollection {#7916 …} #associations: Doctrine\ORM\PersistentCollection {#7900 …} #createdAt: DateTime @1751038910 {#7274 : 2025-06-27 17:41:50.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608190 {#7322 : 2025-08-08 01:09:50.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7922 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7921 #locale: "en_US" #translatable: App\Entity\Product\Product {#7311} #id: 35905 #name: "IEEE 1149.7:2009" #slug: "ieee-1149-7-2009-ieee00003936-241876" #description: """ New IEEE Standard - Inactive-Reserved.<br />\n This specification describes circuitry that may be added to an integrated circuit to provide access to on-chip Test Access Ports (TAPs) specified by IEEE Std 1149.1TM-2001. The circuitry uses IEEE 1149.1-2001 as its foundation, providing complete backward compatibility, while aggressively adding features to support test and applications debug. It defines six classes of 1149.7 Test Access Ports (TAP.7s), T0-T5, with each class providing incremental capability, building on that of the lower level classes. Class T0 provides the behavior specified by 1149.1 from startup when there are multiple on-chip TAPs. Class T1 adds common debug functions and features to minimize power consumption. Class T2 adds operating modes that maximize scan performance. It also provides an optional hot-connection capability to prevent system corruption when a connection is made to a powered system. Class T3 supports operation in either a fourwire Series or Star Scan Topology. Class T4 provides for communication with either a two-pin or four-pin interface. The two-pin operation serializes 1149.1 transactions and provides for higher Test Clock rates. Class T5 adds the ability to perform data transfers concurrent with scan, supports utilization of functions other than scan, and provides control of TAP.7 pins to custom debug technologies in a manner that ensures current and future interoperability.<br />\n \t\t\t\t<br />\n The standard will define a link between IEEE 1149.1 interfaces in Debug and Test Systems (DTS) and IEEE 1149.1 (JTAG) interfaces in Target Systems (TS). The link defined by this standard introduces an additional layer between these legacy interfaces. This layer may be viewed as an adapter that provides new functionality and features while preserving all elements of the original IEEE 1149.1 (JTAG) interfaces. The standard will define the link behavior (including timing characteristics of signals), protocols, and functionality of the adapters deployed within the DTS and TS. The standard will not modify or create inconsistencies with IEEE 1149.1 (JTAG). The standard will define a superset of the IEEE 1149.1 specification and achieve compliance with IEEE Std 1149.1TM-2001.<br />\n The purpose of the standard is to define a debug and test interface that meets an expanding set of challenges facing Debug and Test Systems (many of which have emerged since the inception of the original IEEE Std 1149.1) while preserving the hardware and software investments of the many industries currently using IEEE Std 1149.1-2001. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture" -notes: "Inactive-Reserved" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …} #channels: Doctrine\ORM\PersistentCollection {#7628 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#7613 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7645 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1698706800 {#7292 : 2023-10-31 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1265756400 {#7318 : 2010-02-10 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1616626800 {#7316 : 2021-03-25 00:00:00.0 Europe/Paris (+01:00) } -edition: null -coreDocument: "1149.7" -bookCollection: "" -pageCount: 985 -documents: Doctrine\ORM\PersistentCollection {#7465 …} -favorites: Doctrine\ORM\PersistentCollection {#7500 …} } ] |
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| Attributes | [] |
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| Component | App\Twig\Components\ProductType {#93188 +product: App\Entity\Product\Product {#7311 #id: 10224 #code: "IEEE00003936" #attributes: Doctrine\ORM\PersistentCollection {#7701 …} #variants: Doctrine\ORM\PersistentCollection {#7744 …} #options: Doctrine\ORM\PersistentCollection {#7916 …} #associations: Doctrine\ORM\PersistentCollection {#7900 …} #createdAt: DateTime @1751038910 {#7274 : 2025-06-27 17:41:50.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608190 {#7322 : 2025-08-08 01:09:50.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7922 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7921 #locale: "en_US" #translatable: App\Entity\Product\Product {#7311} #id: 35905 #name: "IEEE 1149.7:2009" #slug: "ieee-1149-7-2009-ieee00003936-241876" #description: """ New IEEE Standard - Inactive-Reserved.<br />\n This specification describes circuitry that may be added to an integrated circuit to provide access to on-chip Test Access Ports (TAPs) specified by IEEE Std 1149.1TM-2001. The circuitry uses IEEE 1149.1-2001 as its foundation, providing complete backward compatibility, while aggressively adding features to support test and applications debug. It defines six classes of 1149.7 Test Access Ports (TAP.7s), T0-T5, with each class providing incremental capability, building on that of the lower level classes. Class T0 provides the behavior specified by 1149.1 from startup when there are multiple on-chip TAPs. Class T1 adds common debug functions and features to minimize power consumption. Class T2 adds operating modes that maximize scan performance. It also provides an optional hot-connection capability to prevent system corruption when a connection is made to a powered system. Class T3 supports operation in either a fourwire Series or Star Scan Topology. Class T4 provides for communication with either a two-pin or four-pin interface. The two-pin operation serializes 1149.1 transactions and provides for higher Test Clock rates. Class T5 adds the ability to perform data transfers concurrent with scan, supports utilization of functions other than scan, and provides control of TAP.7 pins to custom debug technologies in a manner that ensures current and future interoperability.<br />\n \t\t\t\t<br />\n The standard will define a link between IEEE 1149.1 interfaces in Debug and Test Systems (DTS) and IEEE 1149.1 (JTAG) interfaces in Target Systems (TS). The link defined by this standard introduces an additional layer between these legacy interfaces. This layer may be viewed as an adapter that provides new functionality and features while preserving all elements of the original IEEE 1149.1 (JTAG) interfaces. The standard will define the link behavior (including timing characteristics of signals), protocols, and functionality of the adapters deployed within the DTS and TS. The standard will not modify or create inconsistencies with IEEE 1149.1 (JTAG). The standard will define a superset of the IEEE 1149.1 specification and achieve compliance with IEEE Std 1149.1TM-2001.<br />\n The purpose of the standard is to define a debug and test interface that meets an expanding set of challenges facing Debug and Test Systems (many of which have emerged since the inception of the original IEEE Std 1149.1) while preserving the hardware and software investments of the many industries currently using IEEE Std 1149.1-2001. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture" -notes: "Inactive-Reserved" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …} #channels: Doctrine\ORM\PersistentCollection {#7628 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#7613 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7645 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1698706800 {#7292 : 2023-10-31 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1265756400 {#7318 : 2010-02-10 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1616626800 {#7316 : 2021-03-25 00:00:00.0 Europe/Paris (+01:00) } -edition: null -coreDocument: "1149.7" -bookCollection: "" -pageCount: 985 -documents: Doctrine\ORM\PersistentCollection {#7465 …} -favorites: Doctrine\ORM\PersistentCollection {#7500 …} } +label: "Standard" -typeAttributeCode: "type" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …} } |
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| ProductMostRecent | App\Twig\Components\ProductMostRecent | 150.0 MiB | 0.71 ms | |
|---|---|---|---|---|
| Input props | [ "product" => App\Entity\Product\Product {#7311 #id: 10224 #code: "IEEE00003936" #attributes: Doctrine\ORM\PersistentCollection {#7701 …} #variants: Doctrine\ORM\PersistentCollection {#7744 …} #options: Doctrine\ORM\PersistentCollection {#7916 …} #associations: Doctrine\ORM\PersistentCollection {#7900 …} #createdAt: DateTime @1751038910 {#7274 : 2025-06-27 17:41:50.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608190 {#7322 : 2025-08-08 01:09:50.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7922 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7921 #locale: "en_US" #translatable: App\Entity\Product\Product {#7311} #id: 35905 #name: "IEEE 1149.7:2009" #slug: "ieee-1149-7-2009-ieee00003936-241876" #description: """ New IEEE Standard - Inactive-Reserved.<br />\n This specification describes circuitry that may be added to an integrated circuit to provide access to on-chip Test Access Ports (TAPs) specified by IEEE Std 1149.1TM-2001. The circuitry uses IEEE 1149.1-2001 as its foundation, providing complete backward compatibility, while aggressively adding features to support test and applications debug. It defines six classes of 1149.7 Test Access Ports (TAP.7s), T0-T5, with each class providing incremental capability, building on that of the lower level classes. Class T0 provides the behavior specified by 1149.1 from startup when there are multiple on-chip TAPs. Class T1 adds common debug functions and features to minimize power consumption. Class T2 adds operating modes that maximize scan performance. It also provides an optional hot-connection capability to prevent system corruption when a connection is made to a powered system. Class T3 supports operation in either a fourwire Series or Star Scan Topology. Class T4 provides for communication with either a two-pin or four-pin interface. The two-pin operation serializes 1149.1 transactions and provides for higher Test Clock rates. Class T5 adds the ability to perform data transfers concurrent with scan, supports utilization of functions other than scan, and provides control of TAP.7 pins to custom debug technologies in a manner that ensures current and future interoperability.<br />\n \t\t\t\t<br />\n The standard will define a link between IEEE 1149.1 interfaces in Debug and Test Systems (DTS) and IEEE 1149.1 (JTAG) interfaces in Target Systems (TS). The link defined by this standard introduces an additional layer between these legacy interfaces. This layer may be viewed as an adapter that provides new functionality and features while preserving all elements of the original IEEE 1149.1 (JTAG) interfaces. The standard will define the link behavior (including timing characteristics of signals), protocols, and functionality of the adapters deployed within the DTS and TS. The standard will not modify or create inconsistencies with IEEE 1149.1 (JTAG). The standard will define a superset of the IEEE 1149.1 specification and achieve compliance with IEEE Std 1149.1TM-2001.<br />\n The purpose of the standard is to define a debug and test interface that meets an expanding set of challenges facing Debug and Test Systems (many of which have emerged since the inception of the original IEEE Std 1149.1) while preserving the hardware and software investments of the many industries currently using IEEE Std 1149.1-2001. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture" -notes: "Inactive-Reserved" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …} #channels: Doctrine\ORM\PersistentCollection {#7628 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#7613 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7645 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1698706800 {#7292 : 2023-10-31 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1265756400 {#7318 : 2010-02-10 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1616626800 {#7316 : 2021-03-25 00:00:00.0 Europe/Paris (+01:00) } -edition: null -coreDocument: "1149.7" -bookCollection: "" -pageCount: 985 -documents: Doctrine\ORM\PersistentCollection {#7465 …} -favorites: Doctrine\ORM\PersistentCollection {#7500 …} } ] |
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| Attributes | [] |
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| Component | App\Twig\Components\ProductMostRecent {#93263 +product: App\Entity\Product\Product {#7311 #id: 10224 #code: "IEEE00003936" #attributes: Doctrine\ORM\PersistentCollection {#7701 …} #variants: Doctrine\ORM\PersistentCollection {#7744 …} #options: Doctrine\ORM\PersistentCollection {#7916 …} #associations: Doctrine\ORM\PersistentCollection {#7900 …} #createdAt: DateTime @1751038910 {#7274 : 2025-06-27 17:41:50.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608190 {#7322 : 2025-08-08 01:09:50.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7922 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7921 #locale: "en_US" #translatable: App\Entity\Product\Product {#7311} #id: 35905 #name: "IEEE 1149.7:2009" #slug: "ieee-1149-7-2009-ieee00003936-241876" #description: """ New IEEE Standard - Inactive-Reserved.<br />\n This specification describes circuitry that may be added to an integrated circuit to provide access to on-chip Test Access Ports (TAPs) specified by IEEE Std 1149.1TM-2001. The circuitry uses IEEE 1149.1-2001 as its foundation, providing complete backward compatibility, while aggressively adding features to support test and applications debug. It defines six classes of 1149.7 Test Access Ports (TAP.7s), T0-T5, with each class providing incremental capability, building on that of the lower level classes. Class T0 provides the behavior specified by 1149.1 from startup when there are multiple on-chip TAPs. Class T1 adds common debug functions and features to minimize power consumption. Class T2 adds operating modes that maximize scan performance. It also provides an optional hot-connection capability to prevent system corruption when a connection is made to a powered system. Class T3 supports operation in either a fourwire Series or Star Scan Topology. Class T4 provides for communication with either a two-pin or four-pin interface. The two-pin operation serializes 1149.1 transactions and provides for higher Test Clock rates. Class T5 adds the ability to perform data transfers concurrent with scan, supports utilization of functions other than scan, and provides control of TAP.7 pins to custom debug technologies in a manner that ensures current and future interoperability.<br />\n \t\t\t\t<br />\n The standard will define a link between IEEE 1149.1 interfaces in Debug and Test Systems (DTS) and IEEE 1149.1 (JTAG) interfaces in Target Systems (TS). The link defined by this standard introduces an additional layer between these legacy interfaces. This layer may be viewed as an adapter that provides new functionality and features while preserving all elements of the original IEEE 1149.1 (JTAG) interfaces. The standard will define the link behavior (including timing characteristics of signals), protocols, and functionality of the adapters deployed within the DTS and TS. The standard will not modify or create inconsistencies with IEEE 1149.1 (JTAG). The standard will define a superset of the IEEE 1149.1 specification and achieve compliance with IEEE Std 1149.1TM-2001.<br />\n The purpose of the standard is to define a debug and test interface that meets an expanding set of challenges facing Debug and Test Systems (many of which have emerged since the inception of the original IEEE Std 1149.1) while preserving the hardware and software investments of the many industries currently using IEEE Std 1149.1-2001. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture" -notes: "Inactive-Reserved" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …} #channels: Doctrine\ORM\PersistentCollection {#7628 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#7613 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7645 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1698706800 {#7292 : 2023-10-31 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1265756400 {#7318 : 2010-02-10 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1616626800 {#7316 : 2021-03-25 00:00:00.0 Europe/Paris (+01:00) } -edition: null -coreDocument: "1149.7" -bookCollection: "" -pageCount: 985 -documents: Doctrine\ORM\PersistentCollection {#7465 …} -favorites: Doctrine\ORM\PersistentCollection {#7500 …} } +label: "Most Recent" +icon: "check-xs" -mostRecentAttributeCode: "most_recent" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …} } |
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| Input props | [ "product" => App\Entity\Product\Product {#93687 #id: 12444 #code: "IEEE00007703" #attributes: Doctrine\ORM\PersistentCollection {#93667 …} #variants: Doctrine\ORM\PersistentCollection {#93664 …} #options: Doctrine\ORM\PersistentCollection {#93660 …} #associations: Doctrine\ORM\PersistentCollection {#93656 …} #createdAt: DateTime @1751040435 {#93694 : 2025-06-27 18:07:15.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1753970953 {#93673 : 2025-07-31 16:09:13.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#93678 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#93719 #locale: "en_US" #translatable: App\Entity\Product\Product {#93687} #id: 44785 #name: "IEEE 1149.7:2022" #slug: "ieee-1149-7-2022-ieee00007703-244098" #description: """ Revision Standard - Active.<br />\n Circuitry that may be added to an integrated circuit to provide access to on-chip Test Access Ports (TAPs) specified by IEEE Std 1149.1 is described in this standard. The circuitry<br />\n uses IEEE Std 1149.1 as its foundation, providing complete backward compatibility, while aggressively adding features to support test and applications debug. It defines six classes of IEEE 1149.7 Test Access Ports (TAP.7s), T0 to T5, with each class providing incremental capability, building on that of the lower level classes. Class T0 provides the behavior specified by 1149.1 from startup when there are multiple on-chip TAPs. Class T1 adds common debug functions and features to minimize power consumption. Class T2 adds operating modes that maximize scan performance. It also provides an optional hot-connection capability to prevent system corruption when a connection is made to a powered system. Class T3 supports operation in either a four-wire Series or Star Scan Topology. Class T4 provides for communication with either a two-pin or four-pin interface. The two-pin operation serializes IEEE 1149.1 transactions and provides for higher Test Clock rates. Class T5 adds the ability to perform data transfers concurrently with scan, supports utilization of functions other than scan, and provides control of TAP.7 pins to custom debug technologies in a manner that ensures current and future interoperability.<br />\n \t\t\t\t<br />\n The standard will define a link between IEEE 1149.1 interfaces in Debug and Test Systems (DTS) and IEEE 1149.1 (JTAG) interfaces in Target Systems (TS). The link defined by this standard introduces an additional layer between these legacy interfaces. This layer may be viewed as an adapter that provides new functionality and features while preserving all elements of the original IEEE 1149.1 (JTAG) interfaces. The standard will define the link behavior (including timing characteristics of signals), protocols, and functionality of the adapters deployed within the DTS and TS. The standard will not modify or create inconsistencies with IEEE 1149.1 (JTAG). The standard will define a superset of the IEEE 1149.1 specification and achieve compliance with IEEE Std 1149.1.<br />\n The purpose of the standard is to define a debug and test interface that meets an expanding set of challenges facing Debug and Test Systems (many of which have emerged since the inception of the original IEEE Std 1149.1) while preserving the hardware and software investments of the many industries currently using IEEE Std 1149.1. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture" -notes: "Active" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#93676 …} #channels: Doctrine\ORM\PersistentCollection {#93669 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#93674 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#93671 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#93684 …} -apiLastModifiedAt: DateTime @1743289200 {#93657 : 2025-03-30 00:00:00.0 Europe/Paris (+01:00) } -lastUpdatedAt: DateTime @1725832800 {#93693 : 2024-09-09 00:00:00.0 Europe/Paris (+02:00) } -author: "" -publishedAt: DateTime @1665698400 {#93692 : 2022-10-14 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1665698400 {#93686 : 2022-10-14 00:00:00.0 Europe/Paris (+02:00) } -edition: null -coreDocument: "1149.7" -bookCollection: "" -pageCount: 1048 -documents: Doctrine\ORM\PersistentCollection {#93682 …} -favorites: Doctrine\ORM\PersistentCollection {#93680 …} } "showFullLabel" => "true" ] |
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| Attributes | [ "showFullLabel" => "true" ] |
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| Component | App\Twig\Components\ProductState {#106848 +product: App\Entity\Product\Product {#93687 #id: 12444 #code: "IEEE00007703" #attributes: Doctrine\ORM\PersistentCollection {#93667 …} #variants: Doctrine\ORM\PersistentCollection {#93664 …} #options: Doctrine\ORM\PersistentCollection {#93660 …} #associations: Doctrine\ORM\PersistentCollection {#93656 …} #createdAt: DateTime @1751040435 {#93694 : 2025-06-27 18:07:15.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1753970953 {#93673 : 2025-07-31 16:09:13.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#93678 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#93719 #locale: "en_US" #translatable: App\Entity\Product\Product {#93687} #id: 44785 #name: "IEEE 1149.7:2022" #slug: "ieee-1149-7-2022-ieee00007703-244098" #description: """ Revision Standard - Active.<br />\n Circuitry that may be added to an integrated circuit to provide access to on-chip Test Access Ports (TAPs) specified by IEEE Std 1149.1 is described in this standard. The circuitry<br />\n uses IEEE Std 1149.1 as its foundation, providing complete backward compatibility, while aggressively adding features to support test and applications debug. It defines six classes of IEEE 1149.7 Test Access Ports (TAP.7s), T0 to T5, with each class providing incremental capability, building on that of the lower level classes. Class T0 provides the behavior specified by 1149.1 from startup when there are multiple on-chip TAPs. Class T1 adds common debug functions and features to minimize power consumption. Class T2 adds operating modes that maximize scan performance. It also provides an optional hot-connection capability to prevent system corruption when a connection is made to a powered system. Class T3 supports operation in either a four-wire Series or Star Scan Topology. Class T4 provides for communication with either a two-pin or four-pin interface. The two-pin operation serializes IEEE 1149.1 transactions and provides for higher Test Clock rates. Class T5 adds the ability to perform data transfers concurrently with scan, supports utilization of functions other than scan, and provides control of TAP.7 pins to custom debug technologies in a manner that ensures current and future interoperability.<br />\n \t\t\t\t<br />\n The standard will define a link between IEEE 1149.1 interfaces in Debug and Test Systems (DTS) and IEEE 1149.1 (JTAG) interfaces in Target Systems (TS). The link defined by this standard introduces an additional layer between these legacy interfaces. This layer may be viewed as an adapter that provides new functionality and features while preserving all elements of the original IEEE 1149.1 (JTAG) interfaces. The standard will define the link behavior (including timing characteristics of signals), protocols, and functionality of the adapters deployed within the DTS and TS. The standard will not modify or create inconsistencies with IEEE 1149.1 (JTAG). The standard will define a superset of the IEEE 1149.1 specification and achieve compliance with IEEE Std 1149.1.<br />\n The purpose of the standard is to define a debug and test interface that meets an expanding set of challenges facing Debug and Test Systems (many of which have emerged since the inception of the original IEEE Std 1149.1) while preserving the hardware and software investments of the many industries currently using IEEE Std 1149.1. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture" -notes: "Active" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#93676 …} #channels: Doctrine\ORM\PersistentCollection {#93669 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#93674 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#93671 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#93684 …} -apiLastModifiedAt: DateTime @1743289200 {#93657 : 2025-03-30 00:00:00.0 Europe/Paris (+01:00) } -lastUpdatedAt: DateTime @1725832800 {#93693 : 2024-09-09 00:00:00.0 Europe/Paris (+02:00) } -author: "" -publishedAt: DateTime @1665698400 {#93692 : 2022-10-14 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1665698400 {#93686 : 2022-10-14 00:00:00.0 Europe/Paris (+02:00) } -edition: null -coreDocument: "1149.7" -bookCollection: "" -pageCount: 1048 -documents: Doctrine\ORM\PersistentCollection {#93682 …} -favorites: Doctrine\ORM\PersistentCollection {#93680 …} } +appearance: "state-active" +labels: [ "Active" ] -stateAttributeCode: "state" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …} } |
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| ProductMostRecent | App\Twig\Components\ProductMostRecent | 150.0 MiB | 0.73 ms | |
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| Input props | [ "product" => App\Entity\Product\Product {#93687 #id: 12444 #code: "IEEE00007703" #attributes: Doctrine\ORM\PersistentCollection {#93667 …} #variants: Doctrine\ORM\PersistentCollection {#93664 …} #options: Doctrine\ORM\PersistentCollection {#93660 …} #associations: Doctrine\ORM\PersistentCollection {#93656 …} #createdAt: DateTime @1751040435 {#93694 : 2025-06-27 18:07:15.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1753970953 {#93673 : 2025-07-31 16:09:13.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#93678 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#93719 #locale: "en_US" #translatable: App\Entity\Product\Product {#93687} #id: 44785 #name: "IEEE 1149.7:2022" #slug: "ieee-1149-7-2022-ieee00007703-244098" #description: """ Revision Standard - Active.<br />\n Circuitry that may be added to an integrated circuit to provide access to on-chip Test Access Ports (TAPs) specified by IEEE Std 1149.1 is described in this standard. The circuitry<br />\n uses IEEE Std 1149.1 as its foundation, providing complete backward compatibility, while aggressively adding features to support test and applications debug. It defines six classes of IEEE 1149.7 Test Access Ports (TAP.7s), T0 to T5, with each class providing incremental capability, building on that of the lower level classes. Class T0 provides the behavior specified by 1149.1 from startup when there are multiple on-chip TAPs. Class T1 adds common debug functions and features to minimize power consumption. Class T2 adds operating modes that maximize scan performance. It also provides an optional hot-connection capability to prevent system corruption when a connection is made to a powered system. Class T3 supports operation in either a four-wire Series or Star Scan Topology. Class T4 provides for communication with either a two-pin or four-pin interface. The two-pin operation serializes IEEE 1149.1 transactions and provides for higher Test Clock rates. Class T5 adds the ability to perform data transfers concurrently with scan, supports utilization of functions other than scan, and provides control of TAP.7 pins to custom debug technologies in a manner that ensures current and future interoperability.<br />\n \t\t\t\t<br />\n The standard will define a link between IEEE 1149.1 interfaces in Debug and Test Systems (DTS) and IEEE 1149.1 (JTAG) interfaces in Target Systems (TS). The link defined by this standard introduces an additional layer between these legacy interfaces. This layer may be viewed as an adapter that provides new functionality and features while preserving all elements of the original IEEE 1149.1 (JTAG) interfaces. The standard will define the link behavior (including timing characteristics of signals), protocols, and functionality of the adapters deployed within the DTS and TS. The standard will not modify or create inconsistencies with IEEE 1149.1 (JTAG). The standard will define a superset of the IEEE 1149.1 specification and achieve compliance with IEEE Std 1149.1.<br />\n The purpose of the standard is to define a debug and test interface that meets an expanding set of challenges facing Debug and Test Systems (many of which have emerged since the inception of the original IEEE Std 1149.1) while preserving the hardware and software investments of the many industries currently using IEEE Std 1149.1. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture" -notes: "Active" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#93676 …} #channels: Doctrine\ORM\PersistentCollection {#93669 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#93674 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#93671 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#93684 …} -apiLastModifiedAt: DateTime @1743289200 {#93657 : 2025-03-30 00:00:00.0 Europe/Paris (+01:00) } -lastUpdatedAt: DateTime @1725832800 {#93693 : 2024-09-09 00:00:00.0 Europe/Paris (+02:00) } -author: "" -publishedAt: DateTime @1665698400 {#93692 : 2022-10-14 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1665698400 {#93686 : 2022-10-14 00:00:00.0 Europe/Paris (+02:00) } -edition: null -coreDocument: "1149.7" -bookCollection: "" -pageCount: 1048 -documents: Doctrine\ORM\PersistentCollection {#93682 …} -favorites: Doctrine\ORM\PersistentCollection {#93680 …} } ] |
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| Attributes | [] |
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| Component | App\Twig\Components\ProductMostRecent {#106920 +product: App\Entity\Product\Product {#93687 #id: 12444 #code: "IEEE00007703" #attributes: Doctrine\ORM\PersistentCollection {#93667 …} #variants: Doctrine\ORM\PersistentCollection {#93664 …} #options: Doctrine\ORM\PersistentCollection {#93660 …} #associations: Doctrine\ORM\PersistentCollection {#93656 …} #createdAt: DateTime @1751040435 {#93694 : 2025-06-27 18:07:15.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1753970953 {#93673 : 2025-07-31 16:09:13.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#93678 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#93719 #locale: "en_US" #translatable: App\Entity\Product\Product {#93687} #id: 44785 #name: "IEEE 1149.7:2022" #slug: "ieee-1149-7-2022-ieee00007703-244098" #description: """ Revision Standard - Active.<br />\n Circuitry that may be added to an integrated circuit to provide access to on-chip Test Access Ports (TAPs) specified by IEEE Std 1149.1 is described in this standard. The circuitry<br />\n uses IEEE Std 1149.1 as its foundation, providing complete backward compatibility, while aggressively adding features to support test and applications debug. It defines six classes of IEEE 1149.7 Test Access Ports (TAP.7s), T0 to T5, with each class providing incremental capability, building on that of the lower level classes. Class T0 provides the behavior specified by 1149.1 from startup when there are multiple on-chip TAPs. Class T1 adds common debug functions and features to minimize power consumption. Class T2 adds operating modes that maximize scan performance. It also provides an optional hot-connection capability to prevent system corruption when a connection is made to a powered system. Class T3 supports operation in either a four-wire Series or Star Scan Topology. Class T4 provides for communication with either a two-pin or four-pin interface. The two-pin operation serializes IEEE 1149.1 transactions and provides for higher Test Clock rates. Class T5 adds the ability to perform data transfers concurrently with scan, supports utilization of functions other than scan, and provides control of TAP.7 pins to custom debug technologies in a manner that ensures current and future interoperability.<br />\n \t\t\t\t<br />\n The standard will define a link between IEEE 1149.1 interfaces in Debug and Test Systems (DTS) and IEEE 1149.1 (JTAG) interfaces in Target Systems (TS). The link defined by this standard introduces an additional layer between these legacy interfaces. This layer may be viewed as an adapter that provides new functionality and features while preserving all elements of the original IEEE 1149.1 (JTAG) interfaces. The standard will define the link behavior (including timing characteristics of signals), protocols, and functionality of the adapters deployed within the DTS and TS. The standard will not modify or create inconsistencies with IEEE 1149.1 (JTAG). The standard will define a superset of the IEEE 1149.1 specification and achieve compliance with IEEE Std 1149.1.<br />\n The purpose of the standard is to define a debug and test interface that meets an expanding set of challenges facing Debug and Test Systems (many of which have emerged since the inception of the original IEEE Std 1149.1) while preserving the hardware and software investments of the many industries currently using IEEE Std 1149.1. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture" -notes: "Active" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#93676 …} #channels: Doctrine\ORM\PersistentCollection {#93669 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#93674 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#93671 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#93684 …} -apiLastModifiedAt: DateTime @1743289200 {#93657 : 2025-03-30 00:00:00.0 Europe/Paris (+01:00) } -lastUpdatedAt: DateTime @1725832800 {#93693 : 2024-09-09 00:00:00.0 Europe/Paris (+02:00) } -author: "" -publishedAt: DateTime @1665698400 {#93692 : 2022-10-14 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1665698400 {#93686 : 2022-10-14 00:00:00.0 Europe/Paris (+02:00) } -edition: null -coreDocument: "1149.7" -bookCollection: "" -pageCount: 1048 -documents: Doctrine\ORM\PersistentCollection {#93682 …} -favorites: Doctrine\ORM\PersistentCollection {#93680 …} } +label: "Most Recent" +icon: "check-xs" -mostRecentAttributeCode: "most_recent" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …} } |
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| ProductState | App\Twig\Components\ProductState | 150.0 MiB | 0.18 ms | |
|---|---|---|---|---|
| Input props | [ "product" => App\Entity\Product\Product {#7311 #id: 10224 #code: "IEEE00003936" #attributes: Doctrine\ORM\PersistentCollection {#7701 …} #variants: Doctrine\ORM\PersistentCollection {#7744 …} #options: Doctrine\ORM\PersistentCollection {#7916 …} #associations: Doctrine\ORM\PersistentCollection {#7900 …} #createdAt: DateTime @1751038910 {#7274 : 2025-06-27 17:41:50.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608190 {#7322 : 2025-08-08 01:09:50.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7922 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7921 #locale: "en_US" #translatable: App\Entity\Product\Product {#7311} #id: 35905 #name: "IEEE 1149.7:2009" #slug: "ieee-1149-7-2009-ieee00003936-241876" #description: """ New IEEE Standard - Inactive-Reserved.<br />\n This specification describes circuitry that may be added to an integrated circuit to provide access to on-chip Test Access Ports (TAPs) specified by IEEE Std 1149.1TM-2001. The circuitry uses IEEE 1149.1-2001 as its foundation, providing complete backward compatibility, while aggressively adding features to support test and applications debug. It defines six classes of 1149.7 Test Access Ports (TAP.7s), T0-T5, with each class providing incremental capability, building on that of the lower level classes. Class T0 provides the behavior specified by 1149.1 from startup when there are multiple on-chip TAPs. Class T1 adds common debug functions and features to minimize power consumption. Class T2 adds operating modes that maximize scan performance. It also provides an optional hot-connection capability to prevent system corruption when a connection is made to a powered system. Class T3 supports operation in either a fourwire Series or Star Scan Topology. Class T4 provides for communication with either a two-pin or four-pin interface. The two-pin operation serializes 1149.1 transactions and provides for higher Test Clock rates. Class T5 adds the ability to perform data transfers concurrent with scan, supports utilization of functions other than scan, and provides control of TAP.7 pins to custom debug technologies in a manner that ensures current and future interoperability.<br />\n \t\t\t\t<br />\n The standard will define a link between IEEE 1149.1 interfaces in Debug and Test Systems (DTS) and IEEE 1149.1 (JTAG) interfaces in Target Systems (TS). The link defined by this standard introduces an additional layer between these legacy interfaces. This layer may be viewed as an adapter that provides new functionality and features while preserving all elements of the original IEEE 1149.1 (JTAG) interfaces. The standard will define the link behavior (including timing characteristics of signals), protocols, and functionality of the adapters deployed within the DTS and TS. The standard will not modify or create inconsistencies with IEEE 1149.1 (JTAG). The standard will define a superset of the IEEE 1149.1 specification and achieve compliance with IEEE Std 1149.1TM-2001.<br />\n The purpose of the standard is to define a debug and test interface that meets an expanding set of challenges facing Debug and Test Systems (many of which have emerged since the inception of the original IEEE Std 1149.1) while preserving the hardware and software investments of the many industries currently using IEEE Std 1149.1-2001. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture" -notes: "Inactive-Reserved" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …} #channels: Doctrine\ORM\PersistentCollection {#7628 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#7613 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7645 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1698706800 {#7292 : 2023-10-31 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1265756400 {#7318 : 2010-02-10 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1616626800 {#7316 : 2021-03-25 00:00:00.0 Europe/Paris (+01:00) } -edition: null -coreDocument: "1149.7" -bookCollection: "" -pageCount: 985 -documents: Doctrine\ORM\PersistentCollection {#7465 …} -favorites: Doctrine\ORM\PersistentCollection {#7500 …} } "showFullLabel" => "true" ] |
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| Attributes | [ "showFullLabel" => "true" ] |
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| Component | App\Twig\Components\ProductState {#106985 +product: App\Entity\Product\Product {#7311 #id: 10224 #code: "IEEE00003936" #attributes: Doctrine\ORM\PersistentCollection {#7701 …} #variants: Doctrine\ORM\PersistentCollection {#7744 …} #options: Doctrine\ORM\PersistentCollection {#7916 …} #associations: Doctrine\ORM\PersistentCollection {#7900 …} #createdAt: DateTime @1751038910 {#7274 : 2025-06-27 17:41:50.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608190 {#7322 : 2025-08-08 01:09:50.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7922 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7921 #locale: "en_US" #translatable: App\Entity\Product\Product {#7311} #id: 35905 #name: "IEEE 1149.7:2009" #slug: "ieee-1149-7-2009-ieee00003936-241876" #description: """ New IEEE Standard - Inactive-Reserved.<br />\n This specification describes circuitry that may be added to an integrated circuit to provide access to on-chip Test Access Ports (TAPs) specified by IEEE Std 1149.1TM-2001. The circuitry uses IEEE 1149.1-2001 as its foundation, providing complete backward compatibility, while aggressively adding features to support test and applications debug. It defines six classes of 1149.7 Test Access Ports (TAP.7s), T0-T5, with each class providing incremental capability, building on that of the lower level classes. Class T0 provides the behavior specified by 1149.1 from startup when there are multiple on-chip TAPs. Class T1 adds common debug functions and features to minimize power consumption. Class T2 adds operating modes that maximize scan performance. It also provides an optional hot-connection capability to prevent system corruption when a connection is made to a powered system. Class T3 supports operation in either a fourwire Series or Star Scan Topology. Class T4 provides for communication with either a two-pin or four-pin interface. The two-pin operation serializes 1149.1 transactions and provides for higher Test Clock rates. Class T5 adds the ability to perform data transfers concurrent with scan, supports utilization of functions other than scan, and provides control of TAP.7 pins to custom debug technologies in a manner that ensures current and future interoperability.<br />\n \t\t\t\t<br />\n The standard will define a link between IEEE 1149.1 interfaces in Debug and Test Systems (DTS) and IEEE 1149.1 (JTAG) interfaces in Target Systems (TS). The link defined by this standard introduces an additional layer between these legacy interfaces. This layer may be viewed as an adapter that provides new functionality and features while preserving all elements of the original IEEE 1149.1 (JTAG) interfaces. The standard will define the link behavior (including timing characteristics of signals), protocols, and functionality of the adapters deployed within the DTS and TS. The standard will not modify or create inconsistencies with IEEE 1149.1 (JTAG). The standard will define a superset of the IEEE 1149.1 specification and achieve compliance with IEEE Std 1149.1TM-2001.<br />\n The purpose of the standard is to define a debug and test interface that meets an expanding set of challenges facing Debug and Test Systems (many of which have emerged since the inception of the original IEEE Std 1149.1) while preserving the hardware and software investments of the many industries currently using IEEE Std 1149.1-2001. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture" -notes: "Inactive-Reserved" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …} #channels: Doctrine\ORM\PersistentCollection {#7628 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#7613 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7645 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1698706800 {#7292 : 2023-10-31 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1265756400 {#7318 : 2010-02-10 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1616626800 {#7316 : 2021-03-25 00:00:00.0 Europe/Paris (+01:00) } -edition: null -coreDocument: "1149.7" -bookCollection: "" -pageCount: 985 -documents: Doctrine\ORM\PersistentCollection {#7465 …} -favorites: Doctrine\ORM\PersistentCollection {#7500 …} } +appearance: "state-withdrawn" +labels: [ "Withdrawn" ] -stateAttributeCode: "state" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …} } |
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| ProductMostRecent | App\Twig\Components\ProductMostRecent | 150.0 MiB | 0.62 ms | |
|---|---|---|---|---|
| Input props | [ "product" => App\Entity\Product\Product {#7311 #id: 10224 #code: "IEEE00003936" #attributes: Doctrine\ORM\PersistentCollection {#7701 …} #variants: Doctrine\ORM\PersistentCollection {#7744 …} #options: Doctrine\ORM\PersistentCollection {#7916 …} #associations: Doctrine\ORM\PersistentCollection {#7900 …} #createdAt: DateTime @1751038910 {#7274 : 2025-06-27 17:41:50.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608190 {#7322 : 2025-08-08 01:09:50.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7922 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7921 #locale: "en_US" #translatable: App\Entity\Product\Product {#7311} #id: 35905 #name: "IEEE 1149.7:2009" #slug: "ieee-1149-7-2009-ieee00003936-241876" #description: """ New IEEE Standard - Inactive-Reserved.<br />\n This specification describes circuitry that may be added to an integrated circuit to provide access to on-chip Test Access Ports (TAPs) specified by IEEE Std 1149.1TM-2001. The circuitry uses IEEE 1149.1-2001 as its foundation, providing complete backward compatibility, while aggressively adding features to support test and applications debug. It defines six classes of 1149.7 Test Access Ports (TAP.7s), T0-T5, with each class providing incremental capability, building on that of the lower level classes. Class T0 provides the behavior specified by 1149.1 from startup when there are multiple on-chip TAPs. Class T1 adds common debug functions and features to minimize power consumption. Class T2 adds operating modes that maximize scan performance. It also provides an optional hot-connection capability to prevent system corruption when a connection is made to a powered system. Class T3 supports operation in either a fourwire Series or Star Scan Topology. Class T4 provides for communication with either a two-pin or four-pin interface. The two-pin operation serializes 1149.1 transactions and provides for higher Test Clock rates. Class T5 adds the ability to perform data transfers concurrent with scan, supports utilization of functions other than scan, and provides control of TAP.7 pins to custom debug technologies in a manner that ensures current and future interoperability.<br />\n \t\t\t\t<br />\n The standard will define a link between IEEE 1149.1 interfaces in Debug and Test Systems (DTS) and IEEE 1149.1 (JTAG) interfaces in Target Systems (TS). The link defined by this standard introduces an additional layer between these legacy interfaces. This layer may be viewed as an adapter that provides new functionality and features while preserving all elements of the original IEEE 1149.1 (JTAG) interfaces. The standard will define the link behavior (including timing characteristics of signals), protocols, and functionality of the adapters deployed within the DTS and TS. The standard will not modify or create inconsistencies with IEEE 1149.1 (JTAG). The standard will define a superset of the IEEE 1149.1 specification and achieve compliance with IEEE Std 1149.1TM-2001.<br />\n The purpose of the standard is to define a debug and test interface that meets an expanding set of challenges facing Debug and Test Systems (many of which have emerged since the inception of the original IEEE Std 1149.1) while preserving the hardware and software investments of the many industries currently using IEEE Std 1149.1-2001. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture" -notes: "Inactive-Reserved" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …} #channels: Doctrine\ORM\PersistentCollection {#7628 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#7613 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7645 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1698706800 {#7292 : 2023-10-31 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1265756400 {#7318 : 2010-02-10 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1616626800 {#7316 : 2021-03-25 00:00:00.0 Europe/Paris (+01:00) } -edition: null -coreDocument: "1149.7" -bookCollection: "" -pageCount: 985 -documents: Doctrine\ORM\PersistentCollection {#7465 …} -favorites: Doctrine\ORM\PersistentCollection {#7500 …} } ] |
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| Attributes | [] |
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| Component | App\Twig\Components\ProductMostRecent {#107012 +product: App\Entity\Product\Product {#7311 #id: 10224 #code: "IEEE00003936" #attributes: Doctrine\ORM\PersistentCollection {#7701 …} #variants: Doctrine\ORM\PersistentCollection {#7744 …} #options: Doctrine\ORM\PersistentCollection {#7916 …} #associations: Doctrine\ORM\PersistentCollection {#7900 …} #createdAt: DateTime @1751038910 {#7274 : 2025-06-27 17:41:50.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754608190 {#7322 : 2025-08-08 01:09:50.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7922 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7921 #locale: "en_US" #translatable: App\Entity\Product\Product {#7311} #id: 35905 #name: "IEEE 1149.7:2009" #slug: "ieee-1149-7-2009-ieee00003936-241876" #description: """ New IEEE Standard - Inactive-Reserved.<br />\n This specification describes circuitry that may be added to an integrated circuit to provide access to on-chip Test Access Ports (TAPs) specified by IEEE Std 1149.1TM-2001. The circuitry uses IEEE 1149.1-2001 as its foundation, providing complete backward compatibility, while aggressively adding features to support test and applications debug. It defines six classes of 1149.7 Test Access Ports (TAP.7s), T0-T5, with each class providing incremental capability, building on that of the lower level classes. Class T0 provides the behavior specified by 1149.1 from startup when there are multiple on-chip TAPs. Class T1 adds common debug functions and features to minimize power consumption. Class T2 adds operating modes that maximize scan performance. It also provides an optional hot-connection capability to prevent system corruption when a connection is made to a powered system. Class T3 supports operation in either a fourwire Series or Star Scan Topology. Class T4 provides for communication with either a two-pin or four-pin interface. The two-pin operation serializes 1149.1 transactions and provides for higher Test Clock rates. Class T5 adds the ability to perform data transfers concurrent with scan, supports utilization of functions other than scan, and provides control of TAP.7 pins to custom debug technologies in a manner that ensures current and future interoperability.<br />\n \t\t\t\t<br />\n The standard will define a link between IEEE 1149.1 interfaces in Debug and Test Systems (DTS) and IEEE 1149.1 (JTAG) interfaces in Target Systems (TS). The link defined by this standard introduces an additional layer between these legacy interfaces. This layer may be viewed as an adapter that provides new functionality and features while preserving all elements of the original IEEE 1149.1 (JTAG) interfaces. The standard will define the link behavior (including timing characteristics of signals), protocols, and functionality of the adapters deployed within the DTS and TS. The standard will not modify or create inconsistencies with IEEE 1149.1 (JTAG). The standard will define a superset of the IEEE 1149.1 specification and achieve compliance with IEEE Std 1149.1TM-2001.<br />\n The purpose of the standard is to define a debug and test interface that meets an expanding set of challenges facing Debug and Test Systems (many of which have emerged since the inception of the original IEEE Std 1149.1) while preserving the hardware and software investments of the many industries currently using IEEE Std 1149.1-2001. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture" -notes: "Inactive-Reserved" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7534 …} #channels: Doctrine\ORM\PersistentCollection {#7628 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#7613 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7645 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7321 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1698706800 {#7292 : 2023-10-31 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1265756400 {#7318 : 2010-02-10 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: DateTime @1616626800 {#7316 : 2021-03-25 00:00:00.0 Europe/Paris (+01:00) } -edition: null -coreDocument: "1149.7" -bookCollection: "" -pageCount: 985 -documents: Doctrine\ORM\PersistentCollection {#7465 …} -favorites: Doctrine\ORM\PersistentCollection {#7500 …} } +label: "Most Recent" +icon: "check-xs" -mostRecentAttributeCode: "most_recent" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …} } |
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| ProductCard | App\Twig\Components\ProductCard | 150.0 MiB | 6.07 ms | |
|---|---|---|---|---|
| Input props | [ "product" => App\Entity\Product\Product {#128309 #id: 9152 #code: "IEEE00001728" #attributes: Doctrine\ORM\PersistentCollection {#128292 …} #variants: Doctrine\ORM\PersistentCollection {#128290 …} #options: Doctrine\ORM\PersistentCollection {#128285 …} #associations: Doctrine\ORM\PersistentCollection {#128287 …} #createdAt: DateTime @1751038014 {#128282 : 2025-06-27 17:26:54.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#128317 : 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#128303 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#128394 #locale: "en_US" #translatable: App\Entity\Product\Product {#128309} #id: 31617 #name: "IEEE 1149.1:2001 (R2008)" #slug: "ieee-1149-1-2001-r2008-ieee00001728-240804" #description: """ Revision Standard - Superseded.<br />\n Circuitry that may be built into an integrated circuit to assist in the test, maintenance, and support of assembled printed circuit boards is defined. The circuitry includes a standard interface through which instructions and test data are communicated. A set of test features is defined, including a boundary-scan register, such that the component is able to respond to a minimum set of instructions designed to assist with testing of assembled printed circuit boards.<br />\n \t\t\t\t<br />\n This standard defines test logic that can be included in an integrated circuit to provide standardized approaches to<br />\n — testing the interconnections between integrated circuits once they have been assembled onto a<br />\n printed circuit board or other substrate;<br />\n — testing the integrated circuit itself; and<br />\n — observing or modifying circuit activity during the component's normal operation. The test logic consists of a boundary-scan register and other building blocks and is accessed through a Test Access Port (TAP).<br />\n As technology has changed, the original 1149.1 standard does not address the new needs of the end users. The purpose of this PAR is to address these new needs in the IEEE 1149.1 standard. The intended users are silicon vendors, silicon designers, board and system electronic manufacturers and test equiment manufacturers. The benefits are additional capabilities and ease-of-use of 1149.1 for the current technology of mix-signal devices, differential logic and programmable devices. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard Test Access Port and Boundary Scan Architecture" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#128301 …} #channels: Doctrine\ORM\PersistentCollection {#128294 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#128298 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#128296 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#128311 …} -apiLastModifiedAt: DateTime @1754517600 {#128268 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#128316 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @995839200 {#128275 : 2001-07-23 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: DateTime @1206572400 {#128288 : 2008-03-27 00:00:00.0 Europe/Paris (+01:00) } -canceledAt: null -edition: null -coreDocument: "1149.1" -bookCollection: "" -pageCount: 212 -documents: Doctrine\ORM\PersistentCollection {#128307 …} -favorites: Doctrine\ORM\PersistentCollection {#128305 …} } "layout" => "vertical" "showPrice" => true "showStatusBadges" => true "additionalClasses" => "product__teaser--with-grey-border" "hasStretchedLink" => true "hoverType" => "shadow" "linkLabel" => "See more" ] |
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| Attributes | [] |
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| Component | App\Twig\Components\ProductCard {#128365 +product: App\Entity\Product\Product {#128309 #id: 9152 #code: "IEEE00001728" #attributes: Doctrine\ORM\PersistentCollection {#128292 …} #variants: Doctrine\ORM\PersistentCollection {#128290 …} #options: Doctrine\ORM\PersistentCollection {#128285 …} #associations: Doctrine\ORM\PersistentCollection {#128287 …} #createdAt: DateTime @1751038014 {#128282 : 2025-06-27 17:26:54.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#128317 : 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#128303 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#128394 #locale: "en_US" #translatable: App\Entity\Product\Product {#128309} #id: 31617 #name: "IEEE 1149.1:2001 (R2008)" #slug: "ieee-1149-1-2001-r2008-ieee00001728-240804" #description: """ Revision Standard - Superseded.<br />\n Circuitry that may be built into an integrated circuit to assist in the test, maintenance, and support of assembled printed circuit boards is defined. The circuitry includes a standard interface through which instructions and test data are communicated. A set of test features is defined, including a boundary-scan register, such that the component is able to respond to a minimum set of instructions designed to assist with testing of assembled printed circuit boards.<br />\n \t\t\t\t<br />\n This standard defines test logic that can be included in an integrated circuit to provide standardized approaches to<br />\n — testing the interconnections between integrated circuits once they have been assembled onto a<br />\n printed circuit board or other substrate;<br />\n — testing the integrated circuit itself; and<br />\n — observing or modifying circuit activity during the component's normal operation. The test logic consists of a boundary-scan register and other building blocks and is accessed through a Test Access Port (TAP).<br />\n As technology has changed, the original 1149.1 standard does not address the new needs of the end users. The purpose of this PAR is to address these new needs in the IEEE 1149.1 standard. The intended users are silicon vendors, silicon designers, board and system electronic manufacturers and test equiment manufacturers. The benefits are additional capabilities and ease-of-use of 1149.1 for the current technology of mix-signal devices, differential logic and programmable devices. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard Test Access Port and Boundary Scan Architecture" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#128301 …} #channels: Doctrine\ORM\PersistentCollection {#128294 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#128298 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#128296 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#128311 …} -apiLastModifiedAt: DateTime @1754517600 {#128268 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#128316 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @995839200 {#128275 : 2001-07-23 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: DateTime @1206572400 {#128288 : 2008-03-27 00:00:00.0 Europe/Paris (+01:00) } -canceledAt: null -edition: null -coreDocument: "1149.1" -bookCollection: "" -pageCount: 212 -documents: Doctrine\ORM\PersistentCollection {#128307 …} -favorites: Doctrine\ORM\PersistentCollection {#128305 …} } +layout: "vertical" +showPrice: true +showStatusBadges: true +additionalClasses: "product__teaser--with-grey-border" +linkLabel: "See more" +imageFilter: "product_thumbnail_teaser" +hasStretchedLink: true +backgroundColor: "white" +hoverType: "shadow" } |
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| ProductState | App\Twig\Components\ProductState | 150.0 MiB | 0.19 ms | |
|---|---|---|---|---|
| Input props | [ "product" => App\Entity\Product\Product {#128309 #id: 9152 #code: "IEEE00001728" #attributes: Doctrine\ORM\PersistentCollection {#128292 …} #variants: Doctrine\ORM\PersistentCollection {#128290 …} #options: Doctrine\ORM\PersistentCollection {#128285 …} #associations: Doctrine\ORM\PersistentCollection {#128287 …} #createdAt: DateTime @1751038014 {#128282 : 2025-06-27 17:26:54.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#128317 : 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#128303 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#128394 #locale: "en_US" #translatable: App\Entity\Product\Product {#128309} #id: 31617 #name: "IEEE 1149.1:2001 (R2008)" #slug: "ieee-1149-1-2001-r2008-ieee00001728-240804" #description: """ Revision Standard - Superseded.<br />\n Circuitry that may be built into an integrated circuit to assist in the test, maintenance, and support of assembled printed circuit boards is defined. The circuitry includes a standard interface through which instructions and test data are communicated. A set of test features is defined, including a boundary-scan register, such that the component is able to respond to a minimum set of instructions designed to assist with testing of assembled printed circuit boards.<br />\n \t\t\t\t<br />\n This standard defines test logic that can be included in an integrated circuit to provide standardized approaches to<br />\n — testing the interconnections between integrated circuits once they have been assembled onto a<br />\n printed circuit board or other substrate;<br />\n — testing the integrated circuit itself; and<br />\n — observing or modifying circuit activity during the component's normal operation. The test logic consists of a boundary-scan register and other building blocks and is accessed through a Test Access Port (TAP).<br />\n As technology has changed, the original 1149.1 standard does not address the new needs of the end users. The purpose of this PAR is to address these new needs in the IEEE 1149.1 standard. The intended users are silicon vendors, silicon designers, board and system electronic manufacturers and test equiment manufacturers. The benefits are additional capabilities and ease-of-use of 1149.1 for the current technology of mix-signal devices, differential logic and programmable devices. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard Test Access Port and Boundary Scan Architecture" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#128301 …} #channels: Doctrine\ORM\PersistentCollection {#128294 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#128298 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#128296 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#128311 …} -apiLastModifiedAt: DateTime @1754517600 {#128268 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#128316 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @995839200 {#128275 : 2001-07-23 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: DateTime @1206572400 {#128288 : 2008-03-27 00:00:00.0 Europe/Paris (+01:00) } -canceledAt: null -edition: null -coreDocument: "1149.1" -bookCollection: "" -pageCount: 212 -documents: Doctrine\ORM\PersistentCollection {#128307 …} -favorites: Doctrine\ORM\PersistentCollection {#128305 …} } ] |
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| Attributes | [ "showFullLabel" => false ] |
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| Component | App\Twig\Components\ProductState {#128398 +product: App\Entity\Product\Product {#128309 #id: 9152 #code: "IEEE00001728" #attributes: Doctrine\ORM\PersistentCollection {#128292 …} #variants: Doctrine\ORM\PersistentCollection {#128290 …} #options: Doctrine\ORM\PersistentCollection {#128285 …} #associations: Doctrine\ORM\PersistentCollection {#128287 …} #createdAt: DateTime @1751038014 {#128282 : 2025-06-27 17:26:54.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#128317 : 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#128303 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#128394 #locale: "en_US" #translatable: App\Entity\Product\Product {#128309} #id: 31617 #name: "IEEE 1149.1:2001 (R2008)" #slug: "ieee-1149-1-2001-r2008-ieee00001728-240804" #description: """ Revision Standard - Superseded.<br />\n Circuitry that may be built into an integrated circuit to assist in the test, maintenance, and support of assembled printed circuit boards is defined. The circuitry includes a standard interface through which instructions and test data are communicated. A set of test features is defined, including a boundary-scan register, such that the component is able to respond to a minimum set of instructions designed to assist with testing of assembled printed circuit boards.<br />\n \t\t\t\t<br />\n This standard defines test logic that can be included in an integrated circuit to provide standardized approaches to<br />\n — testing the interconnections between integrated circuits once they have been assembled onto a<br />\n printed circuit board or other substrate;<br />\n — testing the integrated circuit itself; and<br />\n — observing or modifying circuit activity during the component's normal operation. The test logic consists of a boundary-scan register and other building blocks and is accessed through a Test Access Port (TAP).<br />\n As technology has changed, the original 1149.1 standard does not address the new needs of the end users. The purpose of this PAR is to address these new needs in the IEEE 1149.1 standard. The intended users are silicon vendors, silicon designers, board and system electronic manufacturers and test equiment manufacturers. The benefits are additional capabilities and ease-of-use of 1149.1 for the current technology of mix-signal devices, differential logic and programmable devices. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard Test Access Port and Boundary Scan Architecture" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#128301 …} #channels: Doctrine\ORM\PersistentCollection {#128294 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#128298 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#128296 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#128311 …} -apiLastModifiedAt: DateTime @1754517600 {#128268 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#128316 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @995839200 {#128275 : 2001-07-23 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: DateTime @1206572400 {#128288 : 2008-03-27 00:00:00.0 Europe/Paris (+01:00) } -canceledAt: null -edition: null -coreDocument: "1149.1" -bookCollection: "" -pageCount: 212 -documents: Doctrine\ORM\PersistentCollection {#128307 …} -favorites: Doctrine\ORM\PersistentCollection {#128305 …} } +appearance: "state-suspended" +labels: [ "Superseded" ] -stateAttributeCode: "state" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …} } |
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| ProductMostRecent | App\Twig\Components\ProductMostRecent | 150.0 MiB | 0.70 ms | |
|---|---|---|---|---|
| Input props | [ "product" => App\Entity\Product\Product {#128309 #id: 9152 #code: "IEEE00001728" #attributes: Doctrine\ORM\PersistentCollection {#128292 …} #variants: Doctrine\ORM\PersistentCollection {#128290 …} #options: Doctrine\ORM\PersistentCollection {#128285 …} #associations: Doctrine\ORM\PersistentCollection {#128287 …} #createdAt: DateTime @1751038014 {#128282 : 2025-06-27 17:26:54.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#128317 : 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#128303 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#128394 #locale: "en_US" #translatable: App\Entity\Product\Product {#128309} #id: 31617 #name: "IEEE 1149.1:2001 (R2008)" #slug: "ieee-1149-1-2001-r2008-ieee00001728-240804" #description: """ Revision Standard - Superseded.<br />\n Circuitry that may be built into an integrated circuit to assist in the test, maintenance, and support of assembled printed circuit boards is defined. The circuitry includes a standard interface through which instructions and test data are communicated. A set of test features is defined, including a boundary-scan register, such that the component is able to respond to a minimum set of instructions designed to assist with testing of assembled printed circuit boards.<br />\n \t\t\t\t<br />\n This standard defines test logic that can be included in an integrated circuit to provide standardized approaches to<br />\n — testing the interconnections between integrated circuits once they have been assembled onto a<br />\n printed circuit board or other substrate;<br />\n — testing the integrated circuit itself; and<br />\n — observing or modifying circuit activity during the component's normal operation. The test logic consists of a boundary-scan register and other building blocks and is accessed through a Test Access Port (TAP).<br />\n As technology has changed, the original 1149.1 standard does not address the new needs of the end users. The purpose of this PAR is to address these new needs in the IEEE 1149.1 standard. The intended users are silicon vendors, silicon designers, board and system electronic manufacturers and test equiment manufacturers. The benefits are additional capabilities and ease-of-use of 1149.1 for the current technology of mix-signal devices, differential logic and programmable devices. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard Test Access Port and Boundary Scan Architecture" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#128301 …} #channels: Doctrine\ORM\PersistentCollection {#128294 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#128298 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#128296 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#128311 …} -apiLastModifiedAt: DateTime @1754517600 {#128268 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#128316 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @995839200 {#128275 : 2001-07-23 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: DateTime @1206572400 {#128288 : 2008-03-27 00:00:00.0 Europe/Paris (+01:00) } -canceledAt: null -edition: null -coreDocument: "1149.1" -bookCollection: "" -pageCount: 212 -documents: Doctrine\ORM\PersistentCollection {#128307 …} -favorites: Doctrine\ORM\PersistentCollection {#128305 …} } ] |
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| Attributes | [] |
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| Component | App\Twig\Components\ProductMostRecent {#128476 +product: App\Entity\Product\Product {#128309 #id: 9152 #code: "IEEE00001728" #attributes: Doctrine\ORM\PersistentCollection {#128292 …} #variants: Doctrine\ORM\PersistentCollection {#128290 …} #options: Doctrine\ORM\PersistentCollection {#128285 …} #associations: Doctrine\ORM\PersistentCollection {#128287 …} #createdAt: DateTime @1751038014 {#128282 : 2025-06-27 17:26:54.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#128317 : 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#128303 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#128394 #locale: "en_US" #translatable: App\Entity\Product\Product {#128309} #id: 31617 #name: "IEEE 1149.1:2001 (R2008)" #slug: "ieee-1149-1-2001-r2008-ieee00001728-240804" #description: """ Revision Standard - Superseded.<br />\n Circuitry that may be built into an integrated circuit to assist in the test, maintenance, and support of assembled printed circuit boards is defined. The circuitry includes a standard interface through which instructions and test data are communicated. A set of test features is defined, including a boundary-scan register, such that the component is able to respond to a minimum set of instructions designed to assist with testing of assembled printed circuit boards.<br />\n \t\t\t\t<br />\n This standard defines test logic that can be included in an integrated circuit to provide standardized approaches to<br />\n — testing the interconnections between integrated circuits once they have been assembled onto a<br />\n printed circuit board or other substrate;<br />\n — testing the integrated circuit itself; and<br />\n — observing or modifying circuit activity during the component's normal operation. The test logic consists of a boundary-scan register and other building blocks and is accessed through a Test Access Port (TAP).<br />\n As technology has changed, the original 1149.1 standard does not address the new needs of the end users. The purpose of this PAR is to address these new needs in the IEEE 1149.1 standard. The intended users are silicon vendors, silicon designers, board and system electronic manufacturers and test equiment manufacturers. The benefits are additional capabilities and ease-of-use of 1149.1 for the current technology of mix-signal devices, differential logic and programmable devices. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard Test Access Port and Boundary Scan Architecture" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#128301 …} #channels: Doctrine\ORM\PersistentCollection {#128294 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7309 …} #reviews: Doctrine\ORM\PersistentCollection {#128298 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#128296 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7324 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#128311 …} -apiLastModifiedAt: DateTime @1754517600 {#128268 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#128316 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @995839200 {#128275 : 2001-07-23 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: DateTime @1206572400 {#128288 : 2008-03-27 00:00:00.0 Europe/Paris (+01:00) } -canceledAt: null -edition: null -coreDocument: "1149.1" -bookCollection: "" -pageCount: 212 -documents: Doctrine\ORM\PersistentCollection {#128307 …} -favorites: Doctrine\ORM\PersistentCollection {#128305 …} } +label: "Historical" +icon: "historical" -mostRecentAttributeCode: "most_recent" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …} } |
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