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sylius_add_to_cart
- cartItem
  - quantity
  - variant
    - format
    - languages
    - multi_user
    - red_line
- _token

sylius_add_to_cart

Form type:

"Sylius\Bundle\CoreBundle\Form\Type\Order\AddToCartType"

Errors

This form has no errors.

Default Data

Property

Value

Model Format

same as normalized format

Normalized Format

Sylius\Bundle\OrderBundle\Controller\AddToCartCommand {#113463
  -cart: App\Entity\Order\Order {#13330 …}
  -cartItem: App\Entity\Order\OrderItem {#113451
    #id: null
    #order: null
    #quantity: 1
    #unitPrice: 0
    #originalUnitPrice: 0
    #total: 0
    #immutable: false
    #units: Doctrine\Common\Collections\ArrayCollection {#113476 …}
    #unitsTotal: 0
    #adjustments: Doctrine\Common\Collections\ArrayCollection {#113475 …}
    #adjustmentsTotal: 0
    #version: 1
    #variant: App\Entity\Product\ProductVariant {#8099
      #id: 4543
      #code: "IEEE00004256PDF"
      #product: App\Entity\Product\Product {#7310
        #id: 10370
        #code: "IEEE00004256"
        #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
        #variants: Doctrine\ORM\PersistentCollection {#7743 …}
        #options: Doctrine\ORM\PersistentCollection {#7915
          #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …}
          #initialized: true
          -snapshot: [ …4]
          -owner: App\Entity\Product\Product {#7310}
          -association: [ …21]
          -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …}
          -backRefFieldName: null
          -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#260654 …}
          -isDirty: false
        }
        #associations: Doctrine\ORM\PersistentCollection {#7899 …}
        #createdAt: DateTime @1751039020 {#7274
          date: 2025-06-27 17:43:40.0 Europe/Paris (+02:00)
        }
        #updatedAt: DateTime @1754607611 {#7322
          date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
        }
        #enabled: true
        #translations: Doctrine\ORM\PersistentCollection {#7921 …}
        #translationsCache: [
          "en_US" => App\Entity\Product\ProductTranslation {#7920
            #locale: "en_US"
            #translatable: App\Entity\Product\Product {#7310}
            #id: 36489
            #name: "IEEE/IEC 62530:2007"
            #slug: "ieee-iec-62530-2007-ieee00004256-242022"
            #description: """
              New IEEE Standard - Superseded.<br />\n
              This standard provides a set of extensions to the IEEE 1364™ Verilog® hardware<br />\n
              description language (HDL) to aid in the creation and verification of abstract architectural level<br />\n
              models. It also includes design specification methods, embedded assertions language, testbench<br />\n
              language including coverage and an assertions application programming interface (API), and a<br />\n
              direct programming interface (DPI). This standard enables a productivity boost in design and<br />\n
              validation and covers design, simulation, validation, and formal assertion-based verification flows.<br />\n
              \t\t\t\t<br />\n
              This standard specifies extensions for a higher level of abstraction for modeling and verification with the<br />\n
              Verilog® hardware description language (HDL). These additions extend Verilog into the systems space and<br />\n
              the verification space. SystemVerilog is built on top of IEEE Std 1364™1 for the Verilog HDL. This<br />\n
              standard includes design specification methods, embedded assertions language, testbench language<br />\n
              including coverage and assertions application programming interface (API), and a direct programming<br />\n
              interface (DPI).<br />\n
              Throughout this standard, the following terms apply:<br />\n
              — Verilog refers to IEEE Std 1364 for the Verilog HDL.<br />\n
              — Verilog-2001 refers to IEEE Std 1364-2001 [B4]2 for the Verilog HDL.<br />\n
              — Verilog-1995 refers to IEEE Std 1364-1995 [B3] for the Verilog HDL.<br />\n
              — SystemVerilog refers to the extensions to the Verilog standard (IEEE Std 1364) as defined in this<br />\n
              standard.<br />\n
              SystemVerilog adds extended and new constructs to Verilog, including the following:<br />\n
              — Extensions to data types for better encapsulation and compactness of code and for tighter<br />\n
              specification<br />\n
              — C data types: int, typedef, struct, union, enum<br />\n
              — Other data types: bounded queues, logic (0, 1, X, Z) and bit (0, 1), tagged unions for safety<br />\n
              — Dynamic data types: string, classes, dynamic queues, dynamic arrays, associative arrays<br />\n
              including automatic memory management freeing users from deallocation issues<br />\n
              — Dynamic casting and bit-stream casting<br />\n
              — Automatic/static specification on a per-variable-instance basis<br />\n
              — Extended operators for concise description<br />\n
              — Wild equality and inequality<br />\n
              — Built-in methods to extend the language<br />\n
              — Operator overloading<br />\n
              — Streaming operators<br />\n
              — Set membership<br />\n
              — Extended procedural statements<br />\n
              — Pattern matching on selection statements for use with tagged unions<br />\n
              — Enhanced loop statements plus the foreach statement<br />\n
              — C-like jump statements: return, break, continue<br />\n
              — final blocks that execute at the end of simulation (inverse of initial)<br />\n
              — Extended event control and sequence events<br />\n
              — Enhanced process control<br />\n
              — Extensions to always blocks to include synthesis consistent simulation semantics<br />\n
              — Extensions to fork…join to model pipelines and for enhanced process control<br />\n
              — Fine-grain process control<br />\n
              — Enhanced tasks and functions<br />\n
              — C-like void functions<br />\n
              — Pass by reference<br />\n
              — Default arguments<br />\n
              — Argument binding by name<br />\n
              — Optional arguments<br />\n
              — Import/export functions for DPI<br />\n
              — Classes: object-oriented mechanism that provides abstraction, encapsulation, and safe pointer<br />\n
              capabilities<br />\n
              — Automated testbench support with random constraints<br />\n
              — Interprocess communication synchronization<br />\n
              — Semaphores<br />\n
              — Mailboxes<br />\n
              — Event extensions, event variables, and event sequencing<br />\n
              — Clarification and extension of the scheduling semantics<br />\n
              — Cycle-based functionality: clocking blocks and cycle-based attributes that help reduce development,<br />\n
              ease maintainability, and promote reusability<br />\n
              — Cycle-based signal drives and samples<br />\n
              — Synchronous samples<br />\n
              SystemVerilog is built on top of IEEE Std 1364. SystemVerilog improves the productivity, readability, and<br />\n
              reusability of Verilog-based code. The language enhancements in SystemVerilog provide more concise<br />\n
              hardware descriptions, while still providing an easy route with existing tools into current hardware<br />\n
              implementation flows. The enhancements also provide extensive support for directed and constrainedrandom<br />\n
              testbench development, coverage-driven verification, and assertion-based verification.<br />\n
              1Information on references can be found in Clause 2.<br />\n
              2The numbers in brackets correspond to the numbers in the bibliography in Annex K.<br />\n
              — Race-free program context<br />\n
              — Assertion mechanism for verifying design intent and functional coverage intent<br />\n
              — Property and sequence declarations<br />\n
              — Assertions and coverage statements with action blocks<br />\n
              — Extended hierarchy support<br />\n
              — Packages for declaration encapsulation with import for controlled access<br />\n
              — Compilation-unit scope nested modules and extern modules for separate compilation support<br />\n
              — Extension of port declarations to support interfaces, events, and variables<br />\n
              — $root to provide unambiguous access using hierarchical references<br />\n
              — Interfaces to encapsulate communication and facilitate communication-oriented design<br />\n
              — Functional coverage<br />\n
              — DPI for clean, efficient interoperation with other languages (C provided)<br />\n
              — Assertion API<br />\n
              — Coverage API<br />\n
              — Data read API<br />\n
              — Verilog procedural interface (VPI) extensions for SystemVerilog constructs<br />\n
              — Concurrent assertion formal semantics
              """
            #metaKeywords: null
            #metaDescription: null
            #shortDescription: "IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language"
            -notes: "Superseded"
          }
        ]
        #currentLocale: "en_US"
        #currentTranslation: null
        #fallbackLocale: "en_US"
        #variantSelectionMethod: "match"
        #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
        #channels: Doctrine\ORM\PersistentCollection {#7627 …}
        #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
        #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
        #averageRating: 0.0
        #images: Doctrine\ORM\PersistentCollection {#7644 …}
        -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
        -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
        -apiLastModifiedAt: DateTime @1754517600 {#7317
          date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
        }
        -lastUpdatedAt: DateTime @1578006000 {#7292
          date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
        }
        -author: ""
        -publishedAt: DateTime @1197154800 {#7318
          date: 2007-12-09 00:00:00.0 Europe/Paris (+01:00)
        }
        -releasedAt: null
        -confirmedAt: null
        -canceledAt: null
        -edition: null
        -coreDocument: "62530"
        -bookCollection: ""
        -pageCount: 668
        -documents: Doctrine\ORM\PersistentCollection {#7464 …}
        -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
      }
      #optionValues: Doctrine\ORM\PersistentCollection {#8315 …}
      #position: 0
      #createdAt: DateTime @1751041198 {#7283
        date: 2025-06-27 18:19:58.0 Europe/Paris (+02:00)
      }
      #updatedAt: DateTime @1755611983 {#8116
        date: 2025-08-19 15:59:43.0 Europe/Paris (+02:00)
      }
      #enabled: true
      #translations: Doctrine\ORM\PersistentCollection {#8259 …}
      #translationsCache: [
        "en_US" => App\Entity\Product\ProductVariantTranslation {#93321
          #locale: "en_US"
          #translatable: App\Entity\Product\ProductVariant {#8099}
          #id: 4561
          #name: null
          -shortDescription: null
          -description: null
          -notes: null
          -shippingInformation: "Instant download"
        }
      ]
      #currentLocale: "en_US"
      #currentTranslation: null
      #fallbackLocale: "en_US"
      #version: 9
      #onHold: 0
      #onHand: 0
      #tracked: false
      #weight: 0.0
      #width: null
      #height: null
      #depth: null
      #taxCategory: Proxies\__CG__\App\Entity\Taxation\TaxCategory {#8131 …}
      #shippingCategory: null
      #channelPricings: Doctrine\ORM\PersistentCollection {#8293 …}
      #shippingRequired: true
      #images: Doctrine\ORM\PersistentCollection {#8290 …}
      -apiLastModifiedAt: DateTime @1753740000 {#8098
        date: 2025-07-29 00:00:00.0 Europe/Paris (+02:00)
      }
      -publishedAt: null
      -isbn: "9-7807-3815-7269"
      -ean: "9780738157269"
      -numberOfUsers: 1
      -physicalProduct: false
      -downloadableImmediately: true
      -downloadable: true
      -drmViewerUrl: "https://online-viewer.normadoc.com/8xbJn4"
      -sellable: true
      -documents: Doctrine\ORM\PersistentCollection {#8127 …}
      -drmTokens: Doctrine\ORM\PersistentCollection {#8119 …}
      -enabledForSubscribers: true
      -currentAreaContext: null
    }
    #productName: null
    #variantName: null
  }
}

View Format

same as normalized format

Submitted Data

This form was not submitted.

Passed Options

Option	Passed Value	Resolved Value
data	Sylius\Bundle\OrderBundle\Controller\AddToCartCommand {#113463-cart: App\Entity\Order\Order {#13330 …} -cartItem: App\Entity\Order\OrderItem {#113451 #id: null #order: null #quantity: 1 #unitPrice: 0 #originalUnitPrice: 0 #total: 0 #immutable: false #units: Doctrine\Common\Collections\ArrayCollection {#113476 …} #unitsTotal: 0 #adjustments: Doctrine\Common\Collections\ArrayCollection {#113475 …} #adjustmentsTotal: 0 #version: 1 #variant: App\Entity\Product\ProductVariant {#8099 #id: 4543 #code: "IEEE00004256PDF" #product: App\Entity\Product\Product {#7310 #id: 10370 #code: "IEEE00004256" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …} #initialized: true -snapshot: [ …4] -owner: App\Entity\Product\Product {#7310} -association: [ …21] -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …} -backRefFieldName: null -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#260654 …} -isDirty: false } #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751039020 {#7274 date: 2025-06-27 17:43:40.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#7322 date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 36489 #name: "IEEE/IEC 62530:2007" #slug: "ieee-iec-62530-2007-ieee00004256-242022" #description: """ New IEEE Standard - Superseded.<br />\n This standard provides a set of extensions to the IEEE 1364™ Verilog® hardware<br />\n description language (HDL) to aid in the creation and verification of abstract architectural level<br />\n models. It also includes design specification methods, embedded assertions language, testbench<br />\n language including coverage and an assertions application programming interface (API), and a<br />\n direct programming interface (DPI). This standard enables a productivity boost in design and<br />\n validation and covers design, simulation, validation, and formal assertion-based verification flows.<br />\n \t\t\t\t<br />\n This standard specifies extensions for a higher level of abstraction for modeling and verification with the<br />\n Verilog® hardware description language (HDL). These additions extend Verilog into the systems space and<br />\n the verification space. SystemVerilog is built on top of IEEE Std 1364™1 for the Verilog HDL. This<br />\n standard includes design specification methods, embedded assertions language, testbench language<br />\n including coverage and assertions application programming interface (API), and a direct programming<br />\n interface (DPI).<br />\n Throughout this standard, the following terms apply:<br />\n — Verilog refers to IEEE Std 1364 for the Verilog HDL.<br />\n — Verilog-2001 refers to IEEE Std 1364-2001 [B4]2 for the Verilog HDL.<br />\n — Verilog-1995 refers to IEEE Std 1364-1995 [B3] for the Verilog HDL.<br />\n — SystemVerilog refers to the extensions to the Verilog standard (IEEE Std 1364) as defined in this<br />\n standard.<br />\n SystemVerilog adds extended and new constructs to Verilog, including the following:<br />\n — Extensions to data types for better encapsulation and compactness of code and for tighter<br />\n specification<br />\n — C data types: int, typedef, struct, union, enum<br />\n — Other data types: bounded queues, logic (0, 1, X, Z) and bit (0, 1), tagged unions for safety<br />\n — Dynamic data types: string, classes, dynamic queues, dynamic arrays, associative arrays<br />\n including automatic memory management freeing users from deallocation issues<br />\n — Dynamic casting and bit-stream casting<br />\n — Automatic/static specification on a per-variable-instance basis<br />\n — Extended operators for concise description<br />\n — Wild equality and inequality<br />\n — Built-in methods to extend the language<br />\n — Operator overloading<br />\n — Streaming operators<br />\n — Set membership<br />\n — Extended procedural statements<br />\n — Pattern matching on selection statements for use with tagged unions<br />\n — Enhanced loop statements plus the foreach statement<br />\n — C-like jump statements: return, break, continue<br />\n — final blocks that execute at the end of simulation (inverse of initial)<br />\n — Extended event control and sequence events<br />\n — Enhanced process control<br />\n — Extensions to always blocks to include synthesis consistent simulation semantics<br />\n — Extensions to fork…join to model pipelines and for enhanced process control<br />\n — Fine-grain process control<br />\n — Enhanced tasks and functions<br />\n — C-like void functions<br />\n — Pass by reference<br />\n — Default arguments<br />\n — Argument binding by name<br />\n — Optional arguments<br />\n — Import/export functions for DPI<br />\n — Classes: object-oriented mechanism that provides abstraction, encapsulation, and safe pointer<br />\n capabilities<br />\n — Automated testbench support with random constraints<br />\n — Interprocess communication synchronization<br />\n — Semaphores<br />\n — Mailboxes<br />\n — Event extensions, event variables, and event sequencing<br />\n — Clarification and extension of the scheduling semantics<br />\n — Cycle-based functionality: clocking blocks and cycle-based attributes that help reduce development,<br />\n ease maintainability, and promote reusability<br />\n — Cycle-based signal drives and samples<br />\n — Synchronous samples<br />\n SystemVerilog is built on top of IEEE Std 1364. SystemVerilog improves the productivity, readability, and<br />\n reusability of Verilog-based code. The language enhancements in SystemVerilog provide more concise<br />\n hardware descriptions, while still providing an easy route with existing tools into current hardware<br />\n implementation flows. The enhancements also provide extensive support for directed and constrainedrandom<br />\n testbench development, coverage-driven verification, and assertion-based verification.<br />\n 1Information on references can be found in Clause 2.<br />\n 2The numbers in brackets correspond to the numbers in the bibliography in Annex K.<br />\n — Race-free program context<br />\n — Assertion mechanism for verifying design intent and functional coverage intent<br />\n — Property and sequence declarations<br />\n — Assertions and coverage statements with action blocks<br />\n — Extended hierarchy support<br />\n — Packages for declaration encapsulation with import for controlled access<br />\n — Compilation-unit scope nested modules and extern modules for separate compilation support<br />\n — Extension of port declarations to support interfaces, events, and variables<br />\n — $root to provide unambiguous access using hierarchical references<br />\n — Interfaces to encapsulate communication and facilitate communication-oriented design<br />\n — Functional coverage<br />\n — DPI for clean, efficient interoperation with other languages (C provided)<br />\n — Assertion API<br />\n — Coverage API<br />\n — Data read API<br />\n — Verilog procedural interface (VPI) extensions for SystemVerilog constructs<br />\n — Concurrent assertion formal semantics """ #metaKeywords: null #metaDescription: null #shortDescription: "IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1197154800 {#7318 date: 2007-12-09 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "62530" -bookCollection: "" -pageCount: 668 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } #optionValues: Doctrine\ORM\PersistentCollection {#8315 …} #position: 0 #createdAt: DateTime @1751041198 {#7283 date: 2025-06-27 18:19:58.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1755611983 {#8116 date: 2025-08-19 15:59:43.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#8259 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductVariantTranslation {#93321 #locale: "en_US" #translatable: App\Entity\Product\ProductVariant {#8099} #id: 4561 #name: null -shortDescription: null -description: null -notes: null -shippingInformation: "Instant download" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #version: 9 #onHold: 0 #onHand: 0 #tracked: false #weight: 0.0 #width: null #height: null #depth: null #taxCategory: Proxies\__CG__\App\Entity\Taxation\TaxCategory {#8131 …} #shippingCategory: null #channelPricings: Doctrine\ORM\PersistentCollection {#8293 …} #shippingRequired: true #images: Doctrine\ORM\PersistentCollection {#8290 …} -apiLastModifiedAt: DateTime @1753740000 {#8098 date: 2025-07-29 00:00:00.0 Europe/Paris (+02:00) } -publishedAt: null -isbn: "9-7807-3815-7269" -ean: "9780738157269" -numberOfUsers: 1 -physicalProduct: false -downloadableImmediately: true -downloadable: true -drmViewerUrl: "https://online-viewer.normadoc.com/8xbJn4" -sellable: true -documents: Doctrine\ORM\PersistentCollection {#8127 …} -drmTokens: Doctrine\ORM\PersistentCollection {#8119 …} -enabledForSubscribers: true -currentAreaContext: null } #productName: null #variantName: null }}	same as passed value
product	App\Entity\Product\Product {#7310#id: 10370 #code: "IEEE00004256" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …} #initialized: true -snapshot: [ …4] -owner: App\Entity\Product\Product {#7310} -association: [ …21] -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …} -backRefFieldName: null -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#260654 …} -isDirty: false } #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751039020 {#7274 date: 2025-06-27 17:43:40.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#7322 date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 36489 #name: "IEEE/IEC 62530:2007" #slug: "ieee-iec-62530-2007-ieee00004256-242022" #description: """ New IEEE Standard - Superseded.<br />\n This standard provides a set of extensions to the IEEE 1364™ Verilog® hardware<br />\n description language (HDL) to aid in the creation and verification of abstract architectural level<br />\n models. It also includes design specification methods, embedded assertions language, testbench<br />\n language including coverage and an assertions application programming interface (API), and a<br />\n direct programming interface (DPI). This standard enables a productivity boost in design and<br />\n validation and covers design, simulation, validation, and formal assertion-based verification flows.<br />\n \t\t\t\t<br />\n This standard specifies extensions for a higher level of abstraction for modeling and verification with the<br />\n Verilog® hardware description language (HDL). These additions extend Verilog into the systems space and<br />\n the verification space. SystemVerilog is built on top of IEEE Std 1364™1 for the Verilog HDL. This<br />\n standard includes design specification methods, embedded assertions language, testbench language<br />\n including coverage and assertions application programming interface (API), and a direct programming<br />\n interface (DPI).<br />\n Throughout this standard, the following terms apply:<br />\n — Verilog refers to IEEE Std 1364 for the Verilog HDL.<br />\n — Verilog-2001 refers to IEEE Std 1364-2001 [B4]2 for the Verilog HDL.<br />\n — Verilog-1995 refers to IEEE Std 1364-1995 [B3] for the Verilog HDL.<br />\n — SystemVerilog refers to the extensions to the Verilog standard (IEEE Std 1364) as defined in this<br />\n standard.<br />\n SystemVerilog adds extended and new constructs to Verilog, including the following:<br />\n — Extensions to data types for better encapsulation and compactness of code and for tighter<br />\n specification<br />\n — C data types: int, typedef, struct, union, enum<br />\n — Other data types: bounded queues, logic (0, 1, X, Z) and bit (0, 1), tagged unions for safety<br />\n — Dynamic data types: string, classes, dynamic queues, dynamic arrays, associative arrays<br />\n including automatic memory management freeing users from deallocation issues<br />\n — Dynamic casting and bit-stream casting<br />\n — Automatic/static specification on a per-variable-instance basis<br />\n — Extended operators for concise description<br />\n — Wild equality and inequality<br />\n — Built-in methods to extend the language<br />\n — Operator overloading<br />\n — Streaming operators<br />\n — Set membership<br />\n — Extended procedural statements<br />\n — Pattern matching on selection statements for use with tagged unions<br />\n — Enhanced loop statements plus the foreach statement<br />\n — C-like jump statements: return, break, continue<br />\n — final blocks that execute at the end of simulation (inverse of initial)<br />\n — Extended event control and sequence events<br />\n — Enhanced process control<br />\n — Extensions to always blocks to include synthesis consistent simulation semantics<br />\n — Extensions to fork…join to model pipelines and for enhanced process control<br />\n — Fine-grain process control<br />\n — Enhanced tasks and functions<br />\n — C-like void functions<br />\n — Pass by reference<br />\n — Default arguments<br />\n — Argument binding by name<br />\n — Optional arguments<br />\n — Import/export functions for DPI<br />\n — Classes: object-oriented mechanism that provides abstraction, encapsulation, and safe pointer<br />\n capabilities<br />\n — Automated testbench support with random constraints<br />\n — Interprocess communication synchronization<br />\n — Semaphores<br />\n — Mailboxes<br />\n — Event extensions, event variables, and event sequencing<br />\n — Clarification and extension of the scheduling semantics<br />\n — Cycle-based functionality: clocking blocks and cycle-based attributes that help reduce development,<br />\n ease maintainability, and promote reusability<br />\n — Cycle-based signal drives and samples<br />\n — Synchronous samples<br />\n SystemVerilog is built on top of IEEE Std 1364. SystemVerilog improves the productivity, readability, and<br />\n reusability of Verilog-based code. The language enhancements in SystemVerilog provide more concise<br />\n hardware descriptions, while still providing an easy route with existing tools into current hardware<br />\n implementation flows. The enhancements also provide extensive support for directed and constrainedrandom<br />\n testbench development, coverage-driven verification, and assertion-based verification.<br />\n 1Information on references can be found in Clause 2.<br />\n 2The numbers in brackets correspond to the numbers in the bibliography in Annex K.<br />\n — Race-free program context<br />\n — Assertion mechanism for verifying design intent and functional coverage intent<br />\n — Property and sequence declarations<br />\n — Assertions and coverage statements with action blocks<br />\n — Extended hierarchy support<br />\n — Packages for declaration encapsulation with import for controlled access<br />\n — Compilation-unit scope nested modules and extern modules for separate compilation support<br />\n — Extension of port declarations to support interfaces, events, and variables<br />\n — $root to provide unambiguous access using hierarchical references<br />\n — Interfaces to encapsulate communication and facilitate communication-oriented design<br />\n — Functional coverage<br />\n — DPI for clean, efficient interoperation with other languages (C provided)<br />\n — Assertion API<br />\n — Coverage API<br />\n — Data read API<br />\n — Verilog procedural interface (VPI) extensions for SystemVerilog constructs<br />\n — Concurrent assertion formal semantics """ #metaKeywords: null #metaDescription: null #shortDescription: "IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1197154800 {#7318 date: 2007-12-09 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "62530" -bookCollection: "" -pageCount: 668 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …}}	same as passed value

Option

Passed Value

Resolved Value

data

Sylius\Bundle\OrderBundle\Controller\AddToCartCommand {#113463
  -cart: App\Entity\Order\Order {#13330 …}
  -cartItem: App\Entity\Order\OrderItem {#113451
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    #order: null
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    #unitPrice: 0
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    #total: 0
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    #units: Doctrine\Common\Collections\ArrayCollection {#113476 …}
    #unitsTotal: 0
    #adjustments: Doctrine\Common\Collections\ArrayCollection {#113475 …}
    #adjustmentsTotal: 0
    #version: 1
    #variant: App\Entity\Product\ProductVariant {#8099
      #id: 4543
      #code: "IEEE00004256PDF"
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        #code: "IEEE00004256"
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        #options: Doctrine\ORM\PersistentCollection {#7915
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          #initialized: true
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          -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#260654 …}
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          "en_US" => App\Entity\Product\ProductTranslation {#7920
            #locale: "en_US"
            #translatable: App\Entity\Product\Product {#7310}
            #id: 36489
            #name: "IEEE/IEC 62530:2007"
            #slug: "ieee-iec-62530-2007-ieee00004256-242022"
            #description: """
              New IEEE Standard - Superseded.<br />\n
              This standard provides a set of extensions to the IEEE 1364™ Verilog® hardware<br />\n
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              models. It also includes design specification methods, embedded assertions language, testbench<br />\n
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              \t\t\t\t<br />\n
              This standard specifies extensions for a higher level of abstraction for modeling and verification with the<br />\n
              Verilog® hardware description language (HDL). These additions extend Verilog into the systems space and<br />\n
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              standard includes design specification methods, embedded assertions language, testbench language<br />\n
              including coverage and assertions application programming interface (API), and a direct programming<br />\n
              interface (DPI).<br />\n
              Throughout this standard, the following terms apply:<br />\n
              — Verilog refers to IEEE Std 1364 for the Verilog HDL.<br />\n
              — Verilog-2001 refers to IEEE Std 1364-2001 [B4]2 for the Verilog HDL.<br />\n
              — Verilog-1995 refers to IEEE Std 1364-1995 [B3] for the Verilog HDL.<br />\n
              — SystemVerilog refers to the extensions to the Verilog standard (IEEE Std 1364) as defined in this<br />\n
              standard.<br />\n
              SystemVerilog adds extended and new constructs to Verilog, including the following:<br />\n
              — Extensions to data types for better encapsulation and compactness of code and for tighter<br />\n
              specification<br />\n
              — C data types: int, typedef, struct, union, enum<br />\n
              — Other data types: bounded queues, logic (0, 1, X, Z) and bit (0, 1), tagged unions for safety<br />\n
              — Dynamic data types: string, classes, dynamic queues, dynamic arrays, associative arrays<br />\n
              including automatic memory management freeing users from deallocation issues<br />\n
              — Dynamic casting and bit-stream casting<br />\n
              — Automatic/static specification on a per-variable-instance basis<br />\n
              — Extended operators for concise description<br />\n
              — Wild equality and inequality<br />\n
              — Built-in methods to extend the language<br />\n
              — Operator overloading<br />\n
              — Streaming operators<br />\n
              — Set membership<br />\n
              — Extended procedural statements<br />\n
              — Pattern matching on selection statements for use with tagged unions<br />\n
              — Enhanced loop statements plus the foreach statement<br />\n
              — C-like jump statements: return, break, continue<br />\n
              — final blocks that execute at the end of simulation (inverse of initial)<br />\n
              — Extended event control and sequence events<br />\n
              — Enhanced process control<br />\n
              — Extensions to always blocks to include synthesis consistent simulation semantics<br />\n
              — Extensions to fork…join to model pipelines and for enhanced process control<br />\n
              — Fine-grain process control<br />\n
              — Enhanced tasks and functions<br />\n
              — C-like void functions<br />\n
              — Pass by reference<br />\n
              — Default arguments<br />\n
              — Argument binding by name<br />\n
              — Optional arguments<br />\n
              — Import/export functions for DPI<br />\n
              — Classes: object-oriented mechanism that provides abstraction, encapsulation, and safe pointer<br />\n
              capabilities<br />\n
              — Automated testbench support with random constraints<br />\n
              — Interprocess communication synchronization<br />\n
              — Semaphores<br />\n
              — Mailboxes<br />\n
              — Event extensions, event variables, and event sequencing<br />\n
              — Clarification and extension of the scheduling semantics<br />\n
              — Cycle-based functionality: clocking blocks and cycle-based attributes that help reduce development,<br />\n
              ease maintainability, and promote reusability<br />\n
              — Cycle-based signal drives and samples<br />\n
              — Synchronous samples<br />\n
              SystemVerilog is built on top of IEEE Std 1364. SystemVerilog improves the productivity, readability, and<br />\n
              reusability of Verilog-based code. The language enhancements in SystemVerilog provide more concise<br />\n
              hardware descriptions, while still providing an easy route with existing tools into current hardware<br />\n
              implementation flows. The enhancements also provide extensive support for directed and constrainedrandom<br />\n
              testbench development, coverage-driven verification, and assertion-based verification.<br />\n
              1Information on references can be found in Clause 2.<br />\n
              2The numbers in brackets correspond to the numbers in the bibliography in Annex K.<br />\n
              — Race-free program context<br />\n
              — Assertion mechanism for verifying design intent and functional coverage intent<br />\n
              — Property and sequence declarations<br />\n
              — Assertions and coverage statements with action blocks<br />\n
              — Extended hierarchy support<br />\n
              — Packages for declaration encapsulation with import for controlled access<br />\n
              — Compilation-unit scope nested modules and extern modules for separate compilation support<br />\n
              — Extension of port declarations to support interfaces, events, and variables<br />\n
              — $root to provide unambiguous access using hierarchical references<br />\n
              — Interfaces to encapsulate communication and facilitate communication-oriented design<br />\n
              — Functional coverage<br />\n
              — DPI for clean, efficient interoperation with other languages (C provided)<br />\n
              — Assertion API<br />\n
              — Coverage API<br />\n
              — Data read API<br />\n
              — Verilog procedural interface (VPI) extensions for SystemVerilog constructs<br />\n
              — Concurrent assertion formal semantics
              """
            #metaKeywords: null
            #metaDescription: null
            #shortDescription: "IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language"
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        -edition: null
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        -bookCollection: ""
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      #optionValues: Doctrine\ORM\PersistentCollection {#8315 …}
      #position: 0
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      }
      #enabled: true
      #translations: Doctrine\ORM\PersistentCollection {#8259 …}
      #translationsCache: [
        "en_US" => App\Entity\Product\ProductVariantTranslation {#93321
          #locale: "en_US"
          #translatable: App\Entity\Product\ProductVariant {#8099}
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      #taxCategory: Proxies\__CG__\App\Entity\Taxation\TaxCategory {#8131 …}
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      -publishedAt: null
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      -sellable: true
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    #productName: null
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}

same as passed value

product

App\Entity\Product\Product {#7310
  #id: 10370
  #code: "IEEE00004256"
  #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
  #variants: Doctrine\ORM\PersistentCollection {#7743 …}
  #options: Doctrine\ORM\PersistentCollection {#7915
    #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …}
    #initialized: true
    -snapshot: [ …4]
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    -association: [ …21]
    -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …}
    -backRefFieldName: null
    -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#260654 …}
    -isDirty: false
  }
  #associations: Doctrine\ORM\PersistentCollection {#7899 …}
  #createdAt: DateTime @1751039020 {#7274
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  }
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    date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
  }
  #enabled: true
  #translations: Doctrine\ORM\PersistentCollection {#7921 …}
  #translationsCache: [
    "en_US" => App\Entity\Product\ProductTranslation {#7920
      #locale: "en_US"
      #translatable: App\Entity\Product\Product {#7310}
      #id: 36489
      #name: "IEEE/IEC 62530:2007"
      #slug: "ieee-iec-62530-2007-ieee00004256-242022"
      #description: """
        New IEEE Standard - Superseded.<br />\n
        This standard provides a set of extensions to the IEEE 1364™ Verilog® hardware<br />\n
        description language (HDL) to aid in the creation and verification of abstract architectural level<br />\n
        models. It also includes design specification methods, embedded assertions language, testbench<br />\n
        language including coverage and an assertions application programming interface (API), and a<br />\n
        direct programming interface (DPI). This standard enables a productivity boost in design and<br />\n
        validation and covers design, simulation, validation, and formal assertion-based verification flows.<br />\n
        \t\t\t\t<br />\n
        This standard specifies extensions for a higher level of abstraction for modeling and verification with the<br />\n
        Verilog® hardware description language (HDL). These additions extend Verilog into the systems space and<br />\n
        the verification space. SystemVerilog is built on top of IEEE Std 1364™1 for the Verilog HDL. This<br />\n
        standard includes design specification methods, embedded assertions language, testbench language<br />\n
        including coverage and assertions application programming interface (API), and a direct programming<br />\n
        interface (DPI).<br />\n
        Throughout this standard, the following terms apply:<br />\n
        — Verilog refers to IEEE Std 1364 for the Verilog HDL.<br />\n
        — Verilog-2001 refers to IEEE Std 1364-2001 [B4]2 for the Verilog HDL.<br />\n
        — Verilog-1995 refers to IEEE Std 1364-1995 [B3] for the Verilog HDL.<br />\n
        — SystemVerilog refers to the extensions to the Verilog standard (IEEE Std 1364) as defined in this<br />\n
        standard.<br />\n
        SystemVerilog adds extended and new constructs to Verilog, including the following:<br />\n
        — Extensions to data types for better encapsulation and compactness of code and for tighter<br />\n
        specification<br />\n
        — C data types: int, typedef, struct, union, enum<br />\n
        — Other data types: bounded queues, logic (0, 1, X, Z) and bit (0, 1), tagged unions for safety<br />\n
        — Dynamic data types: string, classes, dynamic queues, dynamic arrays, associative arrays<br />\n
        including automatic memory management freeing users from deallocation issues<br />\n
        — Dynamic casting and bit-stream casting<br />\n
        — Automatic/static specification on a per-variable-instance basis<br />\n
        — Extended operators for concise description<br />\n
        — Wild equality and inequality<br />\n
        — Built-in methods to extend the language<br />\n
        — Operator overloading<br />\n
        — Streaming operators<br />\n
        — Set membership<br />\n
        — Extended procedural statements<br />\n
        — Pattern matching on selection statements for use with tagged unions<br />\n
        — Enhanced loop statements plus the foreach statement<br />\n
        — C-like jump statements: return, break, continue<br />\n
        — final blocks that execute at the end of simulation (inverse of initial)<br />\n
        — Extended event control and sequence events<br />\n
        — Enhanced process control<br />\n
        — Extensions to always blocks to include synthesis consistent simulation semantics<br />\n
        — Extensions to fork…join to model pipelines and for enhanced process control<br />\n
        — Fine-grain process control<br />\n
        — Enhanced tasks and functions<br />\n
        — C-like void functions<br />\n
        — Pass by reference<br />\n
        — Default arguments<br />\n
        — Argument binding by name<br />\n
        — Optional arguments<br />\n
        — Import/export functions for DPI<br />\n
        — Classes: object-oriented mechanism that provides abstraction, encapsulation, and safe pointer<br />\n
        capabilities<br />\n
        — Automated testbench support with random constraints<br />\n
        — Interprocess communication synchronization<br />\n
        — Semaphores<br />\n
        — Mailboxes<br />\n
        — Event extensions, event variables, and event sequencing<br />\n
        — Clarification and extension of the scheduling semantics<br />\n
        — Cycle-based functionality: clocking blocks and cycle-based attributes that help reduce development,<br />\n
        ease maintainability, and promote reusability<br />\n
        — Cycle-based signal drives and samples<br />\n
        — Synchronous samples<br />\n
        SystemVerilog is built on top of IEEE Std 1364. SystemVerilog improves the productivity, readability, and<br />\n
        reusability of Verilog-based code. The language enhancements in SystemVerilog provide more concise<br />\n
        hardware descriptions, while still providing an easy route with existing tools into current hardware<br />\n
        implementation flows. The enhancements also provide extensive support for directed and constrainedrandom<br />\n
        testbench development, coverage-driven verification, and assertion-based verification.<br />\n
        1Information on references can be found in Clause 2.<br />\n
        2The numbers in brackets correspond to the numbers in the bibliography in Annex K.<br />\n
        — Race-free program context<br />\n
        — Assertion mechanism for verifying design intent and functional coverage intent<br />\n
        — Property and sequence declarations<br />\n
        — Assertions and coverage statements with action blocks<br />\n
        — Extended hierarchy support<br />\n
        — Packages for declaration encapsulation with import for controlled access<br />\n
        — Compilation-unit scope nested modules and extern modules for separate compilation support<br />\n
        — Extension of port declarations to support interfaces, events, and variables<br />\n
        — $root to provide unambiguous access using hierarchical references<br />\n
        — Interfaces to encapsulate communication and facilitate communication-oriented design<br />\n
        — Functional coverage<br />\n
        — DPI for clean, efficient interoperation with other languages (C provided)<br />\n
        — Assertion API<br />\n
        — Coverage API<br />\n
        — Data read API<br />\n
        — Verilog procedural interface (VPI) extensions for SystemVerilog constructs<br />\n
        — Concurrent assertion formal semantics
        """
      #metaKeywords: null
      #metaDescription: null
      #shortDescription: "IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language"
      -notes: "Superseded"
    }
  ]
  #currentLocale: "en_US"
  #currentTranslation: null
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  #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
  #averageRating: 0.0
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    date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
  }
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    date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
  }
  -author: ""
  -publishedAt: DateTime @1197154800 {#7318
    date: 2007-12-09 00:00:00.0 Europe/Paris (+01:00)
  }
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  -coreDocument: "62530"
  -bookCollection: ""
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  -documents: Doctrine\ORM\PersistentCollection {#7464 …}
  -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
}

same as passed value

Resolved Options

Option	Value
action	""
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The enhancements also provide extensive support for directed and constrainedrandom<br />\n testbench development, coverage-driven verification, and assertion-based verification.<br />\n 1Information on references can be found in Clause 2.<br />\n 2The numbers in brackets correspond to the numbers in the bibliography in Annex K.<br />\n — Race-free program context<br />\n — Assertion mechanism for verifying design intent and functional coverage intent<br />\n — Property and sequence declarations<br />\n — Assertions and coverage statements with action blocks<br />\n — Extended hierarchy support<br />\n — Packages for declaration encapsulation with import for controlled access<br />\n — Compilation-unit scope nested modules and extern modules for separate compilation support<br />\n — Extension of port declarations to support interfaces, events, and variables<br />\n — $root to provide unambiguous access using hierarchical references<br />\n — Interfaces to encapsulate communication and facilitate communication-oriented design<br />\n — Functional coverage<br />\n — DPI for clean, efficient interoperation with other languages (C provided)<br />\n — Assertion API<br />\n — Coverage API<br />\n — Data read API<br />\n — Verilog procedural interface (VPI) extensions for SystemVerilog constructs<br />\n — Concurrent assertion formal semantics """ #metaKeywords: null #metaDescription: null #shortDescription: "IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1197154800 {#7318 date: 2007-12-09 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "62530" -bookCollection: "" -pageCount: 668 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } #optionValues: Doctrine\ORM\PersistentCollection {#8315 …} #position: 0 #createdAt: DateTime @1751041198 {#7283 date: 2025-06-27 18:19:58.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1755611983 {#8116 date: 2025-08-19 15:59:43.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#8259 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductVariantTranslation {#93321 #locale: "en_US" #translatable: App\Entity\Product\ProductVariant {#8099} #id: 4561 #name: null -shortDescription: null -description: null -notes: null -shippingInformation: "Instant download" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #version: 9 #onHold: 0 #onHand: 0 #tracked: false #weight: 0.0 #width: null #height: null #depth: null #taxCategory: Proxies\__CG__\App\Entity\Taxation\TaxCategory {#8131 …} #shippingCategory: null #channelPricings: Doctrine\ORM\PersistentCollection {#8293 …} #shippingRequired: true #images: Doctrine\ORM\PersistentCollection {#8290 …} -apiLastModifiedAt: DateTime @1753740000 {#8098 date: 2025-07-29 00:00:00.0 Europe/Paris (+02:00) } -publishedAt: null -isbn: "9-7807-3815-7269" -ean: "9780738157269" -numberOfUsers: 1 -physicalProduct: false -downloadableImmediately: true -downloadable: true -drmViewerUrl: "https://online-viewer.normadoc.com/8xbJn4" -sellable: true -documents: Doctrine\ORM\PersistentCollection {#8127 …} -drmTokens: Doctrine\ORM\PersistentCollection {#8119 …} -enabledForSubscribers: true -currentAreaContext: null } #productName: null #variantName: null }}
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It also includes design specification methods, embedded assertions language, testbench<br />\n language including coverage and an assertions application programming interface (API), and a<br />\n direct programming interface (DPI). This standard enables a productivity boost in design and<br />\n validation and covers design, simulation, validation, and formal assertion-based verification flows.<br />\n \t\t\t\t<br />\n This standard specifies extensions for a higher level of abstraction for modeling and verification with the<br />\n Verilog® hardware description language (HDL). These additions extend Verilog into the systems space and<br />\n the verification space. SystemVerilog is built on top of IEEE Std 1364™1 for the Verilog HDL. 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SystemVerilog improves the productivity, readability, and<br />\n reusability of Verilog-based code. The language enhancements in SystemVerilog provide more concise<br />\n hardware descriptions, while still providing an easy route with existing tools into current hardware<br />\n implementation flows. The enhancements also provide extensive support for directed and constrainedrandom<br />\n testbench development, coverage-driven verification, and assertion-based verification.<br />\n 1Information on references can be found in Clause 2.<br />\n 2The numbers in brackets correspond to the numbers in the bibliography in Annex K.<br />\n — Race-free program context<br />\n — Assertion mechanism for verifying design intent and functional coverage intent<br />\n — Property and sequence declarations<br />\n — Assertions and coverage statements with action blocks<br />\n — Extended hierarchy support<br />\n — Packages for declaration encapsulation with import for controlled access<br />\n — Compilation-unit scope nested modules and extern modules for separate compilation support<br />\n — Extension of port declarations to support interfaces, events, and variables<br />\n — $root to provide unambiguous access using hierarchical references<br />\n — Interfaces to encapsulate communication and facilitate communication-oriented design<br />\n — Functional coverage<br />\n — DPI for clean, efficient interoperation with other languages (C provided)<br />\n — Assertion API<br />\n — Coverage API<br />\n — Data read API<br />\n — Verilog procedural interface (VPI) extensions for SystemVerilog constructs<br />\n — Concurrent assertion formal semantics """ #metaKeywords: null #metaDescription: null #shortDescription: "IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1197154800 {#7318 date: 2007-12-09 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "62530" -bookCollection: "" -pageCount: 668 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } #optionValues: Doctrine\ORM\PersistentCollection {#8315 …} #position: 0 #createdAt: DateTime @1751041198 {#7283 date: 2025-06-27 18:19:58.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1755611983 {#8116 date: 2025-08-19 15:59:43.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#8259 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductVariantTranslation {#93321 #locale: "en_US" #translatable: App\Entity\Product\ProductVariant {#8099} #id: 4561 #name: null -shortDescription: null -description: null -notes: null -shippingInformation: "Instant download" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #version: 9 #onHold: 0 #onHand: 0 #tracked: false #weight: 0.0 #width: null #height: null #depth: null #taxCategory: Proxies\__CG__\App\Entity\Taxation\TaxCategory {#8131 …} #shippingCategory: null #channelPricings: Doctrine\ORM\PersistentCollection {#8293 …} #shippingRequired: true #images: Doctrine\ORM\PersistentCollection {#8290 …} -apiLastModifiedAt: DateTime @1753740000 {#8098 date: 2025-07-29 00:00:00.0 Europe/Paris (+02:00) } -publishedAt: null -isbn: "9-7807-3815-7269" -ean: "9780738157269" -numberOfUsers: 1 -physicalProduct: false -downloadableImmediately: true -downloadable: true -drmViewerUrl: "https://online-viewer.normadoc.com/8xbJn4" -sellable: true -documents: Doctrine\ORM\PersistentCollection {#8127 …} -drmTokens: Doctrine\ORM\PersistentCollection {#8119 …} -enabledForSubscribers: true -currentAreaContext: null } #productName: null #variantName: null }}

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            — Set membership<br />\n
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            — Default arguments<br />\n
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            — Interprocess communication synchronization<br />\n
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            — Cycle-based signal drives and samples<br />\n
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            SystemVerilog is built on top of IEEE Std 1364. SystemVerilog improves the productivity, readability, and<br />\n
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            testbench development, coverage-driven verification, and assertion-based verification.<br />\n
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            2The numbers in brackets correspond to the numbers in the bibliography in Annex K.<br />\n
            — Race-free program context<br />\n
            — Assertion mechanism for verifying design intent and functional coverage intent<br />\n
            — Property and sequence declarations<br />\n
            — Assertions and coverage statements with action blocks<br />\n
            — Extended hierarchy support<br />\n
            — Packages for declaration encapsulation with import for controlled access<br />\n
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            — Extension of port declarations to support interfaces, events, and variables<br />\n
            — $root to provide unambiguous access using hierarchical references<br />\n
            — Interfaces to encapsulate communication and facilitate communication-oriented design<br />\n
            — Functional coverage<br />\n
            — DPI for clean, efficient interoperation with other languages (C provided)<br />\n
            — Assertion API<br />\n
            — Coverage API<br />\n
            — Data read API<br />\n
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            """
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product	App\Entity\Product\Product {#7310#id: 10370 #code: "IEEE00004256" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …} #initialized: true -snapshot: [ …4] -owner: App\Entity\Product\Product {#7310} -association: [ …21] -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …} -backRefFieldName: null -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#260654 …} -isDirty: false } #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751039020 {#7274 date: 2025-06-27 17:43:40.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#7322 date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 36489 #name: "IEEE/IEC 62530:2007" #slug: "ieee-iec-62530-2007-ieee00004256-242022" #description: """ New IEEE Standard - Superseded.<br />\n This standard provides a set of extensions to the IEEE 1364™ Verilog® hardware<br />\n description language (HDL) to aid in the creation and verification of abstract architectural level<br />\n models. It also includes design specification methods, embedded assertions language, testbench<br />\n language including coverage and an assertions application programming interface (API), and a<br />\n direct programming interface (DPI). This standard enables a productivity boost in design and<br />\n validation and covers design, simulation, validation, and formal assertion-based verification flows.<br />\n \t\t\t\t<br />\n This standard specifies extensions for a higher level of abstraction for modeling and verification with the<br />\n Verilog® hardware description language (HDL). These additions extend Verilog into the systems space and<br />\n the verification space. SystemVerilog is built on top of IEEE Std 1364™1 for the Verilog HDL. This<br />\n standard includes design specification methods, embedded assertions language, testbench language<br />\n including coverage and assertions application programming interface (API), and a direct programming<br />\n interface (DPI).<br />\n Throughout this standard, the following terms apply:<br />\n — Verilog refers to IEEE Std 1364 for the Verilog HDL.<br />\n — Verilog-2001 refers to IEEE Std 1364-2001 [B4]2 for the Verilog HDL.<br />\n — Verilog-1995 refers to IEEE Std 1364-1995 [B3] for the Verilog HDL.<br />\n — SystemVerilog refers to the extensions to the Verilog standard (IEEE Std 1364) as defined in this<br />\n standard.<br />\n SystemVerilog adds extended and new constructs to Verilog, including the following:<br />\n — Extensions to data types for better encapsulation and compactness of code and for tighter<br />\n specification<br />\n — C data types: int, typedef, struct, union, enum<br />\n — Other data types: bounded queues, logic (0, 1, X, Z) and bit (0, 1), tagged unions for safety<br />\n — Dynamic data types: string, classes, dynamic queues, dynamic arrays, associative arrays<br />\n including automatic memory management freeing users from deallocation issues<br />\n — Dynamic casting and bit-stream casting<br />\n — Automatic/static specification on a per-variable-instance basis<br />\n — Extended operators for concise description<br />\n — Wild equality and inequality<br />\n — Built-in methods to extend the language<br />\n — Operator overloading<br />\n — Streaming operators<br />\n — Set membership<br />\n — Extended procedural statements<br />\n — Pattern matching on selection statements for use with tagged unions<br />\n — Enhanced loop statements plus the foreach statement<br />\n — C-like jump statements: return, break, continue<br />\n — final blocks that execute at the end of simulation (inverse of initial)<br />\n — Extended event control and sequence events<br />\n — Enhanced process control<br />\n — Extensions to always blocks to include synthesis consistent simulation semantics<br />\n — Extensions to fork…join to model pipelines and for enhanced process control<br />\n — Fine-grain process control<br />\n — Enhanced tasks and functions<br />\n — C-like void functions<br />\n — Pass by reference<br />\n — Default arguments<br />\n — Argument binding by name<br />\n — Optional arguments<br />\n — Import/export functions for DPI<br />\n — Classes: object-oriented mechanism that provides abstraction, encapsulation, and safe pointer<br />\n capabilities<br />\n — Automated testbench support with random constraints<br />\n — Interprocess communication synchronization<br />\n — Semaphores<br />\n — Mailboxes<br />\n — Event extensions, event variables, and event sequencing<br />\n — Clarification and extension of the scheduling semantics<br />\n — Cycle-based functionality: clocking blocks and cycle-based attributes that help reduce development,<br />\n ease maintainability, and promote reusability<br />\n — Cycle-based signal drives and samples<br />\n — Synchronous samples<br />\n SystemVerilog is built on top of IEEE Std 1364. SystemVerilog improves the productivity, readability, and<br />\n reusability of Verilog-based code. The language enhancements in SystemVerilog provide more concise<br />\n hardware descriptions, while still providing an easy route with existing tools into current hardware<br />\n implementation flows. The enhancements also provide extensive support for directed and constrainedrandom<br />\n testbench development, coverage-driven verification, and assertion-based verification.<br />\n 1Information on references can be found in Clause 2.<br />\n 2The numbers in brackets correspond to the numbers in the bibliography in Annex K.<br />\n — Race-free program context<br />\n — Assertion mechanism for verifying design intent and functional coverage intent<br />\n — Property and sequence declarations<br />\n — Assertions and coverage statements with action blocks<br />\n — Extended hierarchy support<br />\n — Packages for declaration encapsulation with import for controlled access<br />\n — Compilation-unit scope nested modules and extern modules for separate compilation support<br />\n — Extension of port declarations to support interfaces, events, and variables<br />\n — $root to provide unambiguous access using hierarchical references<br />\n — Interfaces to encapsulate communication and facilitate communication-oriented design<br />\n — Functional coverage<br />\n — DPI for clean, efficient interoperation with other languages (C provided)<br />\n — Assertion API<br />\n — Coverage API<br />\n — Data read API<br />\n — Verilog procedural interface (VPI) extensions for SystemVerilog constructs<br />\n — Concurrent assertion formal semantics """ #metaKeywords: null #metaDescription: null #shortDescription: "IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1197154800 {#7318 date: 2007-12-09 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "62530" -bookCollection: "" -pageCount: 668 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …}}	same as passed value

Option

Passed Value

Resolved Value

product

App\Entity\Product\Product {#7310
  #id: 10370
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    -association: [ …21]
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    -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#260654 …}
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    "en_US" => App\Entity\Product\ProductTranslation {#7920
      #locale: "en_US"
      #translatable: App\Entity\Product\Product {#7310}
      #id: 36489
      #name: "IEEE/IEC 62530:2007"
      #slug: "ieee-iec-62530-2007-ieee00004256-242022"
      #description: """
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        This standard provides a set of extensions to the IEEE 1364™ Verilog® hardware<br />\n
        description language (HDL) to aid in the creation and verification of abstract architectural level<br />\n
        models. It also includes design specification methods, embedded assertions language, testbench<br />\n
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        This standard specifies extensions for a higher level of abstraction for modeling and verification with the<br />\n
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        the verification space. SystemVerilog is built on top of IEEE Std 1364™1 for the Verilog HDL. This<br />\n
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        Throughout this standard, the following terms apply:<br />\n
        — Verilog refers to IEEE Std 1364 for the Verilog HDL.<br />\n
        — Verilog-2001 refers to IEEE Std 1364-2001 [B4]2 for the Verilog HDL.<br />\n
        — Verilog-1995 refers to IEEE Std 1364-1995 [B3] for the Verilog HDL.<br />\n
        — SystemVerilog refers to the extensions to the Verilog standard (IEEE Std 1364) as defined in this<br />\n
        standard.<br />\n
        SystemVerilog adds extended and new constructs to Verilog, including the following:<br />\n
        — Extensions to data types for better encapsulation and compactness of code and for tighter<br />\n
        specification<br />\n
        — C data types: int, typedef, struct, union, enum<br />\n
        — Other data types: bounded queues, logic (0, 1, X, Z) and bit (0, 1), tagged unions for safety<br />\n
        — Dynamic data types: string, classes, dynamic queues, dynamic arrays, associative arrays<br />\n
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        — Automatic/static specification on a per-variable-instance basis<br />\n
        — Extended operators for concise description<br />\n
        — Wild equality and inequality<br />\n
        — Built-in methods to extend the language<br />\n
        — Operator overloading<br />\n
        — Streaming operators<br />\n
        — Set membership<br />\n
        — Extended procedural statements<br />\n
        — Pattern matching on selection statements for use with tagged unions<br />\n
        — Enhanced loop statements plus the foreach statement<br />\n
        — C-like jump statements: return, break, continue<br />\n
        — final blocks that execute at the end of simulation (inverse of initial)<br />\n
        — Extended event control and sequence events<br />\n
        — Enhanced process control<br />\n
        — Extensions to always blocks to include synthesis consistent simulation semantics<br />\n
        — Extensions to fork…join to model pipelines and for enhanced process control<br />\n
        — Fine-grain process control<br />\n
        — Enhanced tasks and functions<br />\n
        — C-like void functions<br />\n
        — Pass by reference<br />\n
        — Default arguments<br />\n
        — Argument binding by name<br />\n
        — Optional arguments<br />\n
        — Import/export functions for DPI<br />\n
        — Classes: object-oriented mechanism that provides abstraction, encapsulation, and safe pointer<br />\n
        capabilities<br />\n
        — Automated testbench support with random constraints<br />\n
        — Interprocess communication synchronization<br />\n
        — Semaphores<br />\n
        — Mailboxes<br />\n
        — Event extensions, event variables, and event sequencing<br />\n
        — Clarification and extension of the scheduling semantics<br />\n
        — Cycle-based functionality: clocking blocks and cycle-based attributes that help reduce development,<br />\n
        ease maintainability, and promote reusability<br />\n
        — Cycle-based signal drives and samples<br />\n
        — Synchronous samples<br />\n
        SystemVerilog is built on top of IEEE Std 1364. SystemVerilog improves the productivity, readability, and<br />\n
        reusability of Verilog-based code. The language enhancements in SystemVerilog provide more concise<br />\n
        hardware descriptions, while still providing an easy route with existing tools into current hardware<br />\n
        implementation flows. The enhancements also provide extensive support for directed and constrainedrandom<br />\n
        testbench development, coverage-driven verification, and assertion-based verification.<br />\n
        1Information on references can be found in Clause 2.<br />\n
        2The numbers in brackets correspond to the numbers in the bibliography in Annex K.<br />\n
        — Race-free program context<br />\n
        — Assertion mechanism for verifying design intent and functional coverage intent<br />\n
        — Property and sequence declarations<br />\n
        — Assertions and coverage statements with action blocks<br />\n
        — Extended hierarchy support<br />\n
        — Packages for declaration encapsulation with import for controlled access<br />\n
        — Compilation-unit scope nested modules and extern modules for separate compilation support<br />\n
        — Extension of port declarations to support interfaces, events, and variables<br />\n
        — $root to provide unambiguous access using hierarchical references<br />\n
        — Interfaces to encapsulate communication and facilitate communication-oriented design<br />\n
        — Functional coverage<br />\n
        — DPI for clean, efficient interoperation with other languages (C provided)<br />\n
        — Assertion API<br />\n
        — Coverage API<br />\n
        — Data read API<br />\n
        — Verilog procedural interface (VPI) extensions for SystemVerilog constructs<br />\n
        — Concurrent assertion formal semantics
        """
      #metaKeywords: null
      #metaDescription: null
      #shortDescription: "IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language"
      -notes: "Superseded"
    }
  ]
  #currentLocale: "en_US"
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  #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
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  #averageRating: 0.0
  #images: Doctrine\ORM\PersistentCollection {#7644 …}
  -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
  -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
  -apiLastModifiedAt: DateTime @1754517600 {#7317
    date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
  }
  -lastUpdatedAt: DateTime @1578006000 {#7292
    date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
  }
  -author: ""
  -publishedAt: DateTime @1197154800 {#7318
    date: 2007-12-09 00:00:00.0 Europe/Paris (+01:00)
  }
  -releasedAt: null
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  -canceledAt: null
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  -coreDocument: "62530"
  -bookCollection: ""
  -pageCount: 668
  -documents: Doctrine\ORM\PersistentCollection {#7464 …}
  -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
}

same as passed value

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data_class	"App\Entity\Order\OrderItem"
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product	App\Entity\Product\Product {#7310#id: 10370 #code: "IEEE00004256" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …} #initialized: true -snapshot: [ …4] -owner: App\Entity\Product\Product {#7310} -association: [ …21] -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …} -backRefFieldName: null -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#260654 …} -isDirty: false } #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751039020 {#7274 date: 2025-06-27 17:43:40.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#7322 date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 36489 #name: "IEEE/IEC 62530:2007" #slug: "ieee-iec-62530-2007-ieee00004256-242022" #description: """ New IEEE Standard - Superseded.<br />\n This standard provides a set of extensions to the IEEE 1364™ Verilog® hardware<br />\n description language (HDL) to aid in the creation and verification of abstract architectural level<br />\n models. It also includes design specification methods, embedded assertions language, testbench<br />\n language including coverage and an assertions application programming interface (API), and a<br />\n direct programming interface (DPI). This standard enables a productivity boost in design and<br />\n validation and covers design, simulation, validation, and formal assertion-based verification flows.<br />\n \t\t\t\t<br />\n This standard specifies extensions for a higher level of abstraction for modeling and verification with the<br />\n Verilog® hardware description language (HDL). These additions extend Verilog into the systems space and<br />\n the verification space. SystemVerilog is built on top of IEEE Std 1364™1 for the Verilog HDL. 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variant

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"Sylius\Bundle\ProductBundle\Form\Type\ProductVariantMatchType"

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Model Format	App\Entity\Product\ProductVariant {#8099#id: 4543 #code: "IEEE00004256PDF" #product: App\Entity\Product\Product {#7310 #id: 10370 #code: "IEEE00004256" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …} #initialized: true -snapshot: [ …4] -owner: App\Entity\Product\Product {#7310} -association: [ …21] -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …} -backRefFieldName: null -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#260654 …} -isDirty: false } #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751039020 {#7274 date: 2025-06-27 17:43:40.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#7322 date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 36489 #name: "IEEE/IEC 62530:2007" #slug: "ieee-iec-62530-2007-ieee00004256-242022" #description: """ New IEEE Standard - Superseded.<br />\n This standard provides a set of extensions to the IEEE 1364™ Verilog® hardware<br />\n description language (HDL) to aid in the creation and verification of abstract architectural level<br />\n models. It also includes design specification methods, embedded assertions language, testbench<br />\n language including coverage and an assertions application programming interface (API), and a<br />\n direct programming interface (DPI). This standard enables a productivity boost in design and<br />\n validation and covers design, simulation, validation, and formal assertion-based verification flows.<br />\n \t\t\t\t<br />\n This standard specifies extensions for a higher level of abstraction for modeling and verification with the<br />\n Verilog® hardware description language (HDL). These additions extend Verilog into the systems space and<br />\n the verification space. SystemVerilog is built on top of IEEE Std 1364™1 for the Verilog HDL. This<br />\n standard includes design specification methods, embedded assertions language, testbench language<br />\n including coverage and assertions application programming interface (API), and a direct programming<br />\n interface (DPI).<br />\n Throughout this standard, the following terms apply:<br />\n — Verilog refers to IEEE Std 1364 for the Verilog HDL.<br />\n — Verilog-2001 refers to IEEE Std 1364-2001 [B4]2 for the Verilog HDL.<br />\n — Verilog-1995 refers to IEEE Std 1364-1995 [B3] for the Verilog HDL.<br />\n — SystemVerilog refers to the extensions to the Verilog standard (IEEE Std 1364) as defined in this<br />\n standard.<br />\n SystemVerilog adds extended and new constructs to Verilog, including the following:<br />\n — Extensions to data types for better encapsulation and compactness of code and for tighter<br />\n specification<br />\n — C data types: int, typedef, struct, union, enum<br />\n — Other data types: bounded queues, logic (0, 1, X, Z) and bit (0, 1), tagged unions for safety<br />\n — Dynamic data types: string, classes, dynamic queues, dynamic arrays, associative arrays<br />\n including automatic memory management freeing users from deallocation issues<br />\n — Dynamic casting and bit-stream casting<br />\n — Automatic/static specification on a per-variable-instance basis<br />\n — Extended operators for concise description<br />\n — Wild equality and inequality<br />\n — Built-in methods to extend the language<br />\n — Operator overloading<br />\n — Streaming operators<br />\n — Set membership<br />\n — Extended procedural statements<br />\n — Pattern matching on selection statements for use with tagged unions<br />\n — Enhanced loop statements plus the foreach statement<br />\n — C-like jump statements: return, break, continue<br />\n — final blocks that execute at the end of simulation (inverse of initial)<br />\n — Extended event control and sequence events<br />\n — Enhanced process control<br />\n — Extensions to always blocks to include synthesis consistent simulation semantics<br />\n — Extensions to fork…join to model pipelines and for enhanced process control<br />\n — Fine-grain process control<br />\n — Enhanced tasks and functions<br />\n — C-like void functions<br />\n — Pass by reference<br />\n — Default arguments<br />\n — Argument binding by name<br />\n — Optional arguments<br />\n — Import/export functions for DPI<br />\n — Classes: object-oriented mechanism that provides abstraction, encapsulation, and safe pointer<br />\n capabilities<br />\n — Automated testbench support with random constraints<br />\n — Interprocess communication synchronization<br />\n — Semaphores<br />\n — Mailboxes<br />\n — Event extensions, event variables, and event sequencing<br />\n — Clarification and extension of the scheduling semantics<br />\n — Cycle-based functionality: clocking blocks and cycle-based attributes that help reduce development,<br />\n ease maintainability, and promote reusability<br />\n — Cycle-based signal drives and samples<br />\n — Synchronous samples<br />\n SystemVerilog is built on top of IEEE Std 1364. SystemVerilog improves the productivity, readability, and<br />\n reusability of Verilog-based code. The language enhancements in SystemVerilog provide more concise<br />\n hardware descriptions, while still providing an easy route with existing tools into current hardware<br />\n implementation flows. The enhancements also provide extensive support for directed and constrainedrandom<br />\n testbench development, coverage-driven verification, and assertion-based verification.<br />\n 1Information on references can be found in Clause 2.<br />\n 2The numbers in brackets correspond to the numbers in the bibliography in Annex K.<br />\n — Race-free program context<br />\n — Assertion mechanism for verifying design intent and functional coverage intent<br />\n — Property and sequence declarations<br />\n — Assertions and coverage statements with action blocks<br />\n — Extended hierarchy support<br />\n — Packages for declaration encapsulation with import for controlled access<br />\n — Compilation-unit scope nested modules and extern modules for separate compilation support<br />\n — Extension of port declarations to support interfaces, events, and variables<br />\n — $root to provide unambiguous access using hierarchical references<br />\n — Interfaces to encapsulate communication and facilitate communication-oriented design<br />\n — Functional coverage<br />\n — DPI for clean, efficient interoperation with other languages (C provided)<br />\n — Assertion API<br />\n — Coverage API<br />\n — Data read API<br />\n — Verilog procedural interface (VPI) extensions for SystemVerilog constructs<br />\n — Concurrent assertion formal semantics """ #metaKeywords: null #metaDescription: null #shortDescription: "IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1197154800 {#7318 date: 2007-12-09 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "62530" -bookCollection: "" -pageCount: 668 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } #optionValues: Doctrine\ORM\PersistentCollection {#8315 …} #position: 0 #createdAt: DateTime @1751041198 {#7283 date: 2025-06-27 18:19:58.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1755611983 {#8116 date: 2025-08-19 15:59:43.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#8259 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductVariantTranslation {#93321 #locale: "en_US" #translatable: App\Entity\Product\ProductVariant {#8099} #id: 4561 #name: null -shortDescription: null -description: null -notes: null -shippingInformation: "Instant download" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #version: 9 #onHold: 0 #onHand: 0 #tracked: false #weight: 0.0 #width: null #height: null #depth: null #taxCategory: Proxies\__CG__\App\Entity\Taxation\TaxCategory {#8131 …} #shippingCategory: null #channelPricings: Doctrine\ORM\PersistentCollection {#8293 …} #shippingRequired: true #images: Doctrine\ORM\PersistentCollection {#8290 …} -apiLastModifiedAt: DateTime @1753740000 {#8098 date: 2025-07-29 00:00:00.0 Europe/Paris (+02:00) } -publishedAt: null -isbn: "9-7807-3815-7269" -ean: "9780738157269" -numberOfUsers: 1 -physicalProduct: false -downloadableImmediately: true -downloadable: true -drmViewerUrl: "https://online-viewer.normadoc.com/8xbJn4" -sellable: true -documents: Doctrine\ORM\PersistentCollection {#8127 …} -drmTokens: Doctrine\ORM\PersistentCollection {#8119 …} -enabledForSubscribers: true -currentAreaContext: null}
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View Format	same as normalized format

Property

Value

Model Format

App\Entity\Product\ProductVariant {#8099
  #id: 4543
  #code: "IEEE00004256PDF"
  #product: App\Entity\Product\Product {#7310
    #id: 10370
    #code: "IEEE00004256"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915
      #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …}
      #initialized: true
      -snapshot: [ …4]
      -owner: App\Entity\Product\Product {#7310}
      -association: [ …21]
      -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …}
      -backRefFieldName: null
      -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#260654 …}
      -isDirty: false
    }
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751039020 {#7274
      date: 2025-06-27 17:43:40.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#7322
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    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
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      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 36489
        #name: "IEEE/IEC 62530:2007"
        #slug: "ieee-iec-62530-2007-ieee00004256-242022"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          This standard provides a set of extensions to the IEEE 1364™ Verilog® hardware<br />\n
          description language (HDL) to aid in the creation and verification of abstract architectural level<br />\n
          models. It also includes design specification methods, embedded assertions language, testbench<br />\n
          language including coverage and an assertions application programming interface (API), and a<br />\n
          direct programming interface (DPI). This standard enables a productivity boost in design and<br />\n
          validation and covers design, simulation, validation, and formal assertion-based verification flows.<br />\n
          \t\t\t\t<br />\n
          This standard specifies extensions for a higher level of abstraction for modeling and verification with the<br />\n
          Verilog® hardware description language (HDL). These additions extend Verilog into the systems space and<br />\n
          the verification space. SystemVerilog is built on top of IEEE Std 1364™1 for the Verilog HDL. This<br />\n
          standard includes design specification methods, embedded assertions language, testbench language<br />\n
          including coverage and assertions application programming interface (API), and a direct programming<br />\n
          interface (DPI).<br />\n
          Throughout this standard, the following terms apply:<br />\n
          — Verilog refers to IEEE Std 1364 for the Verilog HDL.<br />\n
          — Verilog-2001 refers to IEEE Std 1364-2001 [B4]2 for the Verilog HDL.<br />\n
          — Verilog-1995 refers to IEEE Std 1364-1995 [B3] for the Verilog HDL.<br />\n
          — SystemVerilog refers to the extensions to the Verilog standard (IEEE Std 1364) as defined in this<br />\n
          standard.<br />\n
          SystemVerilog adds extended and new constructs to Verilog, including the following:<br />\n
          — Extensions to data types for better encapsulation and compactness of code and for tighter<br />\n
          specification<br />\n
          — C data types: int, typedef, struct, union, enum<br />\n
          — Other data types: bounded queues, logic (0, 1, X, Z) and bit (0, 1), tagged unions for safety<br />\n
          — Dynamic data types: string, classes, dynamic queues, dynamic arrays, associative arrays<br />\n
          including automatic memory management freeing users from deallocation issues<br />\n
          — Dynamic casting and bit-stream casting<br />\n
          — Automatic/static specification on a per-variable-instance basis<br />\n
          — Extended operators for concise description<br />\n
          — Wild equality and inequality<br />\n
          — Built-in methods to extend the language<br />\n
          — Operator overloading<br />\n
          — Streaming operators<br />\n
          — Set membership<br />\n
          — Extended procedural statements<br />\n
          — Pattern matching on selection statements for use with tagged unions<br />\n
          — Enhanced loop statements plus the foreach statement<br />\n
          — C-like jump statements: return, break, continue<br />\n
          — final blocks that execute at the end of simulation (inverse of initial)<br />\n
          — Extended event control and sequence events<br />\n
          — Enhanced process control<br />\n
          — Extensions to always blocks to include synthesis consistent simulation semantics<br />\n
          — Extensions to fork…join to model pipelines and for enhanced process control<br />\n
          — Fine-grain process control<br />\n
          — Enhanced tasks and functions<br />\n
          — C-like void functions<br />\n
          — Pass by reference<br />\n
          — Default arguments<br />\n
          — Argument binding by name<br />\n
          — Optional arguments<br />\n
          — Import/export functions for DPI<br />\n
          — Classes: object-oriented mechanism that provides abstraction, encapsulation, and safe pointer<br />\n
          capabilities<br />\n
          — Automated testbench support with random constraints<br />\n
          — Interprocess communication synchronization<br />\n
          — Semaphores<br />\n
          — Mailboxes<br />\n
          — Event extensions, event variables, and event sequencing<br />\n
          — Clarification and extension of the scheduling semantics<br />\n
          — Cycle-based functionality: clocking blocks and cycle-based attributes that help reduce development,<br />\n
          ease maintainability, and promote reusability<br />\n
          — Cycle-based signal drives and samples<br />\n
          — Synchronous samples<br />\n
          SystemVerilog is built on top of IEEE Std 1364. SystemVerilog improves the productivity, readability, and<br />\n
          reusability of Verilog-based code. The language enhancements in SystemVerilog provide more concise<br />\n
          hardware descriptions, while still providing an easy route with existing tools into current hardware<br />\n
          implementation flows. The enhancements also provide extensive support for directed and constrainedrandom<br />\n
          testbench development, coverage-driven verification, and assertion-based verification.<br />\n
          1Information on references can be found in Clause 2.<br />\n
          2The numbers in brackets correspond to the numbers in the bibliography in Annex K.<br />\n
          — Race-free program context<br />\n
          — Assertion mechanism for verifying design intent and functional coverage intent<br />\n
          — Property and sequence declarations<br />\n
          — Assertions and coverage statements with action blocks<br />\n
          — Extended hierarchy support<br />\n
          — Packages for declaration encapsulation with import for controlled access<br />\n
          — Compilation-unit scope nested modules and extern modules for separate compilation support<br />\n
          — Extension of port declarations to support interfaces, events, and variables<br />\n
          — $root to provide unambiguous access using hierarchical references<br />\n
          — Interfaces to encapsulate communication and facilitate communication-oriented design<br />\n
          — Functional coverage<br />\n
          — DPI for clean, efficient interoperation with other languages (C provided)<br />\n
          — Assertion API<br />\n
          — Coverage API<br />\n
          — Data read API<br />\n
          — Verilog procedural interface (VPI) extensions for SystemVerilog constructs<br />\n
          — Concurrent assertion formal semantics
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#7292
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1197154800 {#7318
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    }
    -releasedAt: null
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    -canceledAt: null
    -edition: null
    -coreDocument: "62530"
    -bookCollection: ""
    -pageCount: 668
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
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  #optionValues: Doctrine\ORM\PersistentCollection {#8315 …}
  #position: 0
  #createdAt: DateTime @1751041198 {#7283
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  }
  #updatedAt: DateTime @1755611983 {#8116
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  }
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    "en_US" => App\Entity\Product\ProductVariantTranslation {#93321
      #locale: "en_US"
      #translatable: App\Entity\Product\ProductVariant {#8099}
      #id: 4561
      #name: null
      -shortDescription: null
      -description: null
      -notes: null
      -shippingInformation: "Instant download"
    }
  ]
  #currentLocale: "en_US"
  #currentTranslation: null
  #fallbackLocale: "en_US"
  #version: 9
  #onHold: 0
  #onHand: 0
  #tracked: false
  #weight: 0.0
  #width: null
  #height: null
  #depth: null
  #taxCategory: Proxies\__CG__\App\Entity\Taxation\TaxCategory {#8131 …}
  #shippingCategory: null
  #channelPricings: Doctrine\ORM\PersistentCollection {#8293 …}
  #shippingRequired: true
  #images: Doctrine\ORM\PersistentCollection {#8290 …}
  -apiLastModifiedAt: DateTime @1753740000 {#8098
    date: 2025-07-29 00:00:00.0 Europe/Paris (+02:00)
  }
  -publishedAt: null
  -isbn: "9-7807-3815-7269"
  -ean: "9780738157269"
  -numberOfUsers: 1
  -physicalProduct: false
  -downloadableImmediately: true
  -downloadable: true
  -drmViewerUrl: "https://online-viewer.normadoc.com/8xbJn4"
  -sellable: true
  -documents: Doctrine\ORM\PersistentCollection {#8127 …}
  -drmTokens: Doctrine\ORM\PersistentCollection {#8119 …}
  -enabledForSubscribers: true
  -currentAreaContext: null
}

Normalized Format

[
  "red_line" => App\Entity\Product\ProductOptionValue {#8442
    #id: 212
    #code: "no"
    #option: App\Entity\Product\ProductOption {#8059
      #id: 34
      #code: "red_line"
      #position: 3
      #values: Doctrine\ORM\PersistentCollection {#8062 …}
      #createdAt: DateTime @1737709966 {#8057
        date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00)
      }
      #updatedAt: DateTime @1737709966 {#8058
        date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00)
      }
      #translations: Doctrine\ORM\PersistentCollection {#8060 …}
      #translationsCache: [
        "en_US" => App\Entity\Product\ProductOptionTranslation {#8090
          #locale: "en_US"
          #translatable: App\Entity\Product\ProductOption {#8059}
          #id: 52
          #name: "Red Line"
        }
      ]
      #currentLocale: "en_US"
      #currentTranslation: null
      #fallbackLocale: "en_US"
    }
    #translations: Doctrine\ORM\PersistentCollection {#8423 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductOptionValueTranslation {#8483
        #locale: "en_US"
        #translatable: App\Entity\Product\ProductOptionValue {#8442}
        #id: 836
        #value: "No"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    -enabled: true
  }
  "format" => App\Entity\Product\ProductOptionValue {#8361
    #id: 220
    #code: "format_28"
    #option: App\Entity\Product\ProductOption {#7320
      #id: 31
      #code: "format"
      #position: 0
      #values: Doctrine\ORM\PersistentCollection {#8026 …}
      #createdAt: DateTime @1737709966 {#7286
        date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00)
      }
      #updatedAt: DateTime @1737709966 {#7985
        date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00)
      }
      #translations: Doctrine\ORM\PersistentCollection {#7982 …}
      #translationsCache: [
        "en_US" => App\Entity\Product\ProductOptionTranslation {#8084
          #locale: "en_US"
          #translatable: App\Entity\Product\ProductOption {#7320}
          #id: 40
          #name: "Format"
        }
      ]
      #currentLocale: "en_US"
      #currentTranslation: null
      #fallbackLocale: "en_US"
    }
    #translations: Doctrine\ORM\PersistentCollection {#8349 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductOptionValueTranslation {#8475
        #locale: "en_US"
        #translatable: App\Entity\Product\ProductOptionValue {#8361}
        #id: 868
        #value: "Secure pdf"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    -enabled: true
  }
  "languages" => App\Entity\Product\ProductOptionValue {#8452
    #id: 231
    #code: "languages_1369"
    #option: App\Entity\Product\ProductOption {#8029
      #id: 32
      #code: "languages"
      #position: 1
      #values: Doctrine\ORM\PersistentCollection {#7979 …}
      #createdAt: DateTime @1737709966 {#8021
        date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00)
      }
      #updatedAt: DateTime @1737709966 {#8022
        date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00)
      }
      #translations: Doctrine\ORM\PersistentCollection {#8019 …}
      #translationsCache: [
        "en_US" => App\Entity\Product\ProductOptionTranslation {#8076
          #locale: "en_US"
          #translatable: App\Entity\Product\ProductOption {#8029}
          #id: 44
          #name: "Languages"
        }
      ]
      #currentLocale: "en_US"
      #currentTranslation: null
      #fallbackLocale: "en_US"
    }
    #translations: Doctrine\ORM\PersistentCollection {#8456 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductOptionValueTranslation {#8458
        #locale: "en_US"
        #translatable: App\Entity\Product\ProductOptionValue {#8452}
        #id: 912
        #value: "English"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    -enabled: true
  }
  "multi_user" => App\Entity\Product\ProductOptionValue {#8455
    #id: 291
    #code: "multi_user_4736"
    #option: App\Entity\Product\ProductOption {#8050
      #id: 33
      #code: "multi_user"
      #position: 2
      #values: Doctrine\ORM\PersistentCollection {#8055 …}
      #createdAt: DateTime @1737709966 {#8051
        date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00)
      }
      #updatedAt: DateTime @1737709966 {#8052
        date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00)
      }
      #translations: Doctrine\ORM\PersistentCollection {#8053 …}
      #translationsCache: [
        "en_US" => App\Entity\Product\ProductOptionTranslation {#8071
          #locale: "en_US"
          #translatable: App\Entity\Product\ProductOption {#8050}
          #id: 48
          #name: "Multi User"
        }
      ]
      #currentLocale: "en_US"
      #currentTranslation: null
      #fallbackLocale: "en_US"
    }
    #translations: Doctrine\ORM\PersistentCollection {#8453 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductOptionValueTranslation {#8489
        #locale: "en_US"
        #translatable: App\Entity\Product\ProductOptionValue {#8455}
        #id: 1152
        #value: "NC"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    -enabled: true
  }
]

View Format

same as normalized format

Submitted Data

This form was not submitted.

Passed Options

Option	Passed Value	Resolved Value
product	App\Entity\Product\Product {#7310#id: 10370 #code: "IEEE00004256" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …} #initialized: true -snapshot: [ …4] -owner: App\Entity\Product\Product {#7310} -association: [ …21] -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …} -backRefFieldName: null -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#260654 …} -isDirty: false } #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751039020 {#7274 date: 2025-06-27 17:43:40.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#7322 date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 36489 #name: "IEEE/IEC 62530:2007" #slug: "ieee-iec-62530-2007-ieee00004256-242022" #description: """ New IEEE Standard - Superseded.<br />\n This standard provides a set of extensions to the IEEE 1364™ Verilog® hardware<br />\n description language (HDL) to aid in the creation and verification of abstract architectural level<br />\n models. It also includes design specification methods, embedded assertions language, testbench<br />\n language including coverage and an assertions application programming interface (API), and a<br />\n direct programming interface (DPI). This standard enables a productivity boost in design and<br />\n validation and covers design, simulation, validation, and formal assertion-based verification flows.<br />\n \t\t\t\t<br />\n This standard specifies extensions for a higher level of abstraction for modeling and verification with the<br />\n Verilog® hardware description language (HDL). These additions extend Verilog into the systems space and<br />\n the verification space. SystemVerilog is built on top of IEEE Std 1364™1 for the Verilog HDL. This<br />\n standard includes design specification methods, embedded assertions language, testbench language<br />\n including coverage and assertions application programming interface (API), and a direct programming<br />\n interface (DPI).<br />\n Throughout this standard, the following terms apply:<br />\n — Verilog refers to IEEE Std 1364 for the Verilog HDL.<br />\n — Verilog-2001 refers to IEEE Std 1364-2001 [B4]2 for the Verilog HDL.<br />\n — Verilog-1995 refers to IEEE Std 1364-1995 [B3] for the Verilog HDL.<br />\n — SystemVerilog refers to the extensions to the Verilog standard (IEEE Std 1364) as defined in this<br />\n standard.<br />\n SystemVerilog adds extended and new constructs to Verilog, including the following:<br />\n — Extensions to data types for better encapsulation and compactness of code and for tighter<br />\n specification<br />\n — C data types: int, typedef, struct, union, enum<br />\n — Other data types: bounded queues, logic (0, 1, X, Z) and bit (0, 1), tagged unions for safety<br />\n — Dynamic data types: string, classes, dynamic queues, dynamic arrays, associative arrays<br />\n including automatic memory management freeing users from deallocation issues<br />\n — Dynamic casting and bit-stream casting<br />\n — Automatic/static specification on a per-variable-instance basis<br />\n — Extended operators for concise description<br />\n — Wild equality and inequality<br />\n — Built-in methods to extend the language<br />\n — Operator overloading<br />\n — Streaming operators<br />\n — Set membership<br />\n — Extended procedural statements<br />\n — Pattern matching on selection statements for use with tagged unions<br />\n — Enhanced loop statements plus the foreach statement<br />\n — C-like jump statements: return, break, continue<br />\n — final blocks that execute at the end of simulation (inverse of initial)<br />\n — Extended event control and sequence events<br />\n — Enhanced process control<br />\n — Extensions to always blocks to include synthesis consistent simulation semantics<br />\n — Extensions to fork…join to model pipelines and for enhanced process control<br />\n — Fine-grain process control<br />\n — Enhanced tasks and functions<br />\n — C-like void functions<br />\n — Pass by reference<br />\n — Default arguments<br />\n — Argument binding by name<br />\n — Optional arguments<br />\n — Import/export functions for DPI<br />\n — Classes: object-oriented mechanism that provides abstraction, encapsulation, and safe pointer<br />\n capabilities<br />\n — Automated testbench support with random constraints<br />\n — Interprocess communication synchronization<br />\n — Semaphores<br />\n — Mailboxes<br />\n — Event extensions, event variables, and event sequencing<br />\n — Clarification and extension of the scheduling semantics<br />\n — Cycle-based functionality: clocking blocks and cycle-based attributes that help reduce development,<br />\n ease maintainability, and promote reusability<br />\n — Cycle-based signal drives and samples<br />\n — Synchronous samples<br />\n SystemVerilog is built on top of IEEE Std 1364. SystemVerilog improves the productivity, readability, and<br />\n reusability of Verilog-based code. The language enhancements in SystemVerilog provide more concise<br />\n hardware descriptions, while still providing an easy route with existing tools into current hardware<br />\n implementation flows. The enhancements also provide extensive support for directed and constrainedrandom<br />\n testbench development, coverage-driven verification, and assertion-based verification.<br />\n 1Information on references can be found in Clause 2.<br />\n 2The numbers in brackets correspond to the numbers in the bibliography in Annex K.<br />\n — Race-free program context<br />\n — Assertion mechanism for verifying design intent and functional coverage intent<br />\n — Property and sequence declarations<br />\n — Assertions and coverage statements with action blocks<br />\n — Extended hierarchy support<br />\n — Packages for declaration encapsulation with import for controlled access<br />\n — Compilation-unit scope nested modules and extern modules for separate compilation support<br />\n — Extension of port declarations to support interfaces, events, and variables<br />\n — $root to provide unambiguous access using hierarchical references<br />\n — Interfaces to encapsulate communication and facilitate communication-oriented design<br />\n — Functional coverage<br />\n — DPI for clean, efficient interoperation with other languages (C provided)<br />\n — Assertion API<br />\n — Coverage API<br />\n — Data read API<br />\n — Verilog procedural interface (VPI) extensions for SystemVerilog constructs<br />\n — Concurrent assertion formal semantics """ #metaKeywords: null #metaDescription: null #shortDescription: "IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1197154800 {#7318 date: 2007-12-09 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "62530" -bookCollection: "" -pageCount: 668 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …}}	same as passed value

Option

Passed Value

Resolved Value

product

App\Entity\Product\Product {#7310
  #id: 10370
  #code: "IEEE00004256"
  #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
  #variants: Doctrine\ORM\PersistentCollection {#7743 …}
  #options: Doctrine\ORM\PersistentCollection {#7915
    #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …}
    #initialized: true
    -snapshot: [ …4]
    -owner: App\Entity\Product\Product {#7310}
    -association: [ …21]
    -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …}
    -backRefFieldName: null
    -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#260654 …}
    -isDirty: false
  }
  #associations: Doctrine\ORM\PersistentCollection {#7899 …}
  #createdAt: DateTime @1751039020 {#7274
    date: 2025-06-27 17:43:40.0 Europe/Paris (+02:00)
  }
  #updatedAt: DateTime @1754607611 {#7322
    date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
  }
  #enabled: true
  #translations: Doctrine\ORM\PersistentCollection {#7921 …}
  #translationsCache: [
    "en_US" => App\Entity\Product\ProductTranslation {#7920
      #locale: "en_US"
      #translatable: App\Entity\Product\Product {#7310}
      #id: 36489
      #name: "IEEE/IEC 62530:2007"
      #slug: "ieee-iec-62530-2007-ieee00004256-242022"
      #description: """
        New IEEE Standard - Superseded.<br />\n
        This standard provides a set of extensions to the IEEE 1364™ Verilog® hardware<br />\n
        description language (HDL) to aid in the creation and verification of abstract architectural level<br />\n
        models. It also includes design specification methods, embedded assertions language, testbench<br />\n
        language including coverage and an assertions application programming interface (API), and a<br />\n
        direct programming interface (DPI). This standard enables a productivity boost in design and<br />\n
        validation and covers design, simulation, validation, and formal assertion-based verification flows.<br />\n
        \t\t\t\t<br />\n
        This standard specifies extensions for a higher level of abstraction for modeling and verification with the<br />\n
        Verilog® hardware description language (HDL). These additions extend Verilog into the systems space and<br />\n
        the verification space. SystemVerilog is built on top of IEEE Std 1364™1 for the Verilog HDL. This<br />\n
        standard includes design specification methods, embedded assertions language, testbench language<br />\n
        including coverage and assertions application programming interface (API), and a direct programming<br />\n
        interface (DPI).<br />\n
        Throughout this standard, the following terms apply:<br />\n
        — Verilog refers to IEEE Std 1364 for the Verilog HDL.<br />\n
        — Verilog-2001 refers to IEEE Std 1364-2001 [B4]2 for the Verilog HDL.<br />\n
        — Verilog-1995 refers to IEEE Std 1364-1995 [B3] for the Verilog HDL.<br />\n
        — SystemVerilog refers to the extensions to the Verilog standard (IEEE Std 1364) as defined in this<br />\n
        standard.<br />\n
        SystemVerilog adds extended and new constructs to Verilog, including the following:<br />\n
        — Extensions to data types for better encapsulation and compactness of code and for tighter<br />\n
        specification<br />\n
        — C data types: int, typedef, struct, union, enum<br />\n
        — Other data types: bounded queues, logic (0, 1, X, Z) and bit (0, 1), tagged unions for safety<br />\n
        — Dynamic data types: string, classes, dynamic queues, dynamic arrays, associative arrays<br />\n
        including automatic memory management freeing users from deallocation issues<br />\n
        — Dynamic casting and bit-stream casting<br />\n
        — Automatic/static specification on a per-variable-instance basis<br />\n
        — Extended operators for concise description<br />\n
        — Wild equality and inequality<br />\n
        — Built-in methods to extend the language<br />\n
        — Operator overloading<br />\n
        — Streaming operators<br />\n
        — Set membership<br />\n
        — Extended procedural statements<br />\n
        — Pattern matching on selection statements for use with tagged unions<br />\n
        — Enhanced loop statements plus the foreach statement<br />\n
        — C-like jump statements: return, break, continue<br />\n
        — final blocks that execute at the end of simulation (inverse of initial)<br />\n
        — Extended event control and sequence events<br />\n
        — Enhanced process control<br />\n
        — Extensions to always blocks to include synthesis consistent simulation semantics<br />\n
        — Extensions to fork…join to model pipelines and for enhanced process control<br />\n
        — Fine-grain process control<br />\n
        — Enhanced tasks and functions<br />\n
        — C-like void functions<br />\n
        — Pass by reference<br />\n
        — Default arguments<br />\n
        — Argument binding by name<br />\n
        — Optional arguments<br />\n
        — Import/export functions for DPI<br />\n
        — Classes: object-oriented mechanism that provides abstraction, encapsulation, and safe pointer<br />\n
        capabilities<br />\n
        — Automated testbench support with random constraints<br />\n
        — Interprocess communication synchronization<br />\n
        — Semaphores<br />\n
        — Mailboxes<br />\n
        — Event extensions, event variables, and event sequencing<br />\n
        — Clarification and extension of the scheduling semantics<br />\n
        — Cycle-based functionality: clocking blocks and cycle-based attributes that help reduce development,<br />\n
        ease maintainability, and promote reusability<br />\n
        — Cycle-based signal drives and samples<br />\n
        — Synchronous samples<br />\n
        SystemVerilog is built on top of IEEE Std 1364. SystemVerilog improves the productivity, readability, and<br />\n
        reusability of Verilog-based code. The language enhancements in SystemVerilog provide more concise<br />\n
        hardware descriptions, while still providing an easy route with existing tools into current hardware<br />\n
        implementation flows. The enhancements also provide extensive support for directed and constrainedrandom<br />\n
        testbench development, coverage-driven verification, and assertion-based verification.<br />\n
        1Information on references can be found in Clause 2.<br />\n
        2The numbers in brackets correspond to the numbers in the bibliography in Annex K.<br />\n
        — Race-free program context<br />\n
        — Assertion mechanism for verifying design intent and functional coverage intent<br />\n
        — Property and sequence declarations<br />\n
        — Assertions and coverage statements with action blocks<br />\n
        — Extended hierarchy support<br />\n
        — Packages for declaration encapsulation with import for controlled access<br />\n
        — Compilation-unit scope nested modules and extern modules for separate compilation support<br />\n
        — Extension of port declarations to support interfaces, events, and variables<br />\n
        — $root to provide unambiguous access using hierarchical references<br />\n
        — Interfaces to encapsulate communication and facilitate communication-oriented design<br />\n
        — Functional coverage<br />\n
        — DPI for clean, efficient interoperation with other languages (C provided)<br />\n
        — Assertion API<br />\n
        — Coverage API<br />\n
        — Data read API<br />\n
        — Verilog procedural interface (VPI) extensions for SystemVerilog constructs<br />\n
        — Concurrent assertion formal semantics
        """
      #metaKeywords: null
      #metaDescription: null
      #shortDescription: "IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language"
      -notes: "Superseded"
    }
  ]
  #currentLocale: "en_US"
  #currentTranslation: null
  #fallbackLocale: "en_US"
  #variantSelectionMethod: "match"
  #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
  #channels: Doctrine\ORM\PersistentCollection {#7627 …}
  #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
  #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
  #averageRating: 0.0
  #images: Doctrine\ORM\PersistentCollection {#7644 …}
  -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
  -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
  -apiLastModifiedAt: DateTime @1754517600 {#7317
    date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
  }
  -lastUpdatedAt: DateTime @1578006000 {#7292
    date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
  }
  -author: ""
  -publishedAt: DateTime @1197154800 {#7318
    date: 2007-12-09 00:00:00.0 Europe/Paris (+01:00)
  }
  -releasedAt: null
  -confirmedAt: null
  -canceledAt: null
  -edition: null
  -coreDocument: "62530"
  -bookCollection: ""
  -pageCount: 668
  -documents: Doctrine\ORM\PersistentCollection {#7464 …}
  -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
}

same as passed value

Resolved Options

Option	Value
action	""
allow_extra_fields	false
allow_file_upload	false
attr	[]
attr_translation_parameters	[]
auto_initialize	true
block_name	null
block_prefix	null
by_reference	true
compound	true
constraints	[]
csrf_field_name	"_token"
csrf_message	"The CSRF token is invalid. Please try to resubmit the form."
csrf_protection	true
csrf_token_id	null
csrf_token_manager	Symfony\Component\Security\Csrf\CsrfTokenManager {#113483`-generator: Symfony\Component\Security\Csrf\TokenGenerator\UriSafeTokenGenerator {#113484 …} -storage: Symfony\Component\Security\Csrf\TokenStorage\SessionTokenStorage {#113485 …} -namespace: Closure() {#113487 …}`}
data_class	null
disabled	false
empty_data	Closure(FormInterface $form) {#113575`class: "Symfony\Component\Form\Extension\Core\Type\FormType"`}
entries	Doctrine\ORM\PersistentCollection {#7915#collection: Doctrine\Common\Collections\ArrayCollection {#7917 …} #initialized: true -snapshot: [ …4] -owner: App\Entity\Product\Product {#7310 #id: 10370 #code: "IEEE00004256" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915} #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751039020 {#7274 date: 2025-06-27 17:43:40.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#7322 date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 36489 #name: "IEEE/IEC 62530:2007" #slug: "ieee-iec-62530-2007-ieee00004256-242022" #description: """ New IEEE Standard - Superseded.<br />\n This standard provides a set of extensions to the IEEE 1364™ Verilog® hardware<br />\n description language (HDL) to aid in the creation and verification of abstract architectural level<br />\n models. It also includes design specification methods, embedded assertions language, testbench<br />\n language including coverage and an assertions application programming interface (API), and a<br />\n direct programming interface (DPI). This standard enables a productivity boost in design and<br />\n validation and covers design, simulation, validation, and formal assertion-based verification flows.<br />\n \t\t\t\t<br />\n This standard specifies extensions for a higher level of abstraction for modeling and verification with the<br />\n Verilog® hardware description language (HDL). These additions extend Verilog into the systems space and<br />\n the verification space. SystemVerilog is built on top of IEEE Std 1364™1 for the Verilog HDL. This<br />\n standard includes design specification methods, embedded assertions language, testbench language<br />\n including coverage and assertions application programming interface (API), and a direct programming<br />\n interface (DPI).<br />\n Throughout this standard, the following terms apply:<br />\n — Verilog refers to IEEE Std 1364 for the Verilog HDL.<br />\n — Verilog-2001 refers to IEEE Std 1364-2001 [B4]2 for the Verilog HDL.<br />\n — Verilog-1995 refers to IEEE Std 1364-1995 [B3] for the Verilog HDL.<br />\n — SystemVerilog refers to the extensions to the Verilog standard (IEEE Std 1364) as defined in this<br />\n standard.<br />\n SystemVerilog adds extended and new constructs to Verilog, including the following:<br />\n — Extensions to data types for better encapsulation and compactness of code and for tighter<br />\n specification<br />\n — C data types: int, typedef, struct, union, enum<br />\n — Other data types: bounded queues, logic (0, 1, X, Z) and bit (0, 1), tagged unions for safety<br />\n — Dynamic data types: string, classes, dynamic queues, dynamic arrays, associative arrays<br />\n including automatic memory management freeing users from deallocation issues<br />\n — Dynamic casting and bit-stream casting<br />\n — Automatic/static specification on a per-variable-instance basis<br />\n — Extended operators for concise description<br />\n — Wild equality and inequality<br />\n — Built-in methods to extend the language<br />\n — Operator overloading<br />\n — Streaming operators<br />\n — Set membership<br />\n — Extended procedural statements<br />\n — Pattern matching on selection statements for use with tagged unions<br />\n — Enhanced loop statements plus the foreach statement<br />\n — C-like jump statements: return, break, continue<br />\n — final blocks that execute at the end of simulation (inverse of initial)<br />\n — Extended event control and sequence events<br />\n — Enhanced process control<br />\n — Extensions to always blocks to include synthesis consistent simulation semantics<br />\n — Extensions to fork…join to model pipelines and for enhanced process control<br />\n — Fine-grain process control<br />\n — Enhanced tasks and functions<br />\n — C-like void functions<br />\n — Pass by reference<br />\n — Default arguments<br />\n — Argument binding by name<br />\n — Optional arguments<br />\n — Import/export functions for DPI<br />\n — Classes: object-oriented mechanism that provides abstraction, encapsulation, and safe pointer<br />\n capabilities<br />\n — Automated testbench support with random constraints<br />\n — Interprocess communication synchronization<br />\n — Semaphores<br />\n — Mailboxes<br />\n — Event extensions, event variables, and event sequencing<br />\n — Clarification and extension of the scheduling semantics<br />\n — Cycle-based functionality: clocking blocks and cycle-based attributes that help reduce development,<br />\n ease maintainability, and promote reusability<br />\n — Cycle-based signal drives and samples<br />\n — Synchronous samples<br />\n SystemVerilog is built on top of IEEE Std 1364. SystemVerilog improves the productivity, readability, and<br />\n reusability of Verilog-based code. The language enhancements in SystemVerilog provide more concise<br />\n hardware descriptions, while still providing an easy route with existing tools into current hardware<br />\n implementation flows. The enhancements also provide extensive support for directed and constrainedrandom<br />\n testbench development, coverage-driven verification, and assertion-based verification.<br />\n 1Information on references can be found in Clause 2.<br />\n 2The numbers in brackets correspond to the numbers in the bibliography in Annex K.<br />\n — Race-free program context<br />\n — Assertion mechanism for verifying design intent and functional coverage intent<br />\n — Property and sequence declarations<br />\n — Assertions and coverage statements with action blocks<br />\n — Extended hierarchy support<br />\n — Packages for declaration encapsulation with import for controlled access<br />\n — Compilation-unit scope nested modules and extern modules for separate compilation support<br />\n — Extension of port declarations to support interfaces, events, and variables<br />\n — $root to provide unambiguous access using hierarchical references<br />\n — Interfaces to encapsulate communication and facilitate communication-oriented design<br />\n — Functional coverage<br />\n — DPI for clean, efficient interoperation with other languages (C provided)<br />\n — Assertion API<br />\n — Coverage API<br />\n — Data read API<br />\n — Verilog procedural interface (VPI) extensions for SystemVerilog constructs<br />\n — Concurrent assertion formal semantics """ #metaKeywords: null #metaDescription: null #shortDescription: "IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1197154800 {#7318 date: 2007-12-09 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "62530" -bookCollection: "" -pageCount: 668 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } -association: [ …21] -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …} -backRefFieldName: null -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#260654 …} -isDirty: false}
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SystemVerilog improves the productivity, readability, and<br />\n reusability of Verilog-based code. The language enhancements in SystemVerilog provide more concise<br />\n hardware descriptions, while still providing an easy route with existing tools into current hardware<br />\n implementation flows. The enhancements also provide extensive support for directed and constrainedrandom<br />\n testbench development, coverage-driven verification, and assertion-based verification.<br />\n 1Information on references can be found in Clause 2.<br />\n 2The numbers in brackets correspond to the numbers in the bibliography in Annex K.<br />\n — Race-free program context<br />\n — Assertion mechanism for verifying design intent and functional coverage intent<br />\n — Property and sequence declarations<br />\n — Assertions and coverage statements with action blocks<br />\n — Extended hierarchy support<br />\n — Packages for declaration encapsulation with import for controlled access<br />\n — Compilation-unit scope nested modules and extern modules for separate compilation support<br />\n — Extension of port declarations to support interfaces, events, and variables<br />\n — $root to provide unambiguous access using hierarchical references<br />\n — Interfaces to encapsulate communication and facilitate communication-oriented design<br />\n — Functional coverage<br />\n — DPI for clean, efficient interoperation with other languages (C provided)<br />\n — Assertion API<br />\n — Coverage API<br />\n — Data read API<br />\n — Verilog procedural interface (VPI) extensions for SystemVerilog constructs<br />\n — Concurrent assertion formal semantics """ #metaKeywords: null #metaDescription: null #shortDescription: "IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1197154800 {#7318 date: 2007-12-09 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "62530" -bookCollection: "" -pageCount: 668 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …}}
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unique_block_prefix	"_sylius_add_to_cart_cartItem_variant"
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value	["red_line" => App\Entity\Product\ProductOptionValue {#8442 #id: 212 #code: "no" #option: App\Entity\Product\ProductOption {#8059 #id: 34 #code: "red_line" #position: 3 #values: Doctrine\ORM\PersistentCollection {#8062 …} #createdAt: DateTime @1737709966 {#8057 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #updatedAt: DateTime @1737709966 {#8058 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #translations: Doctrine\ORM\PersistentCollection {#8060 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductOptionTranslation {#8090 #locale: "en_US" #translatable: App\Entity\Product\ProductOption {#8059} #id: 52 #name: "Red Line" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" } #translations: Doctrine\ORM\PersistentCollection {#8423 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductOptionValueTranslation {#8483 #locale: "en_US" #translatable: App\Entity\Product\ProductOptionValue {#8442} #id: 836 #value: "No" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" -enabled: true } "format" => App\Entity\Product\ProductOptionValue {#8361 #id: 220 #code: "format_28" #option: App\Entity\Product\ProductOption {#7320 #id: 31 #code: "format" #position: 0 #values: Doctrine\ORM\PersistentCollection {#8026 …} #createdAt: DateTime @1737709966 {#7286 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #updatedAt: DateTime @1737709966 {#7985 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #translations: Doctrine\ORM\PersistentCollection {#7982 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductOptionTranslation {#8084 #locale: "en_US" #translatable: App\Entity\Product\ProductOption {#7320} #id: 40 #name: "Format" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" } #translations: Doctrine\ORM\PersistentCollection {#8349 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductOptionValueTranslation {#8475 #locale: "en_US" #translatable: App\Entity\Product\ProductOptionValue {#8361} #id: 868 #value: "Secure pdf" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" -enabled: true } "languages" => App\Entity\Product\ProductOptionValue {#8452 #id: 231 #code: "languages_1369" #option: App\Entity\Product\ProductOption {#8029 #id: 32 #code: "languages" #position: 1 #values: Doctrine\ORM\PersistentCollection {#7979 …} #createdAt: DateTime @1737709966 {#8021 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #updatedAt: DateTime @1737709966 {#8022 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #translations: Doctrine\ORM\PersistentCollection {#8019 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductOptionTranslation {#8076 #locale: "en_US" #translatable: App\Entity\Product\ProductOption {#8029} #id: 44 #name: "Languages" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" } #translations: Doctrine\ORM\PersistentCollection {#8456 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductOptionValueTranslation {#8458 #locale: "en_US" #translatable: App\Entity\Product\ProductOptionValue {#8452} #id: 912 #value: "English" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" -enabled: true } "multi_user" => App\Entity\Product\ProductOptionValue {#8455 #id: 291 #code: "multi_user_4736" #option: App\Entity\Product\ProductOption {#8050 #id: 33 #code: "multi_user" #position: 2 #values: Doctrine\ORM\PersistentCollection {#8055 …} #createdAt: DateTime @1737709966 {#8051 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #updatedAt: DateTime @1737709966 {#8052 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #translations: Doctrine\ORM\PersistentCollection {#8053 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductOptionTranslation {#8071 #locale: "en_US" #translatable: App\Entity\Product\ProductOption {#8050} #id: 48 #name: "Multi User" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" } #translations: Doctrine\ORM\PersistentCollection {#8453 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductOptionValueTranslation {#8489 #locale: "en_US" #translatable: App\Entity\Product\ProductOptionValue {#8455} #id: 1152 #value: "NC" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" -enabled: true }]

format

Form type:

"Sylius\Bundle\ProductBundle\Form\Type\ProductOptionValueChoiceType"

Errors

This form has no errors.

Default Data

Property

Value

Model Format

same as normalized format

Normalized Format

App\Entity\Product\ProductOptionValue {#8361
  #id: 220
  #code: "format_28"
  #option: App\Entity\Product\ProductOption {#7320
    #id: 31
    #code: "format"
    #position: 0
    #values: Doctrine\ORM\PersistentCollection {#8026 …}
    #createdAt: DateTime @1737709966 {#7286
      date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00)
    }
    #updatedAt: DateTime @1737709966 {#7985
      date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00)
    }
    #translations: Doctrine\ORM\PersistentCollection {#7982 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductOptionTranslation {#8084
        #locale: "en_US"
        #translatable: App\Entity\Product\ProductOption {#7320}
        #id: 40
        #name: "Format"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
  }
  #translations: Doctrine\ORM\PersistentCollection {#8349 …}
  #translationsCache: [
    "en_US" => App\Entity\Product\ProductOptionValueTranslation {#8475
      #locale: "en_US"
      #translatable: App\Entity\Product\ProductOptionValue {#8361}
      #id: 868
      #value: "Secure pdf"
    }
  ]
  #currentLocale: "en_US"
  #currentTranslation: null
  #fallbackLocale: "en_US"
  -enabled: true
}

View Format

"format_28"

Submitted Data

This form was not submitted.

Passed Options

Option	Passed Value	Resolved Value
block_name	"entry"	same as passed value
label	"Format"	same as passed value
only_available_values	true	same as passed value
option	App\Entity\Product\ProductOption {#7320#id: 31 #code: "format" #position: 0 #values: Doctrine\ORM\PersistentCollection {#8026 …} #createdAt: DateTime @1737709966 {#7286 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #updatedAt: DateTime @1737709966 {#7985 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #translations: Doctrine\ORM\PersistentCollection {#7982 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductOptionTranslation {#8084 #locale: "en_US" #translatable: App\Entity\Product\ProductOption {#7320} #id: 40 #name: "Format" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US"}	same as passed value
product	App\Entity\Product\Product {#7310#id: 10370 #code: "IEEE00004256" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …} #initialized: true -snapshot: [ …4] -owner: App\Entity\Product\Product {#7310} -association: [ …21] -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …} -backRefFieldName: null -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#260654 …} -isDirty: false } #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751039020 {#7274 date: 2025-06-27 17:43:40.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#7322 date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 36489 #name: "IEEE/IEC 62530:2007" #slug: "ieee-iec-62530-2007-ieee00004256-242022" #description: """ New IEEE Standard - Superseded.<br />\n This standard provides a set of extensions to the IEEE 1364™ Verilog® hardware<br />\n description language (HDL) to aid in the creation and verification of abstract architectural level<br />\n models. It also includes design specification methods, embedded assertions language, testbench<br />\n language including coverage and an assertions application programming interface (API), and a<br />\n direct programming interface (DPI). This standard enables a productivity boost in design and<br />\n validation and covers design, simulation, validation, and formal assertion-based verification flows.<br />\n \t\t\t\t<br />\n This standard specifies extensions for a higher level of abstraction for modeling and verification with the<br />\n Verilog® hardware description language (HDL). These additions extend Verilog into the systems space and<br />\n the verification space. SystemVerilog is built on top of IEEE Std 1364™1 for the Verilog HDL. This<br />\n standard includes design specification methods, embedded assertions language, testbench language<br />\n including coverage and assertions application programming interface (API), and a direct programming<br />\n interface (DPI).<br />\n Throughout this standard, the following terms apply:<br />\n — Verilog refers to IEEE Std 1364 for the Verilog HDL.<br />\n — Verilog-2001 refers to IEEE Std 1364-2001 [B4]2 for the Verilog HDL.<br />\n — Verilog-1995 refers to IEEE Std 1364-1995 [B3] for the Verilog HDL.<br />\n — SystemVerilog refers to the extensions to the Verilog standard (IEEE Std 1364) as defined in this<br />\n standard.<br />\n SystemVerilog adds extended and new constructs to Verilog, including the following:<br />\n — Extensions to data types for better encapsulation and compactness of code and for tighter<br />\n specification<br />\n — C data types: int, typedef, struct, union, enum<br />\n — Other data types: bounded queues, logic (0, 1, X, Z) and bit (0, 1), tagged unions for safety<br />\n — Dynamic data types: string, classes, dynamic queues, dynamic arrays, associative arrays<br />\n including automatic memory management freeing users from deallocation issues<br />\n — Dynamic casting and bit-stream casting<br />\n — Automatic/static specification on a per-variable-instance basis<br />\n — Extended operators for concise description<br />\n — Wild equality and inequality<br />\n — Built-in methods to extend the language<br />\n — Operator overloading<br />\n — Streaming operators<br />\n — Set membership<br />\n — Extended procedural statements<br />\n — Pattern matching on selection statements for use with tagged unions<br />\n — Enhanced loop statements plus the foreach statement<br />\n — C-like jump statements: return, break, continue<br />\n — final blocks that execute at the end of simulation (inverse of initial)<br />\n — Extended event control and sequence events<br />\n — Enhanced process control<br />\n — Extensions to always blocks to include synthesis consistent simulation semantics<br />\n — Extensions to fork…join to model pipelines and for enhanced process control<br />\n — Fine-grain process control<br />\n — Enhanced tasks and functions<br />\n — C-like void functions<br />\n — Pass by reference<br />\n — Default arguments<br />\n — Argument binding by name<br />\n — Optional arguments<br />\n — Import/export functions for DPI<br />\n — Classes: object-oriented mechanism that provides abstraction, encapsulation, and safe pointer<br />\n capabilities<br />\n — Automated testbench support with random constraints<br />\n — Interprocess communication synchronization<br />\n — Semaphores<br />\n — Mailboxes<br />\n — Event extensions, event variables, and event sequencing<br />\n — Clarification and extension of the scheduling semantics<br />\n — Cycle-based functionality: clocking blocks and cycle-based attributes that help reduce development,<br />\n ease maintainability, and promote reusability<br />\n — Cycle-based signal drives and samples<br />\n — Synchronous samples<br />\n SystemVerilog is built on top of IEEE Std 1364. SystemVerilog improves the productivity, readability, and<br />\n reusability of Verilog-based code. The language enhancements in SystemVerilog provide more concise<br />\n hardware descriptions, while still providing an easy route with existing tools into current hardware<br />\n implementation flows. The enhancements also provide extensive support for directed and constrainedrandom<br />\n testbench development, coverage-driven verification, and assertion-based verification.<br />\n 1Information on references can be found in Clause 2.<br />\n 2The numbers in brackets correspond to the numbers in the bibliography in Annex K.<br />\n — Race-free program context<br />\n — Assertion mechanism for verifying design intent and functional coverage intent<br />\n — Property and sequence declarations<br />\n — Assertions and coverage statements with action blocks<br />\n — Extended hierarchy support<br />\n — Packages for declaration encapsulation with import for controlled access<br />\n — Compilation-unit scope nested modules and extern modules for separate compilation support<br />\n — Extension of port declarations to support interfaces, events, and variables<br />\n — $root to provide unambiguous access using hierarchical references<br />\n — Interfaces to encapsulate communication and facilitate communication-oriented design<br />\n — Functional coverage<br />\n — DPI for clean, efficient interoperation with other languages (C provided)<br />\n — Assertion API<br />\n — Coverage API<br />\n — Data read API<br />\n — Verilog procedural interface (VPI) extensions for SystemVerilog constructs<br />\n — Concurrent assertion formal semantics """ #metaKeywords: null #metaDescription: null #shortDescription: "IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1197154800 {#7318 date: 2007-12-09 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "62530" -bookCollection: "" -pageCount: 668 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …}}	same as passed value
property_path	"[format]"	same as passed value

Resolved Options

Option	Value
action	""
allow_extra_fields	false
allow_file_upload	false
attr	[]
attr_translation_parameters	[]
auto_initialize	true
block_name	"entry"
block_prefix	null
by_reference	true
choice_attr	null
choice_filter	null
choice_label	"value"
choice_loader	null
choice_name	null
choice_translation_domain	false
choice_translation_parameters	[]
choice_value	"code"
choices	Doctrine\Common\Collections\ArrayCollection {#113616-elements: [ 7 => App\Entity\Product\ProductOptionValue {#8361 #id: 220 #code: "format_28" #option: App\Entity\Product\ProductOption {#7320 #id: 31 #code: "format" #position: 0 #values: Doctrine\ORM\PersistentCollection {#8026 …} #createdAt: DateTime @1737709966 {#7286 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #updatedAt: DateTime @1737709966 {#7985 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #translations: Doctrine\ORM\PersistentCollection {#7982 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductOptionTranslation {#8084 #locale: "en_US" #translatable: App\Entity\Product\ProductOption {#7320} #id: 40 #name: "Format" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" } #translations: Doctrine\ORM\PersistentCollection {#8349 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductOptionValueTranslation {#8475 #locale: "en_US" #translatable: App\Entity\Product\ProductOptionValue {#8361} #id: 868 #value: "Secure pdf" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" -enabled: true } ]}
compound	false
constraints	[]
csrf_field_name	"_token"
csrf_message	"The CSRF token is invalid. Please try to resubmit the form."
csrf_protection	true
csrf_token_id	null
csrf_token_manager	Symfony\Component\Security\Csrf\CsrfTokenManager {#113483`-generator: Symfony\Component\Security\Csrf\TokenGenerator\UriSafeTokenGenerator {#113484 …} -storage: Symfony\Component\Security\Csrf\TokenStorage\SessionTokenStorage {#113485 …} -namespace: Closure() {#113487 …}`}
data_class	null
disabled	false
duplicate_preferred_choices	true
empty_data	""
error_bubbling	false
error_mapping	[]
expanded	false
extra_fields_message	"This form should not contain extra fields."
form_attr	false
getter	null
group_by	null
help	null
help_attr	[]
help_html	false
help_translation_parameters	[]
inherit_data	false
invalid_message	"The selected choice is invalid."
invalid_message_parameters	[]
is_empty_callback	null
label	"Format"
label_attr	[]
label_format	null
label_html	false
label_translation_parameters	[]
mapped	true
method	"POST"
multiple	false
only_available_values	true
option	App\Entity\Product\ProductOption {#7320#id: 31 #code: "format" #position: 0 #values: Doctrine\ORM\PersistentCollection {#8026 …} #createdAt: DateTime @1737709966 {#7286 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #updatedAt: DateTime @1737709966 {#7985 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #translations: Doctrine\ORM\PersistentCollection {#7982 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductOptionTranslation {#8084 #locale: "en_US" #translatable: App\Entity\Product\ProductOption {#7320} #id: 40 #name: "Format" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US"}
placeholder	null
placeholder_attr	[]
post_max_size_message	"The uploaded file was too large. Please try to upload a smaller file."
preferred_choices	[]
priority	0
product	App\Entity\Product\Product {#7310#id: 10370 #code: "IEEE00004256" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …} #initialized: true -snapshot: [ …4] -owner: App\Entity\Product\Product {#7310} -association: [ …21] -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …} -backRefFieldName: null -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#260654 …} -isDirty: false } #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751039020 {#7274 date: 2025-06-27 17:43:40.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#7322 date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 36489 #name: "IEEE/IEC 62530:2007" #slug: "ieee-iec-62530-2007-ieee00004256-242022" #description: """ New IEEE Standard - Superseded.<br />\n This standard provides a set of extensions to the IEEE 1364™ Verilog® hardware<br />\n description language (HDL) to aid in the creation and verification of abstract architectural level<br />\n models. It also includes design specification methods, embedded assertions language, testbench<br />\n language including coverage and an assertions application programming interface (API), and a<br />\n direct programming interface (DPI). This standard enables a productivity boost in design and<br />\n validation and covers design, simulation, validation, and formal assertion-based verification flows.<br />\n \t\t\t\t<br />\n This standard specifies extensions for a higher level of abstraction for modeling and verification with the<br />\n Verilog® hardware description language (HDL). These additions extend Verilog into the systems space and<br />\n the verification space. SystemVerilog is built on top of IEEE Std 1364™1 for the Verilog HDL. This<br />\n standard includes design specification methods, embedded assertions language, testbench language<br />\n including coverage and assertions application programming interface (API), and a direct programming<br />\n interface (DPI).<br />\n Throughout this standard, the following terms apply:<br />\n — Verilog refers to IEEE Std 1364 for the Verilog HDL.<br />\n — Verilog-2001 refers to IEEE Std 1364-2001 [B4]2 for the Verilog HDL.<br />\n — Verilog-1995 refers to IEEE Std 1364-1995 [B3] for the Verilog HDL.<br />\n — SystemVerilog refers to the extensions to the Verilog standard (IEEE Std 1364) as defined in this<br />\n standard.<br />\n SystemVerilog adds extended and new constructs to Verilog, including the following:<br />\n — Extensions to data types for better encapsulation and compactness of code and for tighter<br />\n specification<br />\n — C data types: int, typedef, struct, union, enum<br />\n — Other data types: bounded queues, logic (0, 1, X, Z) and bit (0, 1), tagged unions for safety<br />\n — Dynamic data types: string, classes, dynamic queues, dynamic arrays, associative arrays<br />\n including automatic memory management freeing users from deallocation issues<br />\n — Dynamic casting and bit-stream casting<br />\n — Automatic/static specification on a per-variable-instance basis<br />\n — Extended operators for concise description<br />\n — Wild equality and inequality<br />\n — Built-in methods to extend the language<br />\n — Operator overloading<br />\n — Streaming operators<br />\n — Set membership<br />\n — Extended procedural statements<br />\n — Pattern matching on selection statements for use with tagged unions<br />\n — Enhanced loop statements plus the foreach statement<br />\n — C-like jump statements: return, break, continue<br />\n — final blocks that execute at the end of simulation (inverse of initial)<br />\n — Extended event control and sequence events<br />\n — Enhanced process control<br />\n — Extensions to always blocks to include synthesis consistent simulation semantics<br />\n — Extensions to fork…join to model pipelines and for enhanced process control<br />\n — Fine-grain process control<br />\n — Enhanced tasks and functions<br />\n — C-like void functions<br />\n — Pass by reference<br />\n — Default arguments<br />\n — Argument binding by name<br />\n — Optional arguments<br />\n — Import/export functions for DPI<br />\n — Classes: object-oriented mechanism that provides abstraction, encapsulation, and safe pointer<br />\n capabilities<br />\n — Automated testbench support with random constraints<br />\n — Interprocess communication synchronization<br />\n — Semaphores<br />\n — Mailboxes<br />\n — Event extensions, event variables, and event sequencing<br />\n — Clarification and extension of the scheduling semantics<br />\n — Cycle-based functionality: clocking blocks and cycle-based attributes that help reduce development,<br />\n ease maintainability, and promote reusability<br />\n — Cycle-based signal drives and samples<br />\n — Synchronous samples<br />\n SystemVerilog is built on top of IEEE Std 1364. SystemVerilog improves the productivity, readability, and<br />\n reusability of Verilog-based code. The language enhancements in SystemVerilog provide more concise<br />\n hardware descriptions, while still providing an easy route with existing tools into current hardware<br />\n implementation flows. The enhancements also provide extensive support for directed and constrainedrandom<br />\n testbench development, coverage-driven verification, and assertion-based verification.<br />\n 1Information on references can be found in Clause 2.<br />\n 2The numbers in brackets correspond to the numbers in the bibliography in Annex K.<br />\n — Race-free program context<br />\n — Assertion mechanism for verifying design intent and functional coverage intent<br />\n — Property and sequence declarations<br />\n — Assertions and coverage statements with action blocks<br />\n — Extended hierarchy support<br />\n — Packages for declaration encapsulation with import for controlled access<br />\n — Compilation-unit scope nested modules and extern modules for separate compilation support<br />\n — Extension of port declarations to support interfaces, events, and variables<br />\n — $root to provide unambiguous access using hierarchical references<br />\n — Interfaces to encapsulate communication and facilitate communication-oriented design<br />\n — Functional coverage<br />\n — DPI for clean, efficient interoperation with other languages (C provided)<br />\n — Assertion API<br />\n — Coverage API<br />\n — Data read API<br />\n — Verilog procedural interface (VPI) extensions for SystemVerilog constructs<br />\n — Concurrent assertion formal semantics """ #metaKeywords: null #metaDescription: null #shortDescription: "IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1197154800 {#7318 date: 2007-12-09 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "62530" -bookCollection: "" -pageCount: 668 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …}}
property_path	"[format]"
required	true
row_attr	[]
setter	null
translation_domain	null
trim	false
upload_max_size_message	Closure() {#113611`class: "Symfony\Component\Form\Extension\Validator\Type\UploadValidatorExtension" use: { $translator: Symfony\Component\Translation\DataCollectorTranslator {#2251 …} $message: Closure() {#113609 …} $translationDomain: "validators" }`}
validation_groups	null

View Vars

Variable	Value
action	""
attr	[]
attr_translation_parameters	[]
block_prefixes	[`"form" "choice" "sylius_product_option_value_choice" "_sylius_add_to_cart_cartItem_variant_entry"`]
cache_key	"_sylius_add_to_cart_cartItem_variant_entry_sylius_product_option_value_choice"
choice_translation_domain	false
choice_translation_parameters	[]
choices	[Symfony\Component\Form\ChoiceList\View\ChoiceView {#114026 +label: "Secure pdf" +value: "format_28" +data: App\Entity\Product\ProductOptionValue {#8361 #id: 220 #code: "format_28" #option: App\Entity\Product\ProductOption {#7320 #id: 31 #code: "format" #position: 0 #values: Doctrine\ORM\PersistentCollection {#8026 …} #createdAt: DateTime @1737709966 {#7286 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #updatedAt: DateTime @1737709966 {#7985 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #translations: Doctrine\ORM\PersistentCollection {#7982 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductOptionTranslation {#8084 #locale: "en_US" #translatable: App\Entity\Product\ProductOption {#7320} #id: 40 #name: "Format" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" } #translations: Doctrine\ORM\PersistentCollection {#8349 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductOptionValueTranslation {#8475 #locale: "en_US" #translatable: App\Entity\Product\ProductOptionValue {#8361} #id: 868 #value: "Secure pdf" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" -enabled: true } +attr: [] +labelTranslationParameters: [] }]
compound	false
data	App\Entity\Product\ProductOptionValue {#8361#id: 220 #code: "format_28" #option: App\Entity\Product\ProductOption {#7320 #id: 31 #code: "format" #position: 0 #values: Doctrine\ORM\PersistentCollection {#8026 …} #createdAt: DateTime @1737709966 {#7286 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #updatedAt: DateTime @1737709966 {#7985 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #translations: Doctrine\ORM\PersistentCollection {#7982 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductOptionTranslation {#8084 #locale: "en_US" #translatable: App\Entity\Product\ProductOption {#7320} #id: 40 #name: "Format" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" } #translations: Doctrine\ORM\PersistentCollection {#8349 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductOptionValueTranslation {#8475 #locale: "en_US" #translatable: App\Entity\Product\ProductOptionValue {#8361} #id: 868 #value: "Secure pdf" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" -enabled: true}
disabled	false
duplicate_preferred_choices	true
errors	Symfony\Component\Form\FormErrorIterator {#114018`-form: Symfony\Component\Form\Form {#114002 …} -errors: []`}
expanded	false
form	Symfony\Component\Form\FormView {#114017 …5}
full_name	"sylius_add_to_cart[cartItem][variant][format]"
help	null
help_attr	[]
help_html	false
help_translation_parameters	[]
id	"sylius_add_to_cart_cartItem_variant_format"
is_selected	Closure($choice, $value) {#114020`class: "Symfony\Component\Form\Extension\Core\Type\ChoiceType"`}
label	"Format"
label_attr	[]
label_format	null
label_html	false
label_translation_parameters	[]
method	"POST"
multipart	false
multiple	false
name	"format"
placeholder	null
placeholder_attr	[]
placeholder_in_choices	false
preferred_choices	[]
priority	0
required	true
row_attr	[]
separator	"-------------------"
submitted	false
translation_domain	null
unique_block_prefix	"_sylius_add_to_cart_cartItem_variant_entry"
valid	true
value	"format_28"

languages

Form type:

"Sylius\Bundle\ProductBundle\Form\Type\ProductOptionValueChoiceType"

Errors

This form has no errors.

Default Data

Property

Value

Model Format

same as normalized format

Normalized Format

App\Entity\Product\ProductOptionValue {#8452
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    #id: 32
    #code: "languages"
    #position: 1
    #values: Doctrine\ORM\PersistentCollection {#7979 …}
    #createdAt: DateTime @1737709966 {#8021
      date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00)
    }
    #updatedAt: DateTime @1737709966 {#8022
      date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00)
    }
    #translations: Doctrine\ORM\PersistentCollection {#8019 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductOptionTranslation {#8076
        #locale: "en_US"
        #translatable: App\Entity\Product\ProductOption {#8029}
        #id: 44
        #name: "Languages"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
  }
  #translations: Doctrine\ORM\PersistentCollection {#8456 …}
  #translationsCache: [
    "en_US" => App\Entity\Product\ProductOptionValueTranslation {#8458
      #locale: "en_US"
      #translatable: App\Entity\Product\ProductOptionValue {#8452}
      #id: 912
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  -enabled: true
}

View Format

"languages_1369"

Submitted Data

This form was not submitted.

Passed Options

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block_name	"entry"	same as passed value
label	"Languages"	same as passed value
only_available_values	true	same as passed value
option	App\Entity\Product\ProductOption {#8029#id: 32 #code: "languages" #position: 1 #values: Doctrine\ORM\PersistentCollection {#7979 …} #createdAt: DateTime @1737709966 {#8021 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #updatedAt: DateTime @1737709966 {#8022 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #translations: Doctrine\ORM\PersistentCollection {#8019 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductOptionTranslation {#8076 #locale: "en_US" #translatable: App\Entity\Product\ProductOption {#8029} #id: 44 #name: "Languages" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US"}	same as passed value
product	App\Entity\Product\Product {#7310#id: 10370 #code: "IEEE00004256" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …} #initialized: true -snapshot: [ …4] -owner: App\Entity\Product\Product {#7310} -association: [ …21] -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …} -backRefFieldName: null -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#260654 …} -isDirty: false } #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751039020 {#7274 date: 2025-06-27 17:43:40.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#7322 date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 36489 #name: "IEEE/IEC 62530:2007" #slug: "ieee-iec-62530-2007-ieee00004256-242022" #description: """ New IEEE Standard - Superseded.<br />\n This standard provides a set of extensions to the IEEE 1364™ Verilog® hardware<br />\n description language (HDL) to aid in the creation and verification of abstract architectural level<br />\n models. It also includes design specification methods, embedded assertions language, testbench<br />\n language including coverage and an assertions application programming interface (API), and a<br />\n direct programming interface (DPI). This standard enables a productivity boost in design and<br />\n validation and covers design, simulation, validation, and formal assertion-based verification flows.<br />\n \t\t\t\t<br />\n This standard specifies extensions for a higher level of abstraction for modeling and verification with the<br />\n Verilog® hardware description language (HDL). These additions extend Verilog into the systems space and<br />\n the verification space. SystemVerilog is built on top of IEEE Std 1364™1 for the Verilog HDL. This<br />\n standard includes design specification methods, embedded assertions language, testbench language<br />\n including coverage and assertions application programming interface (API), and a direct programming<br />\n interface (DPI).<br />\n Throughout this standard, the following terms apply:<br />\n — Verilog refers to IEEE Std 1364 for the Verilog HDL.<br />\n — Verilog-2001 refers to IEEE Std 1364-2001 [B4]2 for the Verilog HDL.<br />\n — Verilog-1995 refers to IEEE Std 1364-1995 [B3] for the Verilog HDL.<br />\n — SystemVerilog refers to the extensions to the Verilog standard (IEEE Std 1364) as defined in this<br />\n standard.<br />\n SystemVerilog adds extended and new constructs to Verilog, including the following:<br />\n — Extensions to data types for better encapsulation and compactness of code and for tighter<br />\n specification<br />\n — C data types: int, typedef, struct, union, enum<br />\n — Other data types: bounded queues, logic (0, 1, X, Z) and bit (0, 1), tagged unions for safety<br />\n — Dynamic data types: string, classes, dynamic queues, dynamic arrays, associative arrays<br />\n including automatic memory management freeing users from deallocation issues<br />\n — Dynamic casting and bit-stream casting<br />\n — Automatic/static specification on a per-variable-instance basis<br />\n — Extended operators for concise description<br />\n — Wild equality and inequality<br />\n — Built-in methods to extend the language<br />\n — Operator overloading<br />\n — Streaming operators<br />\n — Set membership<br />\n — Extended procedural statements<br />\n — Pattern matching on selection statements for use with tagged unions<br />\n — Enhanced loop statements plus the foreach statement<br />\n — C-like jump statements: return, break, continue<br />\n — final blocks that execute at the end of simulation (inverse of initial)<br />\n — Extended event control and sequence events<br />\n — Enhanced process control<br />\n — Extensions to always blocks to include synthesis consistent simulation semantics<br />\n — Extensions to fork…join to model pipelines and for enhanced process control<br />\n — Fine-grain process control<br />\n — Enhanced tasks and functions<br />\n — C-like void functions<br />\n — Pass by reference<br />\n — Default arguments<br />\n — Argument binding by name<br />\n — Optional arguments<br />\n — Import/export functions for DPI<br />\n — Classes: object-oriented mechanism that provides abstraction, encapsulation, and safe pointer<br />\n capabilities<br />\n — Automated testbench support with random constraints<br />\n — Interprocess communication synchronization<br />\n — Semaphores<br />\n — Mailboxes<br />\n — Event extensions, event variables, and event sequencing<br />\n — Clarification and extension of the scheduling semantics<br />\n — Cycle-based functionality: clocking blocks and cycle-based attributes that help reduce development,<br />\n ease maintainability, and promote reusability<br />\n — Cycle-based signal drives and samples<br />\n — Synchronous samples<br />\n SystemVerilog is built on top of IEEE Std 1364. SystemVerilog improves the productivity, readability, and<br />\n reusability of Verilog-based code. The language enhancements in SystemVerilog provide more concise<br />\n hardware descriptions, while still providing an easy route with existing tools into current hardware<br />\n implementation flows. The enhancements also provide extensive support for directed and constrainedrandom<br />\n testbench development, coverage-driven verification, and assertion-based verification.<br />\n 1Information on references can be found in Clause 2.<br />\n 2The numbers in brackets correspond to the numbers in the bibliography in Annex K.<br />\n — Race-free program context<br />\n — Assertion mechanism for verifying design intent and functional coverage intent<br />\n — Property and sequence declarations<br />\n — Assertions and coverage statements with action blocks<br />\n — Extended hierarchy support<br />\n — Packages for declaration encapsulation with import for controlled access<br />\n — Compilation-unit scope nested modules and extern modules for separate compilation support<br />\n — Extension of port declarations to support interfaces, events, and variables<br />\n — $root to provide unambiguous access using hierarchical references<br />\n — Interfaces to encapsulate communication and facilitate communication-oriented design<br />\n — Functional coverage<br />\n — DPI for clean, efficient interoperation with other languages (C provided)<br />\n — Assertion API<br />\n — Coverage API<br />\n — Data read API<br />\n — Verilog procedural interface (VPI) extensions for SystemVerilog constructs<br />\n — Concurrent assertion formal semantics """ #metaKeywords: null #metaDescription: null #shortDescription: "IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1197154800 {#7318 date: 2007-12-09 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "62530" -bookCollection: "" -pageCount: 668 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …}}	same as passed value
property_path	"[languages]"	same as passed value

Resolved Options

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action	""
allow_extra_fields	false
allow_file_upload	false
attr	[]
attr_translation_parameters	[]
auto_initialize	true
block_name	"entry"
block_prefix	null
by_reference	true
choice_attr	null
choice_filter	null
choice_label	"value"
choice_loader	null
choice_name	null
choice_translation_domain	false
choice_translation_parameters	[]
choice_value	"code"
choices	Doctrine\Common\Collections\ArrayCollection {#113667-elements: [ 8 => App\Entity\Product\ProductOptionValue {#8452 #id: 231 #code: "languages_1369" #option: App\Entity\Product\ProductOption {#8029 #id: 32 #code: "languages" #position: 1 #values: Doctrine\ORM\PersistentCollection {#7979 …} #createdAt: DateTime @1737709966 {#8021 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #updatedAt: DateTime @1737709966 {#8022 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #translations: Doctrine\ORM\PersistentCollection {#8019 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductOptionTranslation {#8076 #locale: "en_US" #translatable: App\Entity\Product\ProductOption {#8029} #id: 44 #name: "Languages" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" } #translations: Doctrine\ORM\PersistentCollection {#8456 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductOptionValueTranslation {#8458 #locale: "en_US" #translatable: App\Entity\Product\ProductOptionValue {#8452} #id: 912 #value: "English" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" -enabled: true } ]}
compound	false
constraints	[]
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csrf_message	"The CSRF token is invalid. Please try to resubmit the form."
csrf_protection	true
csrf_token_id	null
csrf_token_manager	Symfony\Component\Security\Csrf\CsrfTokenManager {#113483`-generator: Symfony\Component\Security\Csrf\TokenGenerator\UriSafeTokenGenerator {#113484 …} -storage: Symfony\Component\Security\Csrf\TokenStorage\SessionTokenStorage {#113485 …} -namespace: Closure() {#113487 …}`}
data_class	null
disabled	false
duplicate_preferred_choices	true
empty_data	""
error_bubbling	false
error_mapping	[]
expanded	false
extra_fields_message	"This form should not contain extra fields."
form_attr	false
getter	null
group_by	null
help	null
help_attr	[]
help_html	false
help_translation_parameters	[]
inherit_data	false
invalid_message	"The selected choice is invalid."
invalid_message_parameters	[]
is_empty_callback	null
label	"Languages"
label_attr	[]
label_format	null
label_html	false
label_translation_parameters	[]
mapped	true
method	"POST"
multiple	false
only_available_values	true
option	App\Entity\Product\ProductOption {#8029#id: 32 #code: "languages" #position: 1 #values: Doctrine\ORM\PersistentCollection {#7979 …} #createdAt: DateTime @1737709966 {#8021 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #updatedAt: DateTime @1737709966 {#8022 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #translations: Doctrine\ORM\PersistentCollection {#8019 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductOptionTranslation {#8076 #locale: "en_US" #translatable: App\Entity\Product\ProductOption {#8029} #id: 44 #name: "Languages" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US"}
placeholder	null
placeholder_attr	[]
post_max_size_message	"The uploaded file was too large. Please try to upload a smaller file."
preferred_choices	[]
priority	0
product	App\Entity\Product\Product {#7310#id: 10370 #code: "IEEE00004256" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …} #initialized: true -snapshot: [ …4] -owner: App\Entity\Product\Product {#7310} -association: [ …21] -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …} -backRefFieldName: null -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#260654 …} -isDirty: false } #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751039020 {#7274 date: 2025-06-27 17:43:40.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#7322 date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 36489 #name: "IEEE/IEC 62530:2007" #slug: "ieee-iec-62530-2007-ieee00004256-242022" #description: """ New IEEE Standard - Superseded.<br />\n This standard provides a set of extensions to the IEEE 1364™ Verilog® hardware<br />\n description language (HDL) to aid in the creation and verification of abstract architectural level<br />\n models. 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This<br />\n standard includes design specification methods, embedded assertions language, testbench language<br />\n including coverage and assertions application programming interface (API), and a direct programming<br />\n interface (DPI).<br />\n Throughout this standard, the following terms apply:<br />\n — Verilog refers to IEEE Std 1364 for the Verilog HDL.<br />\n — Verilog-2001 refers to IEEE Std 1364-2001 [B4]2 for the Verilog HDL.<br />\n — Verilog-1995 refers to IEEE Std 1364-1995 [B3] for the Verilog HDL.<br />\n — SystemVerilog refers to the extensions to the Verilog standard (IEEE Std 1364) as defined in this<br />\n standard.<br />\n SystemVerilog adds extended and new constructs to Verilog, including the following:<br />\n — Extensions to data types for better encapsulation and compactness of code and for tighter<br />\n specification<br />\n — C data types: int, typedef, struct, union, enum<br />\n — Other data types: bounded queues, logic (0, 1, X, Z) and bit (0, 1), tagged unions for safety<br />\n — Dynamic data types: string, classes, dynamic queues, dynamic arrays, associative arrays<br />\n including automatic memory management freeing users from deallocation issues<br />\n — Dynamic casting and bit-stream casting<br />\n — Automatic/static specification on a per-variable-instance basis<br />\n — Extended operators for concise description<br />\n — Wild equality and inequality<br />\n — Built-in methods to extend the language<br />\n — Operator overloading<br />\n — Streaming operators<br />\n — Set membership<br />\n — Extended procedural statements<br />\n — Pattern matching on selection statements for use with tagged unions<br />\n — Enhanced loop statements plus the foreach statement<br />\n — C-like jump statements: return, break, continue<br />\n — final blocks that execute at the end of simulation (inverse of initial)<br />\n — Extended event control and sequence events<br />\n — Enhanced process control<br />\n — Extensions to always blocks to include synthesis consistent simulation semantics<br />\n — Extensions to fork…join to model pipelines and for enhanced process control<br />\n — Fine-grain process control<br />\n — Enhanced tasks and functions<br />\n — C-like void functions<br />\n — Pass by reference<br />\n — Default arguments<br />\n — Argument binding by name<br />\n — Optional arguments<br />\n — Import/export functions for DPI<br />\n — Classes: object-oriented mechanism that provides abstraction, encapsulation, and safe pointer<br />\n capabilities<br />\n — Automated testbench support with random constraints<br />\n — Interprocess communication synchronization<br />\n — Semaphores<br />\n — Mailboxes<br />\n — Event extensions, event variables, and event sequencing<br />\n — Clarification and extension of the scheduling semantics<br />\n — Cycle-based functionality: clocking blocks and cycle-based attributes that help reduce development,<br />\n ease maintainability, and promote reusability<br />\n — Cycle-based signal drives and samples<br />\n — Synchronous samples<br />\n SystemVerilog is built on top of IEEE Std 1364. SystemVerilog improves the productivity, readability, and<br />\n reusability of Verilog-based code. The language enhancements in SystemVerilog provide more concise<br />\n hardware descriptions, while still providing an easy route with existing tools into current hardware<br />\n implementation flows. The enhancements also provide extensive support for directed and constrainedrandom<br />\n testbench development, coverage-driven verification, and assertion-based verification.<br />\n 1Information on references can be found in Clause 2.<br />\n 2The numbers in brackets correspond to the numbers in the bibliography in Annex K.<br />\n — Race-free program context<br />\n — Assertion mechanism for verifying design intent and functional coverage intent<br />\n — Property and sequence declarations<br />\n — Assertions and coverage statements with action blocks<br />\n — Extended hierarchy support<br />\n — Packages for declaration encapsulation with import for controlled access<br />\n — Compilation-unit scope nested modules and extern modules for separate compilation support<br />\n — Extension of port declarations to support interfaces, events, and variables<br />\n — $root to provide unambiguous access using hierarchical references<br />\n — Interfaces to encapsulate communication and facilitate communication-oriented design<br />\n — Functional coverage<br />\n — DPI for clean, efficient interoperation with other languages (C provided)<br />\n — Assertion API<br />\n — Coverage API<br />\n — Data read API<br />\n — Verilog procedural interface (VPI) extensions for SystemVerilog constructs<br />\n — Concurrent assertion formal semantics """ #metaKeywords: null #metaDescription: null #shortDescription: "IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1197154800 {#7318 date: 2007-12-09 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "62530" -bookCollection: "" -pageCount: 668 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …}}
property_path	"[languages]"
required	true
row_attr	[]
setter	null
translation_domain	null
trim	false
upload_max_size_message	Closure() {#113663`class: "Symfony\Component\Form\Extension\Validator\Type\UploadValidatorExtension" use: { $translator: Symfony\Component\Translation\DataCollectorTranslator {#2251 …} $message: Closure() {#113686 …} $translationDomain: "validators" }`}
validation_groups	null

View Vars

Variable	Value
action	""
attr	[]
attr_translation_parameters	[]
block_prefixes	[`"form" "choice" "sylius_product_option_value_choice" "_sylius_add_to_cart_cartItem_variant_entry"`]
cache_key	"_sylius_add_to_cart_cartItem_variant_entry_sylius_product_option_value_choice"
choice_translation_domain	false
choice_translation_parameters	[]
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errors	Symfony\Component\Form\FormErrorIterator {#114031`-form: Symfony\Component\Form\Form {#113999 …} -errors: []`}
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form	Symfony\Component\Form\FormView {#114019 …5}
full_name	"sylius_add_to_cart[cartItem][variant][languages]"
help	null
help_attr	[]
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is_selected	Closure($choice, $value) {#114033`class: "Symfony\Component\Form\Extension\Core\Type\ChoiceType"`}
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multi_user

Form type:

"Sylius\Bundle\ProductBundle\Form\Type\ProductOptionValueChoiceType"

Errors

This form has no errors.

Default Data

Property

Value

Model Format

same as normalized format

Normalized Format

App\Entity\Product\ProductOptionValue {#8455
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    #updatedAt: DateTime @1737709966 {#8052
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    }
    #translations: Doctrine\ORM\PersistentCollection {#8053 …}
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      "en_US" => App\Entity\Product\ProductOptionTranslation {#8071
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View Format

"multi_user_4736"

Submitted Data

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Passed Options

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block_name	"entry"	same as passed value
label	"Multi User"	same as passed value
only_available_values	true	same as passed value
option	App\Entity\Product\ProductOption {#8050#id: 33 #code: "multi_user" #position: 2 #values: Doctrine\ORM\PersistentCollection {#8055 …} #createdAt: DateTime @1737709966 {#8051 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #updatedAt: DateTime @1737709966 {#8052 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #translations: Doctrine\ORM\PersistentCollection {#8053 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductOptionTranslation {#8071 #locale: "en_US" #translatable: App\Entity\Product\ProductOption {#8050} #id: 48 #name: "Multi User" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US"}	same as passed value
product	App\Entity\Product\Product {#7310#id: 10370 #code: "IEEE00004256" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …} #initialized: true -snapshot: [ …4] -owner: App\Entity\Product\Product {#7310} -association: [ …21] -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …} -backRefFieldName: null -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#260654 …} -isDirty: false } #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751039020 {#7274 date: 2025-06-27 17:43:40.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#7322 date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 36489 #name: "IEEE/IEC 62530:2007" #slug: "ieee-iec-62530-2007-ieee00004256-242022" #description: """ New IEEE Standard - Superseded.<br />\n This standard provides a set of extensions to the IEEE 1364™ Verilog® hardware<br />\n description language (HDL) to aid in the creation and verification of abstract architectural level<br />\n models. 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This<br />\n standard includes design specification methods, embedded assertions language, testbench language<br />\n including coverage and assertions application programming interface (API), and a direct programming<br />\n interface (DPI).<br />\n Throughout this standard, the following terms apply:<br />\n — Verilog refers to IEEE Std 1364 for the Verilog HDL.<br />\n — Verilog-2001 refers to IEEE Std 1364-2001 [B4]2 for the Verilog HDL.<br />\n — Verilog-1995 refers to IEEE Std 1364-1995 [B3] for the Verilog HDL.<br />\n — SystemVerilog refers to the extensions to the Verilog standard (IEEE Std 1364) as defined in this<br />\n standard.<br />\n SystemVerilog adds extended and new constructs to Verilog, including the following:<br />\n — Extensions to data types for better encapsulation and compactness of code and for tighter<br />\n specification<br />\n — C data types: int, typedef, struct, union, enum<br />\n — Other data types: bounded queues, logic (0, 1, X, Z) and bit (0, 1), tagged unions for safety<br />\n — Dynamic data types: string, classes, dynamic queues, dynamic arrays, associative arrays<br />\n including automatic memory management freeing users from deallocation issues<br />\n — Dynamic casting and bit-stream casting<br />\n — Automatic/static specification on a per-variable-instance basis<br />\n — Extended operators for concise description<br />\n — Wild equality and inequality<br />\n — Built-in methods to extend the language<br />\n — Operator overloading<br />\n — Streaming operators<br />\n — Set membership<br />\n — Extended procedural statements<br />\n — Pattern matching on selection statements for use with tagged unions<br />\n — Enhanced loop statements plus the foreach statement<br />\n — C-like jump statements: return, break, continue<br />\n — final blocks that execute at the end of simulation (inverse of initial)<br />\n — Extended event control and sequence events<br />\n — Enhanced process control<br />\n — Extensions to always blocks to include synthesis consistent simulation semantics<br />\n — Extensions to fork…join to model pipelines and for enhanced process control<br />\n — Fine-grain process control<br />\n — Enhanced tasks and functions<br />\n — C-like void functions<br />\n — Pass by reference<br />\n — Default arguments<br />\n — Argument binding by name<br />\n — Optional arguments<br />\n — Import/export functions for DPI<br />\n — Classes: object-oriented mechanism that provides abstraction, encapsulation, and safe pointer<br />\n capabilities<br />\n — Automated testbench support with random constraints<br />\n — Interprocess communication synchronization<br />\n — Semaphores<br />\n — Mailboxes<br />\n — Event extensions, event variables, and event sequencing<br />\n — Clarification and extension of the scheduling semantics<br />\n — Cycle-based functionality: clocking blocks and cycle-based attributes that help reduce development,<br />\n ease maintainability, and promote reusability<br />\n — Cycle-based signal drives and samples<br />\n — Synchronous samples<br />\n SystemVerilog is built on top of IEEE Std 1364. SystemVerilog improves the productivity, readability, and<br />\n reusability of Verilog-based code. The language enhancements in SystemVerilog provide more concise<br />\n hardware descriptions, while still providing an easy route with existing tools into current hardware<br />\n implementation flows. The enhancements also provide extensive support for directed and constrainedrandom<br />\n testbench development, coverage-driven verification, and assertion-based verification.<br />\n 1Information on references can be found in Clause 2.<br />\n 2The numbers in brackets correspond to the numbers in the bibliography in Annex K.<br />\n — Race-free program context<br />\n — Assertion mechanism for verifying design intent and functional coverage intent<br />\n — Property and sequence declarations<br />\n — Assertions and coverage statements with action blocks<br />\n — Extended hierarchy support<br />\n — Packages for declaration encapsulation with import for controlled access<br />\n — Compilation-unit scope nested modules and extern modules for separate compilation support<br />\n — Extension of port declarations to support interfaces, events, and variables<br />\n — $root to provide unambiguous access using hierarchical references<br />\n — Interfaces to encapsulate communication and facilitate communication-oriented design<br />\n — Functional coverage<br />\n — DPI for clean, efficient interoperation with other languages (C provided)<br />\n — Assertion API<br />\n — Coverage API<br />\n — Data read API<br />\n — Verilog procedural interface (VPI) extensions for SystemVerilog constructs<br />\n — Concurrent assertion formal semantics """ #metaKeywords: null #metaDescription: null #shortDescription: "IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1197154800 {#7318 date: 2007-12-09 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "62530" -bookCollection: "" -pageCount: 668 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …}}	same as passed value
property_path	"[multi_user]"	same as passed value

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attr	[]
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choice_label	"value"
choice_loader	null
choice_name	null
choice_translation_domain	false
choice_translation_parameters	[]
choice_value	"code"
choices	Doctrine\Common\Collections\ArrayCollection {#113884-elements: [ 1 => App\Entity\Product\ProductOptionValue {#8455 #id: 291 #code: "multi_user_4736" #option: App\Entity\Product\ProductOption {#8050 #id: 33 #code: "multi_user" #position: 2 #values: Doctrine\ORM\PersistentCollection {#8055 …} #createdAt: DateTime @1737709966 {#8051 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #updatedAt: DateTime @1737709966 {#8052 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #translations: Doctrine\ORM\PersistentCollection {#8053 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductOptionTranslation {#8071 #locale: "en_US" #translatable: App\Entity\Product\ProductOption {#8050} #id: 48 #name: "Multi User" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" } #translations: Doctrine\ORM\PersistentCollection {#8453 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductOptionValueTranslation {#8489 #locale: "en_US" #translatable: App\Entity\Product\ProductOptionValue {#8455} #id: 1152 #value: "NC" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" -enabled: true } ]}
compound	false
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csrf_message	"The CSRF token is invalid. Please try to resubmit the form."
csrf_protection	true
csrf_token_id	null
csrf_token_manager	Symfony\Component\Security\Csrf\CsrfTokenManager {#113483`-generator: Symfony\Component\Security\Csrf\TokenGenerator\UriSafeTokenGenerator {#113484 …} -storage: Symfony\Component\Security\Csrf\TokenStorage\SessionTokenStorage {#113485 …} -namespace: Closure() {#113487 …}`}
data_class	null
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duplicate_preferred_choices	true
empty_data	""
error_bubbling	false
error_mapping	[]
expanded	false
extra_fields_message	"This form should not contain extra fields."
form_attr	false
getter	null
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help	null
help_attr	[]
help_html	false
help_translation_parameters	[]
inherit_data	false
invalid_message	"The selected choice is invalid."
invalid_message_parameters	[]
is_empty_callback	null
label	"Multi User"
label_attr	[]
label_format	null
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label_translation_parameters	[]
mapped	true
method	"POST"
multiple	false
only_available_values	true
option	App\Entity\Product\ProductOption {#8050#id: 33 #code: "multi_user" #position: 2 #values: Doctrine\ORM\PersistentCollection {#8055 …} #createdAt: DateTime @1737709966 {#8051 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #updatedAt: DateTime @1737709966 {#8052 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #translations: Doctrine\ORM\PersistentCollection {#8053 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductOptionTranslation {#8071 #locale: "en_US" #translatable: App\Entity\Product\ProductOption {#8050} #id: 48 #name: "Multi User" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US"}
placeholder	null
placeholder_attr	[]
post_max_size_message	"The uploaded file was too large. Please try to upload a smaller file."
preferred_choices	[]
priority	0
product	App\Entity\Product\Product {#7310#id: 10370 #code: "IEEE00004256" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …} #initialized: true -snapshot: [ …4] -owner: App\Entity\Product\Product {#7310} -association: [ …21] -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …} -backRefFieldName: null -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#260654 …} -isDirty: false } #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751039020 {#7274 date: 2025-06-27 17:43:40.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#7322 date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 36489 #name: "IEEE/IEC 62530:2007" #slug: "ieee-iec-62530-2007-ieee00004256-242022" #description: """ New IEEE Standard - Superseded.<br />\n This standard provides a set of extensions to the IEEE 1364™ Verilog® hardware<br />\n description language (HDL) to aid in the creation and verification of abstract architectural level<br />\n models. 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SystemVerilog improves the productivity, readability, and<br />\n reusability of Verilog-based code. The language enhancements in SystemVerilog provide more concise<br />\n hardware descriptions, while still providing an easy route with existing tools into current hardware<br />\n implementation flows. The enhancements also provide extensive support for directed and constrainedrandom<br />\n testbench development, coverage-driven verification, and assertion-based verification.<br />\n 1Information on references can be found in Clause 2.<br />\n 2The numbers in brackets correspond to the numbers in the bibliography in Annex K.<br />\n — Race-free program context<br />\n — Assertion mechanism for verifying design intent and functional coverage intent<br />\n — Property and sequence declarations<br />\n — Assertions and coverage statements with action blocks<br />\n — Extended hierarchy support<br />\n — Packages for declaration encapsulation with import for controlled access<br />\n — Compilation-unit scope nested modules and extern modules for separate compilation support<br />\n — Extension of port declarations to support interfaces, events, and variables<br />\n — $root to provide unambiguous access using hierarchical references<br />\n — Interfaces to encapsulate communication and facilitate communication-oriented design<br />\n — Functional coverage<br />\n — DPI for clean, efficient interoperation with other languages (C provided)<br />\n — Assertion API<br />\n — Coverage API<br />\n — Data read API<br />\n — Verilog procedural interface (VPI) extensions for SystemVerilog constructs<br />\n — Concurrent assertion formal semantics """ #metaKeywords: null #metaDescription: null #shortDescription: "IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1197154800 {#7318 date: 2007-12-09 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "62530" -bookCollection: "" -pageCount: 668 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …}}
property_path	"[multi_user]"
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row_attr	[]
setter	null
translation_domain	null
trim	false
upload_max_size_message	Closure() {#113897`class: "Symfony\Component\Form\Extension\Validator\Type\UploadValidatorExtension" use: { $translator: Symfony\Component\Translation\DataCollectorTranslator {#2251 …} $message: Closure() {#113895 …} $translationDomain: "validators" }`}
validation_groups	null

View Vars

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action	""
attr	[]
attr_translation_parameters	[]
block_prefixes	[`"form" "choice" "sylius_product_option_value_choice" "_sylius_add_to_cart_cartItem_variant_entry"`]
cache_key	"_sylius_add_to_cart_cartItem_variant_entry_sylius_product_option_value_choice"
choice_translation_domain	false
choice_translation_parameters	[]
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compound	false
data	App\Entity\Product\ProductOptionValue {#8455#id: 291 #code: "multi_user_4736" #option: App\Entity\Product\ProductOption {#8050 #id: 33 #code: "multi_user" #position: 2 #values: Doctrine\ORM\PersistentCollection {#8055 …} #createdAt: DateTime @1737709966 {#8051 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #updatedAt: DateTime @1737709966 {#8052 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #translations: Doctrine\ORM\PersistentCollection {#8053 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductOptionTranslation {#8071 #locale: "en_US" #translatable: App\Entity\Product\ProductOption {#8050} #id: 48 #name: "Multi User" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" } #translations: Doctrine\ORM\PersistentCollection {#8453 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductOptionValueTranslation {#8489 #locale: "en_US" #translatable: App\Entity\Product\ProductOptionValue {#8455} #id: 1152 #value: "NC" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" -enabled: true}
disabled	false
duplicate_preferred_choices	true
errors	Symfony\Component\Form\FormErrorIterator {#114043`-form: Symfony\Component\Form\Form {#113996 …} -errors: []`}
expanded	false
form	Symfony\Component\Form\FormView {#114030 …5}
full_name	"sylius_add_to_cart[cartItem][variant][multi_user]"
help	null
help_attr	[]
help_html	false
help_translation_parameters	[]
id	"sylius_add_to_cart_cartItem_variant_multi_user"
is_selected	Closure($choice, $value) {#114045`class: "Symfony\Component\Form\Extension\Core\Type\ChoiceType"`}
label	"Multi User"
label_attr	[]
label_format	null
label_html	false
label_translation_parameters	[]
method	"POST"
multipart	false
multiple	false
name	"multi_user"
placeholder	null
placeholder_attr	[]
placeholder_in_choices	false
preferred_choices	[]
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required	true
row_attr	[]
separator	"-------------------"
submitted	false
translation_domain	null
unique_block_prefix	"_sylius_add_to_cart_cartItem_variant_entry"
valid	true
value	"multi_user_4736"

red_line

Form type:

"Sylius\Bundle\ProductBundle\Form\Type\ProductOptionValueChoiceType"

Errors

This form has no errors.

Default Data

Property

Value

Model Format

same as normalized format

Normalized Format

App\Entity\Product\ProductOptionValue {#8442
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  #code: "no"
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    #id: 34
    #code: "red_line"
    #position: 3
    #values: Doctrine\ORM\PersistentCollection {#8062 …}
    #createdAt: DateTime @1737709966 {#8057
      date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00)
    }
    #updatedAt: DateTime @1737709966 {#8058
      date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00)
    }
    #translations: Doctrine\ORM\PersistentCollection {#8060 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductOptionTranslation {#8090
        #locale: "en_US"
        #translatable: App\Entity\Product\ProductOption {#8059}
        #id: 52
        #name: "Red Line"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
  }
  #translations: Doctrine\ORM\PersistentCollection {#8423 …}
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    "en_US" => App\Entity\Product\ProductOptionValueTranslation {#8483
      #locale: "en_US"
      #translatable: App\Entity\Product\ProductOptionValue {#8442}
      #id: 836
      #value: "No"
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  #currentLocale: "en_US"
  #currentTranslation: null
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  -enabled: true
}

View Format

"no"

Submitted Data

This form was not submitted.

Passed Options

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block_name	"entry"	same as passed value
label	"Red Line"	same as passed value
only_available_values	true	same as passed value
option	App\Entity\Product\ProductOption {#8059#id: 34 #code: "red_line" #position: 3 #values: Doctrine\ORM\PersistentCollection {#8062 …} #createdAt: DateTime @1737709966 {#8057 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #updatedAt: DateTime @1737709966 {#8058 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #translations: Doctrine\ORM\PersistentCollection {#8060 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductOptionTranslation {#8090 #locale: "en_US" #translatable: App\Entity\Product\ProductOption {#8059} #id: 52 #name: "Red Line" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US"}	same as passed value
product	App\Entity\Product\Product {#7310#id: 10370 #code: "IEEE00004256" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …} #initialized: true -snapshot: [ …4] -owner: App\Entity\Product\Product {#7310} -association: [ …21] -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …} -backRefFieldName: null -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#260654 …} -isDirty: false } #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751039020 {#7274 date: 2025-06-27 17:43:40.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#7322 date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 36489 #name: "IEEE/IEC 62530:2007" #slug: "ieee-iec-62530-2007-ieee00004256-242022" #description: """ New IEEE Standard - Superseded.<br />\n This standard provides a set of extensions to the IEEE 1364™ Verilog® hardware<br />\n description language (HDL) to aid in the creation and verification of abstract architectural level<br />\n models. It also includes design specification methods, embedded assertions language, testbench<br />\n language including coverage and an assertions application programming interface (API), and a<br />\n direct programming interface (DPI). This standard enables a productivity boost in design and<br />\n validation and covers design, simulation, validation, and formal assertion-based verification flows.<br />\n \t\t\t\t<br />\n This standard specifies extensions for a higher level of abstraction for modeling and verification with the<br />\n Verilog® hardware description language (HDL). These additions extend Verilog into the systems space and<br />\n the verification space. SystemVerilog is built on top of IEEE Std 1364™1 for the Verilog HDL. This<br />\n standard includes design specification methods, embedded assertions language, testbench language<br />\n including coverage and assertions application programming interface (API), and a direct programming<br />\n interface (DPI).<br />\n Throughout this standard, the following terms apply:<br />\n — Verilog refers to IEEE Std 1364 for the Verilog HDL.<br />\n — Verilog-2001 refers to IEEE Std 1364-2001 [B4]2 for the Verilog HDL.<br />\n — Verilog-1995 refers to IEEE Std 1364-1995 [B3] for the Verilog HDL.<br />\n — SystemVerilog refers to the extensions to the Verilog standard (IEEE Std 1364) as defined in this<br />\n standard.<br />\n SystemVerilog adds extended and new constructs to Verilog, including the following:<br />\n — Extensions to data types for better encapsulation and compactness of code and for tighter<br />\n specification<br />\n — C data types: int, typedef, struct, union, enum<br />\n — Other data types: bounded queues, logic (0, 1, X, Z) and bit (0, 1), tagged unions for safety<br />\n — Dynamic data types: string, classes, dynamic queues, dynamic arrays, associative arrays<br />\n including automatic memory management freeing users from deallocation issues<br />\n — Dynamic casting and bit-stream casting<br />\n — Automatic/static specification on a per-variable-instance basis<br />\n — Extended operators for concise description<br />\n — Wild equality and inequality<br />\n — Built-in methods to extend the language<br />\n — Operator overloading<br />\n — Streaming operators<br />\n — Set membership<br />\n — Extended procedural statements<br />\n — Pattern matching on selection statements for use with tagged unions<br />\n — Enhanced loop statements plus the foreach statement<br />\n — C-like jump statements: return, break, continue<br />\n — final blocks that execute at the end of simulation (inverse of initial)<br />\n — Extended event control and sequence events<br />\n — Enhanced process control<br />\n — Extensions to always blocks to include synthesis consistent simulation semantics<br />\n — Extensions to fork…join to model pipelines and for enhanced process control<br />\n — Fine-grain process control<br />\n — Enhanced tasks and functions<br />\n — C-like void functions<br />\n — Pass by reference<br />\n — Default arguments<br />\n — Argument binding by name<br />\n — Optional arguments<br />\n — Import/export functions for DPI<br />\n — Classes: object-oriented mechanism that provides abstraction, encapsulation, and safe pointer<br />\n capabilities<br />\n — Automated testbench support with random constraints<br />\n — Interprocess communication synchronization<br />\n — Semaphores<br />\n — Mailboxes<br />\n — Event extensions, event variables, and event sequencing<br />\n — Clarification and extension of the scheduling semantics<br />\n — Cycle-based functionality: clocking blocks and cycle-based attributes that help reduce development,<br />\n ease maintainability, and promote reusability<br />\n — Cycle-based signal drives and samples<br />\n — Synchronous samples<br />\n SystemVerilog is built on top of IEEE Std 1364. SystemVerilog improves the productivity, readability, and<br />\n reusability of Verilog-based code. The language enhancements in SystemVerilog provide more concise<br />\n hardware descriptions, while still providing an easy route with existing tools into current hardware<br />\n implementation flows. The enhancements also provide extensive support for directed and constrainedrandom<br />\n testbench development, coverage-driven verification, and assertion-based verification.<br />\n 1Information on references can be found in Clause 2.<br />\n 2The numbers in brackets correspond to the numbers in the bibliography in Annex K.<br />\n — Race-free program context<br />\n — Assertion mechanism for verifying design intent and functional coverage intent<br />\n — Property and sequence declarations<br />\n — Assertions and coverage statements with action blocks<br />\n — Extended hierarchy support<br />\n — Packages for declaration encapsulation with import for controlled access<br />\n — Compilation-unit scope nested modules and extern modules for separate compilation support<br />\n — Extension of port declarations to support interfaces, events, and variables<br />\n — $root to provide unambiguous access using hierarchical references<br />\n — Interfaces to encapsulate communication and facilitate communication-oriented design<br />\n — Functional coverage<br />\n — DPI for clean, efficient interoperation with other languages (C provided)<br />\n — Assertion API<br />\n — Coverage API<br />\n — Data read API<br />\n — Verilog procedural interface (VPI) extensions for SystemVerilog constructs<br />\n — Concurrent assertion formal semantics """ #metaKeywords: null #metaDescription: null #shortDescription: "IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1197154800 {#7318 date: 2007-12-09 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "62530" -bookCollection: "" -pageCount: 668 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …}}	same as passed value
property_path	"[red_line]"	same as passed value

Resolved Options

Option	Value
action	""
allow_extra_fields	false
allow_file_upload	false
attr	[]
attr_translation_parameters	[]
auto_initialize	true
block_name	"entry"
block_prefix	null
by_reference	true
choice_attr	null
choice_filter	null
choice_label	"value"
choice_loader	null
choice_name	null
choice_translation_domain	false
choice_translation_parameters	[]
choice_value	"code"
choices	Doctrine\Common\Collections\ArrayCollection {#113969-elements: [ 1 => App\Entity\Product\ProductOptionValue {#8442 #id: 212 #code: "no" #option: App\Entity\Product\ProductOption {#8059 #id: 34 #code: "red_line" #position: 3 #values: Doctrine\ORM\PersistentCollection {#8062 …} #createdAt: DateTime @1737709966 {#8057 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #updatedAt: DateTime @1737709966 {#8058 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #translations: Doctrine\ORM\PersistentCollection {#8060 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductOptionTranslation {#8090 #locale: "en_US" #translatable: App\Entity\Product\ProductOption {#8059} #id: 52 #name: "Red Line" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" } #translations: Doctrine\ORM\PersistentCollection {#8423 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductOptionValueTranslation {#8483 #locale: "en_US" #translatable: App\Entity\Product\ProductOptionValue {#8442} #id: 836 #value: "No" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" -enabled: true } ]}
compound	false
constraints	[]
csrf_field_name	"_token"
csrf_message	"The CSRF token is invalid. Please try to resubmit the form."
csrf_protection	true
csrf_token_id	null
csrf_token_manager	Symfony\Component\Security\Csrf\CsrfTokenManager {#113483`-generator: Symfony\Component\Security\Csrf\TokenGenerator\UriSafeTokenGenerator {#113484 …} -storage: Symfony\Component\Security\Csrf\TokenStorage\SessionTokenStorage {#113485 …} -namespace: Closure() {#113487 …}`}
data_class	null
disabled	false
duplicate_preferred_choices	true
empty_data	""
error_bubbling	false
error_mapping	[]
expanded	false
extra_fields_message	"This form should not contain extra fields."
form_attr	false
getter	null
group_by	null
help	null
help_attr	[]
help_html	false
help_translation_parameters	[]
inherit_data	false
invalid_message	"The selected choice is invalid."
invalid_message_parameters	[]
is_empty_callback	null
label	"Red Line"
label_attr	[]
label_format	null
label_html	false
label_translation_parameters	[]
mapped	true
method	"POST"
multiple	false
only_available_values	true
option	App\Entity\Product\ProductOption {#8059#id: 34 #code: "red_line" #position: 3 #values: Doctrine\ORM\PersistentCollection {#8062 …} #createdAt: DateTime @1737709966 {#8057 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #updatedAt: DateTime @1737709966 {#8058 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #translations: Doctrine\ORM\PersistentCollection {#8060 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductOptionTranslation {#8090 #locale: "en_US" #translatable: App\Entity\Product\ProductOption {#8059} #id: 52 #name: "Red Line" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US"}
placeholder	null
placeholder_attr	[]
post_max_size_message	"The uploaded file was too large. Please try to upload a smaller file."
preferred_choices	[]
priority	0
product	App\Entity\Product\Product {#7310#id: 10370 #code: "IEEE00004256" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …} #initialized: true -snapshot: [ …4] -owner: App\Entity\Product\Product {#7310} -association: [ …21] -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …} -backRefFieldName: null -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#260654 …} -isDirty: false } #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751039020 {#7274 date: 2025-06-27 17:43:40.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#7322 date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 36489 #name: "IEEE/IEC 62530:2007" #slug: "ieee-iec-62530-2007-ieee00004256-242022" #description: """ New IEEE Standard - Superseded.<br />\n This standard provides a set of extensions to the IEEE 1364™ Verilog® hardware<br />\n description language (HDL) to aid in the creation and verification of abstract architectural level<br />\n models. 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This<br />\n standard includes design specification methods, embedded assertions language, testbench language<br />\n including coverage and assertions application programming interface (API), and a direct programming<br />\n interface (DPI).<br />\n Throughout this standard, the following terms apply:<br />\n — Verilog refers to IEEE Std 1364 for the Verilog HDL.<br />\n — Verilog-2001 refers to IEEE Std 1364-2001 [B4]2 for the Verilog HDL.<br />\n — Verilog-1995 refers to IEEE Std 1364-1995 [B3] for the Verilog HDL.<br />\n — SystemVerilog refers to the extensions to the Verilog standard (IEEE Std 1364) as defined in this<br />\n standard.<br />\n SystemVerilog adds extended and new constructs to Verilog, including the following:<br />\n — Extensions to data types for better encapsulation and compactness of code and for tighter<br />\n specification<br />\n — C data types: int, typedef, struct, union, enum<br />\n — Other data types: bounded queues, logic (0, 1, X, Z) and bit (0, 1), tagged unions for safety<br />\n — Dynamic data types: string, classes, dynamic queues, dynamic arrays, associative arrays<br />\n including automatic memory management freeing users from deallocation issues<br />\n — Dynamic casting and bit-stream casting<br />\n — Automatic/static specification on a per-variable-instance basis<br />\n — Extended operators for concise description<br />\n — Wild equality and inequality<br />\n — Built-in methods to extend the language<br />\n — Operator overloading<br />\n — Streaming operators<br />\n — Set membership<br />\n — Extended procedural statements<br />\n — Pattern matching on selection statements for use with tagged unions<br />\n — Enhanced loop statements plus the foreach statement<br />\n — C-like jump statements: return, break, continue<br />\n — final blocks that execute at the end of simulation (inverse of initial)<br />\n — Extended event control and sequence events<br />\n — Enhanced process control<br />\n — Extensions to always blocks to include synthesis consistent simulation semantics<br />\n — Extensions to fork…join to model pipelines and for enhanced process control<br />\n — Fine-grain process control<br />\n — Enhanced tasks and functions<br />\n — C-like void functions<br />\n — Pass by reference<br />\n — Default arguments<br />\n — Argument binding by name<br />\n — Optional arguments<br />\n — Import/export functions for DPI<br />\n — Classes: object-oriented mechanism that provides abstraction, encapsulation, and safe pointer<br />\n capabilities<br />\n — Automated testbench support with random constraints<br />\n — Interprocess communication synchronization<br />\n — Semaphores<br />\n — Mailboxes<br />\n — Event extensions, event variables, and event sequencing<br />\n — Clarification and extension of the scheduling semantics<br />\n — Cycle-based functionality: clocking blocks and cycle-based attributes that help reduce development,<br />\n ease maintainability, and promote reusability<br />\n — Cycle-based signal drives and samples<br />\n — Synchronous samples<br />\n SystemVerilog is built on top of IEEE Std 1364. SystemVerilog improves the productivity, readability, and<br />\n reusability of Verilog-based code. The language enhancements in SystemVerilog provide more concise<br />\n hardware descriptions, while still providing an easy route with existing tools into current hardware<br />\n implementation flows. The enhancements also provide extensive support for directed and constrainedrandom<br />\n testbench development, coverage-driven verification, and assertion-based verification.<br />\n 1Information on references can be found in Clause 2.<br />\n 2The numbers in brackets correspond to the numbers in the bibliography in Annex K.<br />\n — Race-free program context<br />\n — Assertion mechanism for verifying design intent and functional coverage intent<br />\n — Property and sequence declarations<br />\n — Assertions and coverage statements with action blocks<br />\n — Extended hierarchy support<br />\n — Packages for declaration encapsulation with import for controlled access<br />\n — Compilation-unit scope nested modules and extern modules for separate compilation support<br />\n — Extension of port declarations to support interfaces, events, and variables<br />\n — $root to provide unambiguous access using hierarchical references<br />\n — Interfaces to encapsulate communication and facilitate communication-oriented design<br />\n — Functional coverage<br />\n — DPI for clean, efficient interoperation with other languages (C provided)<br />\n — Assertion API<br />\n — Coverage API<br />\n — Data read API<br />\n — Verilog procedural interface (VPI) extensions for SystemVerilog constructs<br />\n — Concurrent assertion formal semantics """ #metaKeywords: null #metaDescription: null #shortDescription: "IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @1197154800 {#7318 date: 2007-12-09 00:00:00.0 Europe/Paris (+01:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "62530" -bookCollection: "" -pageCount: 668 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …}}
property_path	"[red_line]"
required	true
row_attr	[]
setter	null
translation_domain	null
trim	false
upload_max_size_message	Closure() {#113982`class: "Symfony\Component\Form\Extension\Validator\Type\UploadValidatorExtension" use: { $translator: Symfony\Component\Translation\DataCollectorTranslator {#2251 …} $message: Closure() {#113980 …} $translationDomain: "validators" }`}
validation_groups	null

View Vars

Variable	Value
action	""
attr	[]
attr_translation_parameters	[]
block_prefixes	[`"form" "choice" "sylius_product_option_value_choice" "_sylius_add_to_cart_cartItem_variant_entry"`]
cache_key	"_sylius_add_to_cart_cartItem_variant_entry_sylius_product_option_value_choice"
choice_translation_domain	false
choice_translation_parameters	[]
choices	[Symfony\Component\Form\ChoiceList\View\ChoiceView {#114050 +label: "No" +value: "no" +data: App\Entity\Product\ProductOptionValue {#8442 #id: 212 #code: "no" #option: App\Entity\Product\ProductOption {#8059 #id: 34 #code: "red_line" #position: 3 #values: Doctrine\ORM\PersistentCollection {#8062 …} #createdAt: DateTime @1737709966 {#8057 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #updatedAt: DateTime @1737709966 {#8058 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #translations: Doctrine\ORM\PersistentCollection {#8060 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductOptionTranslation {#8090 #locale: "en_US" #translatable: App\Entity\Product\ProductOption {#8059} #id: 52 #name: "Red Line" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" } #translations: Doctrine\ORM\PersistentCollection {#8423 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductOptionValueTranslation {#8483 #locale: "en_US" #translatable: App\Entity\Product\ProductOptionValue {#8442} #id: 836 #value: "No" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" -enabled: true } +attr: [] +labelTranslationParameters: [] }]
compound	false
data	App\Entity\Product\ProductOptionValue {#8442#id: 212 #code: "no" #option: App\Entity\Product\ProductOption {#8059 #id: 34 #code: "red_line" #position: 3 #values: Doctrine\ORM\PersistentCollection {#8062 …} #createdAt: DateTime @1737709966 {#8057 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #updatedAt: DateTime @1737709966 {#8058 date: 2025-01-24 10:12:46.0 Europe/Paris (+01:00) } #translations: Doctrine\ORM\PersistentCollection {#8060 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductOptionTranslation {#8090 #locale: "en_US" #translatable: App\Entity\Product\ProductOption {#8059} #id: 52 #name: "Red Line" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" } #translations: Doctrine\ORM\PersistentCollection {#8423 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductOptionValueTranslation {#8483 #locale: "en_US" #translatable: App\Entity\Product\ProductOptionValue {#8442} #id: 836 #value: "No" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" -enabled: true}
disabled	false
duplicate_preferred_choices	true
errors	Symfony\Component\Form\FormErrorIterator {#114047`-form: Symfony\Component\Form\Form {#113991 …} -errors: []`}
expanded	false
form	Symfony\Component\Form\FormView {#114044 …5}
full_name	"sylius_add_to_cart[cartItem][variant][red_line]"
help	null
help_attr	[]
help_html	false
help_translation_parameters	[]
id	"sylius_add_to_cart_cartItem_variant_red_line"
is_selected	Closure($choice, $value) {#114049`class: "Symfony\Component\Form\Extension\Core\Type\ChoiceType"`}
label	"Red Line"
label_attr	[]
label_format	null
label_html	false
label_translation_parameters	[]
method	"POST"
multipart	false
multiple	false
name	"red_line"
placeholder	null
placeholder_attr	[]
placeholder_in_choices	false
preferred_choices	[]
priority	0
required	true
row_attr	[]
separator	"-------------------"
submitted	false
translation_domain	null
unique_block_prefix	"_sylius_add_to_cart_cartItem_variant_entry"
valid	true
value	"no"

_token

Form type:

"Symfony\Component\Form\Extension\Core\Type\HiddenType"

Errors

This form has no errors.

Default Data

Property	Value
Model Format	same as normalized format
Normalized Format	"b75f71a14ec9a9df45b698777.-N90JyE-oA0hhZJRVmYMO9ZksSHNeUwZX9UilbBT610.jLtGFRlVyTx-yv5lNxVLCqUy3E-KNCpoCplQ9-IQnBuOmhZ1eA3nWxfz3w"
View Format	same as normalized format

Submitted Data

This form was not submitted.

Passed Options

Option	Passed Value	Resolved Value
block_prefix	"csrf_token"	same as passed value
data	"b75f71a14ec9a9df45b698777.-N90JyE-oA0hhZJRVmYMO9ZksSHNeUwZX9UilbBT610.jLtGFRlVyTx-yv5lNxVLCqUy3E-KNCpoCplQ9-IQnBuOmhZ1eA3nWxfz3w"	same as passed value
mapped	false	same as passed value

Resolved Options

Option	Value
action	""
allow_extra_fields	false
allow_file_upload	false
attr	[]
attr_translation_parameters	[]
auto_initialize	true
block_name	null
block_prefix	"csrf_token"
by_reference	true
compound	false
constraints	[]
csrf_field_name	"_token"
csrf_message	"The CSRF token is invalid. Please try to resubmit the form."
csrf_protection	true
csrf_token_id	null
csrf_token_manager	Symfony\Component\Security\Csrf\CsrfTokenManager {#113483`-generator: Symfony\Component\Security\Csrf\TokenGenerator\UriSafeTokenGenerator {#113484 …} -storage: Symfony\Component\Security\Csrf\TokenStorage\SessionTokenStorage {#113485 …} -namespace: Closure() {#113487 …}`}
data	"b75f71a14ec9a9df45b698777.-N90JyE-oA0hhZJRVmYMO9ZksSHNeUwZX9UilbBT610.jLtGFRlVyTx-yv5lNxVLCqUy3E-KNCpoCplQ9-IQnBuOmhZ1eA3nWxfz3w"
data_class	null
disabled	false
empty_data	Closure(FormInterface $form) {#113612`class: "Symfony\Component\Form\Extension\Core\Type\FormType"`}
error_bubbling	true
error_mapping	[]
extra_fields_message	"This form should not contain extra fields."
form_attr	false
getter	null
help	null
help_attr	[]
help_html	false
help_translation_parameters	[]
inherit_data	false
invalid_message	"The hidden field is invalid."
invalid_message_parameters	[]
is_empty_callback	null
label	null
label_attr	[]
label_format	null
label_html	false
label_translation_parameters	[]
mapped	false
method	"POST"
post_max_size_message	"The uploaded file was too large. Please try to upload a smaller file."
priority	0
property_path	null
required	false
row_attr	[]
setter	null
translation_domain	null
trim	true
upload_max_size_message	Closure() {#114051`class: "Symfony\Component\Form\Extension\Validator\Type\UploadValidatorExtension" use: { $translator: Symfony\Component\Translation\DataCollectorTranslator {#2251 …} $message: Closure() {#114015 …} $translationDomain: "validators" }`}
validation_groups	null

View Vars

Variable	Value
action	""
attr	[]
attr_translation_parameters	[]
block_prefixes	[`"form" "hidden" "csrf_token" "_sylius_add_to_cart__token"`]
cache_key	"_sylius_add_to_cart__token_hidden"
compound	false
data	"b75f71a14ec9a9df45b698777.-N90JyE-oA0hhZJRVmYMO9ZksSHNeUwZX9UilbBT610.jLtGFRlVyTx-yv5lNxVLCqUy3E-KNCpoCplQ9-IQnBuOmhZ1eA3nWxfz3w"
disabled	false
errors	Symfony\Component\Form\FormErrorIterator {#114061`-form: Symfony\Component\Form\Form {#114057 …} -errors: []`}
form	Symfony\Component\Form\FormView {#114052 …5}
full_name	"sylius_add_to_cart[_token]"
help	null
help_attr	[]
help_html	false
help_translation_parameters	[]
id	"sylius_add_to_cart__token"
label	null
label_attr	[]
label_format	null
label_html	false
label_translation_parameters	[]
method	"POST"
multipart	false
name	"_token"
priority	0
required	false
row_attr	[]
submitted	false
translation_domain	null
unique_block_prefix	"_sylius_add_to_cart__token"
valid	true
value	"b75f71a14ec9a9df45b698777.-N90JyE-oA0hhZJRVmYMO9ZksSHNeUwZX9UilbBT610.jLtGFRlVyTx-yv5lNxVLCqUy3E-KNCpoCplQ9-IQnBuOmhZ1eA3nWxfz3w"

Symfony Profiler

GET https://dev.normadoc.fr/products/ieee-iec-62530-2007-ieee00004256-242022

Configuration Settings

Theme

Page Width

Forms

sylius_add_to_cart

Errors

Default Data

Submitted Data

Passed Options

Resolved Options

View Vars

cartItem

Errors

Default Data

Submitted Data

Passed Options

Resolved Options

View Vars

quantity

Errors

Default Data

Submitted Data

Passed Options

Resolved Options

View Vars

variant

Errors

Default Data

Submitted Data

Passed Options

Resolved Options

View Vars

format

Errors

Default Data

Submitted Data

Passed Options

Resolved Options

View Vars

languages

Errors

Default Data

Submitted Data

Passed Options

Resolved Options

View Vars

multi_user

Errors

Default Data

Submitted Data

Passed Options

Resolved Options

View Vars

red_line

Errors

Default Data

Submitted Data

Passed Options

Resolved Options

View Vars

_token

Errors

Default Data

Submitted Data

Passed Options

Resolved Options

View Vars