GET https://dev.normadoc.fr/_partial/cart/add-item?productId=9382&template=%40SyliusShop%2FProduct%2FShow%2F_addToCart.html.twig

Response
200 OK
IP
216.73.217.47
Profiled on
Token
0e1715

Forms

  • sylius_add_to_cart
    • cartItem
    • _token

sylius_add_to_cart

Form type: 
"Sylius\Bundle\CoreBundle\Form\Type\Order\AddToCartType"

Errors

This form has no errors.

Default Data

Property Value
Model Format same as normalized format
Normalized Format 
Sylius\Bundle\OrderBundle\Controller\AddToCartCommand {#113630
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  -cartItem: App\Entity\Order\OrderItem {#113618
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    #order: null
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    #version: 1
    #variant: App\Entity\Product\ProductVariant {#8099
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      #code: "IEEE00002200PDF"
      #product: App\Entity\Product\Product {#7310
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        #code: "IEEE00002200"
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        #variants: Doctrine\ORM\PersistentCollection {#7743 …}
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        #enabled: true
        #translations: Doctrine\ORM\PersistentCollection {#7921 …}
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            #translatable: App\Entity\Product\Product {#7310}
            #id: 32537
            #name: "IEEE 1481:1999"
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            #description: """
              New IEEE Standard - Superseded.<br />\n
              Ways for integrated circuit designers to analyze chip timing and power consistently across a broad set of electric design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, this standard covers means by which EDA vendors can meet their application performance and capacity needs.<br />\n
              \t\t\t\t<br />\n
              The scope of the DPCS standard is to make it possible for integrated circuit designers to analyze chip timing and power consistently across a broad set of EDA applications, for integrated circuit vendors to express timing and power information once (for a given technology), and for EDA vendors to meet their application performance and capacity needs. The intended use for this standard is IC timing and power. This standard may be applied to both unit logic cells supplied by the IC vendor and logical macros defined by the IC designer. Although this standard is written toward the integrated circuit supplier and EDA developer, its application applies equally well to representation of timing and power for designer-defined macros (or hierarchical design elements).<br />\n
              As feature sizes for chips shrink below 0.5<br />\n
              µ<br />\n
              m, interconnect delay effects outweigh those of the logic cells.<br />\n
              This means placement of cells and wire routing of the interconnects become as important a factor as the type<br />\n
              of cell drivers and receivers on the interconnect. As a result, EDA logic design applications (such as<br />\n
              synthesis) now need to interact closely with physical design applications (such as floorplanning and layout).<br />\n
              Applications that before could consider only simple delay and power models now need to deal with complex delay and power equations. The designer now needs EDA applications that can be directed to specific timing constraints, and provide consistent and accurate characterization of a chip’s timing and power before it is manufactured. Plus, due to the complexities of the delay and power equations, the integrated circuit vendor needs to have control of application calculations and not be restricted by unique characteristics of the broad set of applications demanded by the customers (or designers).
              """
            #metaKeywords: null
            #metaDescription: null
            #shortDescription: "IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System"
            -notes: "Superseded"
          }
        ]
        #currentLocale: "en_US"
        #currentTranslation: null
        #fallbackLocale: "en_US"
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        #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
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        #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
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        #images: Doctrine\ORM\PersistentCollection {#7644 …}
        -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
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        -lastUpdatedAt: DateTime @1578006000 {#7292
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        -author: ""
        -publishedAt: DateTime @958082400 {#7318
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      }
      #updatedAt: DateTime @1755611970 {#8116
        date: 2025-08-19 15:59:30.0 Europe/Paris (+02:00)
      }
      #enabled: true
      #translations: Doctrine\ORM\PersistentCollection {#8259 …}
      #translationsCache: [
        "en_US" => App\Entity\Product\ProductVariantTranslation {#93321
          #locale: "en_US"
          #translatable: App\Entity\Product\ProductVariant {#8099}
          #id: 3293
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      #taxCategory: Proxies\__CG__\App\Entity\Taxation\TaxCategory {#8131 …}
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      #shippingRequired: true
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      -apiLastModifiedAt: DateTime @1753740000 {#8098
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View Format same as normalized format

Submitted Data

This form was not submitted.

Passed Options

Option Passed Value Resolved Value
data 
Sylius\Bundle\OrderBundle\Controller\AddToCartCommand {#113630
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  -cartItem: App\Entity\Order\OrderItem {#113618
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    #order: null
    #quantity: 1
    #unitPrice: 0
    #originalUnitPrice: 0
    #total: 0
    #immutable: false
    #units: Doctrine\Common\Collections\ArrayCollection {#113642 …}
    #unitsTotal: 0
    #adjustments: Doctrine\Common\Collections\ArrayCollection {#113643 …}
    #adjustmentsTotal: 0
    #version: 1
    #variant: App\Entity\Product\ProductVariant {#8099
      #id: 3275
      #code: "IEEE00002200PDF"
      #product: App\Entity\Product\Product {#7310
        #id: 9382
        #code: "IEEE00002200"
        #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
        #variants: Doctrine\ORM\PersistentCollection {#7743 …}
        #options: Doctrine\ORM\PersistentCollection {#7915
          #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …}
          #initialized: true
          -snapshot: [ …4]
          -owner: App\Entity\Product\Product {#7310}
          -association: [ …21]
          -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …}
          -backRefFieldName: null
          -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#198975 …}
          -isDirty: false
        }
        #associations: Doctrine\ORM\PersistentCollection {#7899 …}
        #createdAt: DateTime @1751038218 {#7274
          date: 2025-06-27 17:30:18.0 Europe/Paris (+02:00)
        }
        #updatedAt: DateTime @1753969444 {#7322
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        }
        #enabled: true
        #translations: Doctrine\ORM\PersistentCollection {#7921 …}
        #translationsCache: [
          "en_US" => App\Entity\Product\ProductTranslation {#7920
            #locale: "en_US"
            #translatable: App\Entity\Product\Product {#7310}
            #id: 32537
            #name: "IEEE 1481:1999"
            #slug: "ieee-1481-1999-ieee00002200-241034"
            #description: """
              New IEEE Standard - Superseded.<br />\n
              Ways for integrated circuit designers to analyze chip timing and power consistently across a broad set of electric design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, this standard covers means by which EDA vendors can meet their application performance and capacity needs.<br />\n
              \t\t\t\t<br />\n
              The scope of the DPCS standard is to make it possible for integrated circuit designers to analyze chip timing and power consistently across a broad set of EDA applications, for integrated circuit vendors to express timing and power information once (for a given technology), and for EDA vendors to meet their application performance and capacity needs. The intended use for this standard is IC timing and power. This standard may be applied to both unit logic cells supplied by the IC vendor and logical macros defined by the IC designer. Although this standard is written toward the integrated circuit supplier and EDA developer, its application applies equally well to representation of timing and power for designer-defined macros (or hierarchical design elements).<br />\n
              As feature sizes for chips shrink below 0.5<br />\n
              µ<br />\n
              m, interconnect delay effects outweigh those of the logic cells.<br />\n
              This means placement of cells and wire routing of the interconnects become as important a factor as the type<br />\n
              of cell drivers and receivers on the interconnect. As a result, EDA logic design applications (such as<br />\n
              synthesis) now need to interact closely with physical design applications (such as floorplanning and layout).<br />\n
              Applications that before could consider only simple delay and power models now need to deal with complex delay and power equations. The designer now needs EDA applications that can be directed to specific timing constraints, and provide consistent and accurate characterization of a chip’s timing and power before it is manufactured. Plus, due to the complexities of the delay and power equations, the integrated circuit vendor needs to have control of application calculations and not be restricted by unique characteristics of the broad set of applications demanded by the customers (or designers).
              """
            #metaKeywords: null
            #metaDescription: null
            #shortDescription: "IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System"
            -notes: "Superseded"
          }
        ]
        #currentLocale: "en_US"
        #currentTranslation: null
        #fallbackLocale: "en_US"
        #variantSelectionMethod: "match"
        #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
        #channels: Doctrine\ORM\PersistentCollection {#7627 …}
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        #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
        #averageRating: 0.0
        #images: Doctrine\ORM\PersistentCollection {#7644 …}
        -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
        -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
        -apiLastModifiedAt: DateTime @1743289200 {#7317
          date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
        }
        -lastUpdatedAt: DateTime @1578006000 {#7292
          date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
        }
        -author: ""
        -publishedAt: DateTime @958082400 {#7318
          date: 2000-05-12 00:00:00.0 Europe/Paris (+02:00)
        }
        -releasedAt: null
        -confirmedAt: null
        -canceledAt: null
        -edition: null
        -coreDocument: "1481"
        -bookCollection: ""
        -pageCount: 400
        -documents: Doctrine\ORM\PersistentCollection {#7464 …}
        -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
      }
      #optionValues: Doctrine\ORM\PersistentCollection {#8315 …}
      #position: 0
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      }
      #updatedAt: DateTime @1755611970 {#8116
        date: 2025-08-19 15:59:30.0 Europe/Paris (+02:00)
      }
      #enabled: true
      #translations: Doctrine\ORM\PersistentCollection {#8259 …}
      #translationsCache: [
        "en_US" => App\Entity\Product\ProductVariantTranslation {#93321
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          #translatable: App\Entity\Product\ProductVariant {#8099}
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      #taxCategory: Proxies\__CG__\App\Entity\Taxation\TaxCategory {#8131 …}
      #shippingCategory: null
      #channelPricings: Doctrine\ORM\PersistentCollection {#8293 …}
      #shippingRequired: true
      #images: Doctrine\ORM\PersistentCollection {#8290 …}
      -apiLastModifiedAt: DateTime @1753740000 {#8098
        date: 2025-07-29 00:00:00.0 Europe/Paris (+02:00)
      }
      -publishedAt: null
      -isbn: "978-0-7381-1772-0"
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      -physicalProduct: false
      -downloadableImmediately: true
      -downloadable: true
      -drmViewerUrl: "https://online-viewer.normadoc.com/8PP7rD"
      -sellable: true
      -documents: Doctrine\ORM\PersistentCollection {#8127 …}
      -drmTokens: Doctrine\ORM\PersistentCollection {#8119 …}
      -enabledForSubscribers: true
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    #productName: null
    #variantName: null
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}
 same as passed value
product 
App\Entity\Product\Product {#7310
  #id: 9382
  #code: "IEEE00002200"
  #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
  #variants: Doctrine\ORM\PersistentCollection {#7743 …}
  #options: Doctrine\ORM\PersistentCollection {#7915
    #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …}
    #initialized: true
    -snapshot: [ …4]
    -owner: App\Entity\Product\Product {#7310}
    -association: [ …21]
    -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …}
    -backRefFieldName: null
    -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#198975 …}
    -isDirty: false
  }
  #associations: Doctrine\ORM\PersistentCollection {#7899 …}
  #createdAt: DateTime @1751038218 {#7274
    date: 2025-06-27 17:30:18.0 Europe/Paris (+02:00)
  }
  #updatedAt: DateTime @1753969444 {#7322
    date: 2025-07-31 15:44:04.0 Europe/Paris (+02:00)
  }
  #enabled: true
  #translations: Doctrine\ORM\PersistentCollection {#7921 …}
  #translationsCache: [
    "en_US" => App\Entity\Product\ProductTranslation {#7920
      #locale: "en_US"
      #translatable: App\Entity\Product\Product {#7310}
      #id: 32537
      #name: "IEEE 1481:1999"
      #slug: "ieee-1481-1999-ieee00002200-241034"
      #description: """
        New IEEE Standard - Superseded.<br />\n
        Ways for integrated circuit designers to analyze chip timing and power consistently across a broad set of electric design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, this standard covers means by which EDA vendors can meet their application performance and capacity needs.<br />\n
        \t\t\t\t<br />\n
        The scope of the DPCS standard is to make it possible for integrated circuit designers to analyze chip timing and power consistently across a broad set of EDA applications, for integrated circuit vendors to express timing and power information once (for a given technology), and for EDA vendors to meet their application performance and capacity needs. The intended use for this standard is IC timing and power. This standard may be applied to both unit logic cells supplied by the IC vendor and logical macros defined by the IC designer. Although this standard is written toward the integrated circuit supplier and EDA developer, its application applies equally well to representation of timing and power for designer-defined macros (or hierarchical design elements).<br />\n
        As feature sizes for chips shrink below 0.5<br />\n
        µ<br />\n
        m, interconnect delay effects outweigh those of the logic cells.<br />\n
        This means placement of cells and wire routing of the interconnects become as important a factor as the type<br />\n
        of cell drivers and receivers on the interconnect. As a result, EDA logic design applications (such as<br />\n
        synthesis) now need to interact closely with physical design applications (such as floorplanning and layout).<br />\n
        Applications that before could consider only simple delay and power models now need to deal with complex delay and power equations. The designer now needs EDA applications that can be directed to specific timing constraints, and provide consistent and accurate characterization of a chip’s timing and power before it is manufactured. Plus, due to the complexities of the delay and power equations, the integrated circuit vendor needs to have control of application calculations and not be restricted by unique characteristics of the broad set of applications demanded by the customers (or designers).
        """
      #metaKeywords: null
      #metaDescription: null
      #shortDescription: "IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System"
      -notes: "Superseded"
    }
  ]
  #currentLocale: "en_US"
  #currentTranslation: null
  #fallbackLocale: "en_US"
  #variantSelectionMethod: "match"
  #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
  #channels: Doctrine\ORM\PersistentCollection {#7627 …}
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  #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
  #averageRating: 0.0
  #images: Doctrine\ORM\PersistentCollection {#7644 …}
  -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
  -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
  -apiLastModifiedAt: DateTime @1743289200 {#7317
    date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
  }
  -lastUpdatedAt: DateTime @1578006000 {#7292
    date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
  }
  -author: ""
  -publishedAt: DateTime @958082400 {#7318
    date: 2000-05-12 00:00:00.0 Europe/Paris (+02:00)
  }
  -releasedAt: null
  -confirmedAt: null
  -canceledAt: null
  -edition: null
  -coreDocument: "1481"
  -bookCollection: ""
  -pageCount: 400
  -documents: Doctrine\ORM\PersistentCollection {#7464 …}
  -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
}
 same as passed value

Resolved Options

Option Value
action 
""
allow_extra_fields 
false
allow_file_upload 
false
attr 
[]
attr_translation_parameters 
[]
auto_initialize 
true
block_name 
null
block_prefix 
null
by_reference 
true
compound 
true
constraints 
[]
csrf_field_name 
"_token"
csrf_message 
"The CSRF token is invalid. Please try to resubmit the form."
csrf_protection 
true
csrf_token_id 
null
csrf_token_manager 
Symfony\Component\Security\Csrf\CsrfTokenManager {#113650
  -generator: Symfony\Component\Security\Csrf\TokenGenerator\UriSafeTokenGenerator {#113651 …}
  -storage: Symfony\Component\Security\Csrf\TokenStorage\SessionTokenStorage {#113652 …}
  -namespace: Closure() {#113654 …}
}
data 
Sylius\Bundle\OrderBundle\Controller\AddToCartCommand {#113630
  -cart: App\Entity\Order\Order {#13330 …}
  -cartItem: App\Entity\Order\OrderItem {#113618
    #id: null
    #order: null
    #quantity: 1
    #unitPrice: 0
    #originalUnitPrice: 0
    #total: 0
    #immutable: false
    #units: Doctrine\Common\Collections\ArrayCollection {#113642 …}
    #unitsTotal: 0
    #adjustments: Doctrine\Common\Collections\ArrayCollection {#113643 …}
    #adjustmentsTotal: 0
    #version: 1
    #variant: App\Entity\Product\ProductVariant {#8099
      #id: 3275
      #code: "IEEE00002200PDF"
      #product: App\Entity\Product\Product {#7310
        #id: 9382
        #code: "IEEE00002200"
        #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
        #variants: Doctrine\ORM\PersistentCollection {#7743 …}
        #options: Doctrine\ORM\PersistentCollection {#7915
          #collection: Doctrine\Common\Collections\ArrayCollection {#7917 …}
          #initialized: true
          -snapshot: [ …4]
          -owner: App\Entity\Product\Product {#7310}
          -association: [ …21]
          -em: ContainerHAOxQ06\EntityManagerGhostEbeb667 {#775 …}
          -backRefFieldName: null
          -typeClass: Symfony\Component\VarDumper\Caster\CutStub {#198975 …}
          -isDirty: false
        }
        #associations: Doctrine\ORM\PersistentCollection {#7899 …}
        #createdAt: DateTime @1751038218 {#7274
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        }
        #updatedAt: DateTime @1753969444 {#7322
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        }
        #enabled: true
        #translations: Doctrine\ORM\PersistentCollection {#7921 …}
        #translationsCache: [
          "en_US" => App\Entity\Product\ProductTranslation {#7920
            #locale: "en_US"
            #translatable: App\Entity\Product\Product {#7310}
            #id: 32537
            #name: "IEEE 1481:1999"
            #slug: "ieee-1481-1999-ieee00002200-241034"
            #description: """
              New IEEE Standard - Superseded.<br />\n
              Ways for integrated circuit designers to analyze chip timing and power consistently across a broad set of electric design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, this standard covers means by which EDA vendors can meet their application performance and capacity needs.<br />\n
              \t\t\t\t<br />\n
              The scope of the DPCS standard is to make it possible for integrated circuit designers to analyze chip timing and power consistently across a broad set of EDA applications, for integrated circuit vendors to express timing and power information once (for a given technology), and for EDA vendors to meet their application performance and capacity needs. The intended use for this standard is IC timing and power. This standard may be applied to both unit logic cells supplied by the IC vendor and logical macros defined by the IC designer. Although this standard is written toward the integrated circuit supplier and EDA developer, its application applies equally well to representation of timing and power for designer-defined macros (or hierarchical design elements).<br />\n
              As feature sizes for chips shrink below 0.5<br />\n
              µ<br />\n
              m, interconnect delay effects outweigh those of the logic cells.<br />\n
              This means placement of cells and wire routing of the interconnects become as important a factor as the type<br />\n
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              synthesis) now need to interact closely with physical design applications (such as floorplanning and layout).<br />\n
              Applications that before could consider only simple delay and power models now need to deal with complex delay and power equations. The designer now needs EDA applications that can be directed to specific timing constraints, and provide consistent and accurate characterization of a chip’s timing and power before it is manufactured. Plus, due to the complexities of the delay and power equations, the integrated circuit vendor needs to have control of application calculations and not be restricted by unique characteristics of the broad set of applications demanded by the customers (or designers).
              """
            #metaKeywords: null
            #metaDescription: null
            #shortDescription: "IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System"
            -notes: "Superseded"
          }
        ]
        #currentLocale: "en_US"
        #currentTranslation: null
        #fallbackLocale: "en_US"
        #variantSelectionMethod: "match"
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