GET https://dev.normadoc.fr/products/ieee-1364-2005-ieee00003641-241755

Response
200 OK
IP
216.73.216.245
Profiled on
Token
0aaac6

Components

3 Twig Components
11 Render Count
5 ms Render Time
298.0 MiB Memory Usage

Components

Name Metadata Render Count Render Time
ProductState 
"App\Twig\Components\ProductState"
components/ProductState.html.twig 		5 1.05ms
ProductMostRecent 
"App\Twig\Components\ProductMostRecent"
components/ProductMostRecent.html.twig 		5 3.57ms
ProductType 
"App\Twig\Components\ProductType"
components/ProductType.html.twig 		1 0.26ms

Render calls

ProductState App\Twig\Components\ProductState 298.0 MiB 0.41 ms
Input props 
[
  "product" => App\Entity\Product\Product {#7310
    #id: 10103
    #code: "IEEE00003641"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751038817 {#7274
      date: 2025-06-27 17:40:17.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#7322
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 35421
        #name: "IEEE 1364:2005"
        #slug: "ieee-1364-2005-ieee00003641-241755"
        #description: """
          Revision Standard - Superseded.<br />\n
          The Verilog hardware description language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementers of tools supporting the language and advanced users of the language.<br />\n
          (Supersedes IEEE Std 1364-2001. Superseded by IEEE Std 1800-2009).<br />\n
          \t\t\t\t<br />\n
          Verilog is a hardware description language (HDL) that was standardized as IEEE Std 1364™-1995 and first revised as IEEE Std 1364-2001. This revision corrects and clarifies features ambiguously described in the 1995 and 2001 editions. It also resolves incompatibilities and inconsistencies of IEEE 1364-2001 with IEEE Std 1800™-2005.<br />\n
          The intent of this standard is to serve as a complete specification of the Verilog HDL. This standard contains the following:<br />\n
          — The formal syntax and semantics of all Verilog HDL constructs<br />\n
          — The formal syntax and semantics of standard delay format (SDF) constructs<br />\n
          — Simulation system tasks and functions, such as text output display commands<br />\n
          — Compiler directives, such as text substitution macros and simulation time scaling<br />\n
          — The programming language interface (PLI) binding mechanism<br />\n
          — The formal syntax and semantics of the Verilog procedural interface (VPI)<br />\n
          — Informative usage examples<br />\n
          — Informative delay model for SDF<br />\n
          — The VPI header file<br />\n
          The purpose of the original document, IEEE Std 1364-2001, was to provide an industry standard based on the Verilog Hardware Description Language. The reason for the document's revision is to incorporate corrections that have been identified by the working group since 1364-1995 and 1364-2001 were published by the IEEE.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Verilog Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1616454000 {#7292
      date: 2021-03-23 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1144360800 {#7318
      date: 2006-04-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 590
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  "showFullLabel" => "true"
]
Attributes 
[
  "showFullLabel" => "true"
]
Component 
App\Twig\Components\ProductState {#93007
  +product: App\Entity\Product\Product {#7310
    #id: 10103
    #code: "IEEE00003641"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751038817 {#7274
      date: 2025-06-27 17:40:17.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#7322
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 35421
        #name: "IEEE 1364:2005"
        #slug: "ieee-1364-2005-ieee00003641-241755"
        #description: """
          Revision Standard - Superseded.<br />\n
          The Verilog hardware description language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementers of tools supporting the language and advanced users of the language.<br />\n
          (Supersedes IEEE Std 1364-2001. Superseded by IEEE Std 1800-2009).<br />\n
          \t\t\t\t<br />\n
          Verilog is a hardware description language (HDL) that was standardized as IEEE Std 1364™-1995 and first revised as IEEE Std 1364-2001. This revision corrects and clarifies features ambiguously described in the 1995 and 2001 editions. It also resolves incompatibilities and inconsistencies of IEEE 1364-2001 with IEEE Std 1800™-2005.<br />\n
          The intent of this standard is to serve as a complete specification of the Verilog HDL. This standard contains the following:<br />\n
          — The formal syntax and semantics of all Verilog HDL constructs<br />\n
          — The formal syntax and semantics of standard delay format (SDF) constructs<br />\n
          — Simulation system tasks and functions, such as text output display commands<br />\n
          — Compiler directives, such as text substitution macros and simulation time scaling<br />\n
          — The programming language interface (PLI) binding mechanism<br />\n
          — The formal syntax and semantics of the Verilog procedural interface (VPI)<br />\n
          — Informative usage examples<br />\n
          — Informative delay model for SDF<br />\n
          — The VPI header file<br />\n
          The purpose of the original document, IEEE Std 1364-2001, was to provide an industry standard based on the Verilog Hardware Description Language. The reason for the document's revision is to incorporate corrections that have been identified by the working group since 1364-1995 and 1364-2001 were published by the IEEE.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Verilog Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1616454000 {#7292
      date: 2021-03-23 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1144360800 {#7318
      date: 2006-04-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 590
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductType App\Twig\Components\ProductType 298.0 MiB 0.26 ms
Input props 
[
  "product" => App\Entity\Product\Product {#7310
    #id: 10103
    #code: "IEEE00003641"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751038817 {#7274
      date: 2025-06-27 17:40:17.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#7322
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 35421
        #name: "IEEE 1364:2005"
        #slug: "ieee-1364-2005-ieee00003641-241755"
        #description: """
          Revision Standard - Superseded.<br />\n
          The Verilog hardware description language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementers of tools supporting the language and advanced users of the language.<br />\n
          (Supersedes IEEE Std 1364-2001. Superseded by IEEE Std 1800-2009).<br />\n
          \t\t\t\t<br />\n
          Verilog is a hardware description language (HDL) that was standardized as IEEE Std 1364™-1995 and first revised as IEEE Std 1364-2001. This revision corrects and clarifies features ambiguously described in the 1995 and 2001 editions. It also resolves incompatibilities and inconsistencies of IEEE 1364-2001 with IEEE Std 1800™-2005.<br />\n
          The intent of this standard is to serve as a complete specification of the Verilog HDL. This standard contains the following:<br />\n
          — The formal syntax and semantics of all Verilog HDL constructs<br />\n
          — The formal syntax and semantics of standard delay format (SDF) constructs<br />\n
          — Simulation system tasks and functions, such as text output display commands<br />\n
          — Compiler directives, such as text substitution macros and simulation time scaling<br />\n
          — The programming language interface (PLI) binding mechanism<br />\n
          — The formal syntax and semantics of the Verilog procedural interface (VPI)<br />\n
          — Informative usage examples<br />\n
          — Informative delay model for SDF<br />\n
          — The VPI header file<br />\n
          The purpose of the original document, IEEE Std 1364-2001, was to provide an industry standard based on the Verilog Hardware Description Language. The reason for the document's revision is to incorporate corrections that have been identified by the working group since 1364-1995 and 1364-2001 were published by the IEEE.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Verilog Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1616454000 {#7292
      date: 2021-03-23 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1144360800 {#7318
      date: 2006-04-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 590
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
]
Attributes 
[]
Component 
App\Twig\Components\ProductType {#93187
  +product: App\Entity\Product\Product {#7310
    #id: 10103
    #code: "IEEE00003641"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751038817 {#7274
      date: 2025-06-27 17:40:17.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#7322
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 35421
        #name: "IEEE 1364:2005"
        #slug: "ieee-1364-2005-ieee00003641-241755"
        #description: """
          Revision Standard - Superseded.<br />\n
          The Verilog hardware description language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementers of tools supporting the language and advanced users of the language.<br />\n
          (Supersedes IEEE Std 1364-2001. Superseded by IEEE Std 1800-2009).<br />\n
          \t\t\t\t<br />\n
          Verilog is a hardware description language (HDL) that was standardized as IEEE Std 1364™-1995 and first revised as IEEE Std 1364-2001. This revision corrects and clarifies features ambiguously described in the 1995 and 2001 editions. It also resolves incompatibilities and inconsistencies of IEEE 1364-2001 with IEEE Std 1800™-2005.<br />\n
          The intent of this standard is to serve as a complete specification of the Verilog HDL. This standard contains the following:<br />\n
          — The formal syntax and semantics of all Verilog HDL constructs<br />\n
          — The formal syntax and semantics of standard delay format (SDF) constructs<br />\n
          — Simulation system tasks and functions, such as text output display commands<br />\n
          — Compiler directives, such as text substitution macros and simulation time scaling<br />\n
          — The programming language interface (PLI) binding mechanism<br />\n
          — The formal syntax and semantics of the Verilog procedural interface (VPI)<br />\n
          — Informative usage examples<br />\n
          — Informative delay model for SDF<br />\n
          — The VPI header file<br />\n
          The purpose of the original document, IEEE Std 1364-2001, was to provide an industry standard based on the Verilog Hardware Description Language. The reason for the document's revision is to incorporate corrections that have been identified by the working group since 1364-1995 and 1364-2001 were published by the IEEE.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Verilog Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1616454000 {#7292
      date: 2021-03-23 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1144360800 {#7318
      date: 2006-04-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 590
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +label: "Standard"
  -typeAttributeCode: "type"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductMostRecent App\Twig\Components\ProductMostRecent 298.0 MiB 0.99 ms
Input props 
[
  "product" => App\Entity\Product\Product {#7310
    #id: 10103
    #code: "IEEE00003641"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751038817 {#7274
      date: 2025-06-27 17:40:17.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#7322
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 35421
        #name: "IEEE 1364:2005"
        #slug: "ieee-1364-2005-ieee00003641-241755"
        #description: """
          Revision Standard - Superseded.<br />\n
          The Verilog hardware description language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementers of tools supporting the language and advanced users of the language.<br />\n
          (Supersedes IEEE Std 1364-2001. Superseded by IEEE Std 1800-2009).<br />\n
          \t\t\t\t<br />\n
          Verilog is a hardware description language (HDL) that was standardized as IEEE Std 1364™-1995 and first revised as IEEE Std 1364-2001. This revision corrects and clarifies features ambiguously described in the 1995 and 2001 editions. It also resolves incompatibilities and inconsistencies of IEEE 1364-2001 with IEEE Std 1800™-2005.<br />\n
          The intent of this standard is to serve as a complete specification of the Verilog HDL. This standard contains the following:<br />\n
          — The formal syntax and semantics of all Verilog HDL constructs<br />\n
          — The formal syntax and semantics of standard delay format (SDF) constructs<br />\n
          — Simulation system tasks and functions, such as text output display commands<br />\n
          — Compiler directives, such as text substitution macros and simulation time scaling<br />\n
          — The programming language interface (PLI) binding mechanism<br />\n
          — The formal syntax and semantics of the Verilog procedural interface (VPI)<br />\n
          — Informative usage examples<br />\n
          — Informative delay model for SDF<br />\n
          — The VPI header file<br />\n
          The purpose of the original document, IEEE Std 1364-2001, was to provide an industry standard based on the Verilog Hardware Description Language. The reason for the document's revision is to incorporate corrections that have been identified by the working group since 1364-1995 and 1364-2001 were published by the IEEE.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Verilog Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1616454000 {#7292
      date: 2021-03-23 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1144360800 {#7318
      date: 2006-04-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 590
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
]
Attributes 
[]
Component 
App\Twig\Components\ProductMostRecent {#93262
  +product: App\Entity\Product\Product {#7310
    #id: 10103
    #code: "IEEE00003641"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751038817 {#7274
      date: 2025-06-27 17:40:17.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#7322
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 35421
        #name: "IEEE 1364:2005"
        #slug: "ieee-1364-2005-ieee00003641-241755"
        #description: """
          Revision Standard - Superseded.<br />\n
          The Verilog hardware description language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementers of tools supporting the language and advanced users of the language.<br />\n
          (Supersedes IEEE Std 1364-2001. Superseded by IEEE Std 1800-2009).<br />\n
          \t\t\t\t<br />\n
          Verilog is a hardware description language (HDL) that was standardized as IEEE Std 1364™-1995 and first revised as IEEE Std 1364-2001. This revision corrects and clarifies features ambiguously described in the 1995 and 2001 editions. It also resolves incompatibilities and inconsistencies of IEEE 1364-2001 with IEEE Std 1800™-2005.<br />\n
          The intent of this standard is to serve as a complete specification of the Verilog HDL. This standard contains the following:<br />\n
          — The formal syntax and semantics of all Verilog HDL constructs<br />\n
          — The formal syntax and semantics of standard delay format (SDF) constructs<br />\n
          — Simulation system tasks and functions, such as text output display commands<br />\n
          — Compiler directives, such as text substitution macros and simulation time scaling<br />\n
          — The programming language interface (PLI) binding mechanism<br />\n
          — The formal syntax and semantics of the Verilog procedural interface (VPI)<br />\n
          — Informative usage examples<br />\n
          — Informative delay model for SDF<br />\n
          — The VPI header file<br />\n
          The purpose of the original document, IEEE Std 1364-2001, was to provide an industry standard based on the Verilog Hardware Description Language. The reason for the document's revision is to incorporate corrections that have been identified by the working group since 1364-1995 and 1364-2001 were published by the IEEE.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Verilog Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1616454000 {#7292
      date: 2021-03-23 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1144360800 {#7318
      date: 2006-04-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 590
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +label: "Historical"
  +icon: "historical"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductState App\Twig\Components\ProductState 298.0 MiB 0.19 ms
Input props 
[
  "product" => App\Entity\Product\Product {#100252
    #id: 10248
    #code: "IEEE00003989"
    #attributes: Doctrine\ORM\PersistentCollection {#100235 …}
    #variants: Doctrine\ORM\PersistentCollection {#100232 …}
    #options: Doctrine\ORM\PersistentCollection {#100228 …}
    #associations: Doctrine\ORM\PersistentCollection {#100230 …}
    #createdAt: DateTime @1751038925 {#100260
      date: 2025-06-27 17:42:05.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#100233
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#100246 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#100275
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#100252}
        #id: 36001
        #name: "IEEE 1800:2009"
        #slug: "ieee-1800-2009-ieee00003989-241900"
        #description: """
          Revision Standard - Superseded.<br />\n
          This standard represents a merger of two previous standards: IEEE Std 1364(TM)-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document.<br />\n
          (IEEE Std1800-2009 was a revision of both IEEE Std1364-2005 and IEEE Std1800-2005.)<br />\n
          \t\t\t\t<br />\n
          This SystemVerilog standard (IEEE Std 1800) is a Unified Hardware Design, Specification, and Verification language. IEEE Std 1364TM-2005 Verilog is a design language. Both standards were approved by the IEEE-SASB in November 2005. This standard creates new revisions of the IEEE 1364 Verilog and IEEE 1800 SystemVerilog standards, which include errata fixes and resolutions, enhancements, enhanced assertion language, merger of Verilog Language Reference Manual (LRM) and SystemVerilog 1800 LRM into a single LRM, integration with Verilog-AMS, and ensures interoperability with other languages such as SystemC and VHDL.<br />\n
          The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a solid and well-defined IEEE Unified Hardware Design, Specification and Verification standard language, while resolving errata and developing enhancements to the current IEEE 1800 SystemVerilog standard. The language is designed to co-exist, be interoperable, possibly merge, and enhance those hardware description languages presently used by designers.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#100243 …}
    #channels: Doctrine\ORM\PersistentCollection {#100237 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#100241 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#100239 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#100253 …}
    -apiLastModifiedAt: DateTime @1754517600 {#100220
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1613602800 {#100259
      date: 2021-02-18 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1260486000 {#100258
      date: 2009-12-11 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1285
    -documents: Doctrine\ORM\PersistentCollection {#100250 …}
    -favorites: Doctrine\ORM\PersistentCollection {#100248 …}
  }
  "showFullLabel" => "true"
]
Attributes 
[
  "showFullLabel" => "true"
]
Component 
App\Twig\Components\ProductState {#100310
  +product: App\Entity\Product\Product {#100252
    #id: 10248
    #code: "IEEE00003989"
    #attributes: Doctrine\ORM\PersistentCollection {#100235 …}
    #variants: Doctrine\ORM\PersistentCollection {#100232 …}
    #options: Doctrine\ORM\PersistentCollection {#100228 …}
    #associations: Doctrine\ORM\PersistentCollection {#100230 …}
    #createdAt: DateTime @1751038925 {#100260
      date: 2025-06-27 17:42:05.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#100233
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#100246 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#100275
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#100252}
        #id: 36001
        #name: "IEEE 1800:2009"
        #slug: "ieee-1800-2009-ieee00003989-241900"
        #description: """
          Revision Standard - Superseded.<br />\n
          This standard represents a merger of two previous standards: IEEE Std 1364(TM)-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document.<br />\n
          (IEEE Std1800-2009 was a revision of both IEEE Std1364-2005 and IEEE Std1800-2005.)<br />\n
          \t\t\t\t<br />\n
          This SystemVerilog standard (IEEE Std 1800) is a Unified Hardware Design, Specification, and Verification language. IEEE Std 1364TM-2005 Verilog is a design language. Both standards were approved by the IEEE-SASB in November 2005. This standard creates new revisions of the IEEE 1364 Verilog and IEEE 1800 SystemVerilog standards, which include errata fixes and resolutions, enhancements, enhanced assertion language, merger of Verilog Language Reference Manual (LRM) and SystemVerilog 1800 LRM into a single LRM, integration with Verilog-AMS, and ensures interoperability with other languages such as SystemC and VHDL.<br />\n
          The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a solid and well-defined IEEE Unified Hardware Design, Specification and Verification standard language, while resolving errata and developing enhancements to the current IEEE 1800 SystemVerilog standard. The language is designed to co-exist, be interoperable, possibly merge, and enhance those hardware description languages presently used by designers.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#100243 …}
    #channels: Doctrine\ORM\PersistentCollection {#100237 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#100241 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#100239 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#100253 …}
    -apiLastModifiedAt: DateTime @1754517600 {#100220
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1613602800 {#100259
      date: 2021-02-18 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1260486000 {#100258
      date: 2009-12-11 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1285
    -documents: Doctrine\ORM\PersistentCollection {#100250 …}
    -favorites: Doctrine\ORM\PersistentCollection {#100248 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductMostRecent App\Twig\Components\ProductMostRecent 298.0 MiB 0.72 ms
Input props 
[
  "product" => App\Entity\Product\Product {#100252
    #id: 10248
    #code: "IEEE00003989"
    #attributes: Doctrine\ORM\PersistentCollection {#100235 …}
    #variants: Doctrine\ORM\PersistentCollection {#100232 …}
    #options: Doctrine\ORM\PersistentCollection {#100228 …}
    #associations: Doctrine\ORM\PersistentCollection {#100230 …}
    #createdAt: DateTime @1751038925 {#100260
      date: 2025-06-27 17:42:05.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#100233
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#100246 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#100275
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#100252}
        #id: 36001
        #name: "IEEE 1800:2009"
        #slug: "ieee-1800-2009-ieee00003989-241900"
        #description: """
          Revision Standard - Superseded.<br />\n
          This standard represents a merger of two previous standards: IEEE Std 1364(TM)-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document.<br />\n
          (IEEE Std1800-2009 was a revision of both IEEE Std1364-2005 and IEEE Std1800-2005.)<br />\n
          \t\t\t\t<br />\n
          This SystemVerilog standard (IEEE Std 1800) is a Unified Hardware Design, Specification, and Verification language. IEEE Std 1364TM-2005 Verilog is a design language. Both standards were approved by the IEEE-SASB in November 2005. This standard creates new revisions of the IEEE 1364 Verilog and IEEE 1800 SystemVerilog standards, which include errata fixes and resolutions, enhancements, enhanced assertion language, merger of Verilog Language Reference Manual (LRM) and SystemVerilog 1800 LRM into a single LRM, integration with Verilog-AMS, and ensures interoperability with other languages such as SystemC and VHDL.<br />\n
          The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a solid and well-defined IEEE Unified Hardware Design, Specification and Verification standard language, while resolving errata and developing enhancements to the current IEEE 1800 SystemVerilog standard. The language is designed to co-exist, be interoperable, possibly merge, and enhance those hardware description languages presently used by designers.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#100243 …}
    #channels: Doctrine\ORM\PersistentCollection {#100237 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#100241 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#100239 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#100253 …}
    -apiLastModifiedAt: DateTime @1754517600 {#100220
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1613602800 {#100259
      date: 2021-02-18 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1260486000 {#100258
      date: 2009-12-11 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1285
    -documents: Doctrine\ORM\PersistentCollection {#100250 …}
    -favorites: Doctrine\ORM\PersistentCollection {#100248 …}
  }
]
Attributes 
[]
Component 
App\Twig\Components\ProductMostRecent {#100377
  +product: App\Entity\Product\Product {#100252
    #id: 10248
    #code: "IEEE00003989"
    #attributes: Doctrine\ORM\PersistentCollection {#100235 …}
    #variants: Doctrine\ORM\PersistentCollection {#100232 …}
    #options: Doctrine\ORM\PersistentCollection {#100228 …}
    #associations: Doctrine\ORM\PersistentCollection {#100230 …}
    #createdAt: DateTime @1751038925 {#100260
      date: 2025-06-27 17:42:05.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#100233
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#100246 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#100275
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#100252}
        #id: 36001
        #name: "IEEE 1800:2009"
        #slug: "ieee-1800-2009-ieee00003989-241900"
        #description: """
          Revision Standard - Superseded.<br />\n
          This standard represents a merger of two previous standards: IEEE Std 1364(TM)-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document.<br />\n
          (IEEE Std1800-2009 was a revision of both IEEE Std1364-2005 and IEEE Std1800-2005.)<br />\n
          \t\t\t\t<br />\n
          This SystemVerilog standard (IEEE Std 1800) is a Unified Hardware Design, Specification, and Verification language. IEEE Std 1364TM-2005 Verilog is a design language. Both standards were approved by the IEEE-SASB in November 2005. This standard creates new revisions of the IEEE 1364 Verilog and IEEE 1800 SystemVerilog standards, which include errata fixes and resolutions, enhancements, enhanced assertion language, merger of Verilog Language Reference Manual (LRM) and SystemVerilog 1800 LRM into a single LRM, integration with Verilog-AMS, and ensures interoperability with other languages such as SystemC and VHDL.<br />\n
          The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a solid and well-defined IEEE Unified Hardware Design, Specification and Verification standard language, while resolving errata and developing enhancements to the current IEEE 1800 SystemVerilog standard. The language is designed to co-exist, be interoperable, possibly merge, and enhance those hardware description languages presently used by designers.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#100243 …}
    #channels: Doctrine\ORM\PersistentCollection {#100237 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#100241 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#100239 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#100253 …}
    -apiLastModifiedAt: DateTime @1754517600 {#100220
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1613602800 {#100259
      date: 2021-02-18 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1260486000 {#100258
      date: 2009-12-11 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1285
    -documents: Doctrine\ORM\PersistentCollection {#100250 …}
    -favorites: Doctrine\ORM\PersistentCollection {#100248 …}
  }
  +label: "Historical"
  +icon: "historical"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductState App\Twig\Components\ProductState 298.0 MiB 0.16 ms
Input props 
[
  "product" => App\Entity\Product\Product {#7310
    #id: 10103
    #code: "IEEE00003641"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751038817 {#7274
      date: 2025-06-27 17:40:17.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#7322
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 35421
        #name: "IEEE 1364:2005"
        #slug: "ieee-1364-2005-ieee00003641-241755"
        #description: """
          Revision Standard - Superseded.<br />\n
          The Verilog hardware description language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementers of tools supporting the language and advanced users of the language.<br />\n
          (Supersedes IEEE Std 1364-2001. Superseded by IEEE Std 1800-2009).<br />\n
          \t\t\t\t<br />\n
          Verilog is a hardware description language (HDL) that was standardized as IEEE Std 1364™-1995 and first revised as IEEE Std 1364-2001. This revision corrects and clarifies features ambiguously described in the 1995 and 2001 editions. It also resolves incompatibilities and inconsistencies of IEEE 1364-2001 with IEEE Std 1800™-2005.<br />\n
          The intent of this standard is to serve as a complete specification of the Verilog HDL. This standard contains the following:<br />\n
          — The formal syntax and semantics of all Verilog HDL constructs<br />\n
          — The formal syntax and semantics of standard delay format (SDF) constructs<br />\n
          — Simulation system tasks and functions, such as text output display commands<br />\n
          — Compiler directives, such as text substitution macros and simulation time scaling<br />\n
          — The programming language interface (PLI) binding mechanism<br />\n
          — The formal syntax and semantics of the Verilog procedural interface (VPI)<br />\n
          — Informative usage examples<br />\n
          — Informative delay model for SDF<br />\n
          — The VPI header file<br />\n
          The purpose of the original document, IEEE Std 1364-2001, was to provide an industry standard based on the Verilog Hardware Description Language. The reason for the document's revision is to incorporate corrections that have been identified by the working group since 1364-1995 and 1364-2001 were published by the IEEE.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Verilog Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1616454000 {#7292
      date: 2021-03-23 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1144360800 {#7318
      date: 2006-04-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 590
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  "showFullLabel" => "true"
]
Attributes 
[
  "showFullLabel" => "true"
]
Component 
App\Twig\Components\ProductState {#107020
  +product: App\Entity\Product\Product {#7310
    #id: 10103
    #code: "IEEE00003641"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751038817 {#7274
      date: 2025-06-27 17:40:17.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#7322
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 35421
        #name: "IEEE 1364:2005"
        #slug: "ieee-1364-2005-ieee00003641-241755"
        #description: """
          Revision Standard - Superseded.<br />\n
          The Verilog hardware description language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementers of tools supporting the language and advanced users of the language.<br />\n
          (Supersedes IEEE Std 1364-2001. Superseded by IEEE Std 1800-2009).<br />\n
          \t\t\t\t<br />\n
          Verilog is a hardware description language (HDL) that was standardized as IEEE Std 1364™-1995 and first revised as IEEE Std 1364-2001. This revision corrects and clarifies features ambiguously described in the 1995 and 2001 editions. It also resolves incompatibilities and inconsistencies of IEEE 1364-2001 with IEEE Std 1800™-2005.<br />\n
          The intent of this standard is to serve as a complete specification of the Verilog HDL. This standard contains the following:<br />\n
          — The formal syntax and semantics of all Verilog HDL constructs<br />\n
          — The formal syntax and semantics of standard delay format (SDF) constructs<br />\n
          — Simulation system tasks and functions, such as text output display commands<br />\n
          — Compiler directives, such as text substitution macros and simulation time scaling<br />\n
          — The programming language interface (PLI) binding mechanism<br />\n
          — The formal syntax and semantics of the Verilog procedural interface (VPI)<br />\n
          — Informative usage examples<br />\n
          — Informative delay model for SDF<br />\n
          — The VPI header file<br />\n
          The purpose of the original document, IEEE Std 1364-2001, was to provide an industry standard based on the Verilog Hardware Description Language. The reason for the document's revision is to incorporate corrections that have been identified by the working group since 1364-1995 and 1364-2001 were published by the IEEE.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Verilog Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1616454000 {#7292
      date: 2021-03-23 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1144360800 {#7318
      date: 2006-04-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 590
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductMostRecent App\Twig\Components\ProductMostRecent 298.0 MiB 0.68 ms
Input props 
[
  "product" => App\Entity\Product\Product {#7310
    #id: 10103
    #code: "IEEE00003641"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751038817 {#7274
      date: 2025-06-27 17:40:17.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#7322
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 35421
        #name: "IEEE 1364:2005"
        #slug: "ieee-1364-2005-ieee00003641-241755"
        #description: """
          Revision Standard - Superseded.<br />\n
          The Verilog hardware description language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementers of tools supporting the language and advanced users of the language.<br />\n
          (Supersedes IEEE Std 1364-2001. Superseded by IEEE Std 1800-2009).<br />\n
          \t\t\t\t<br />\n
          Verilog is a hardware description language (HDL) that was standardized as IEEE Std 1364™-1995 and first revised as IEEE Std 1364-2001. This revision corrects and clarifies features ambiguously described in the 1995 and 2001 editions. It also resolves incompatibilities and inconsistencies of IEEE 1364-2001 with IEEE Std 1800™-2005.<br />\n
          The intent of this standard is to serve as a complete specification of the Verilog HDL. This standard contains the following:<br />\n
          — The formal syntax and semantics of all Verilog HDL constructs<br />\n
          — The formal syntax and semantics of standard delay format (SDF) constructs<br />\n
          — Simulation system tasks and functions, such as text output display commands<br />\n
          — Compiler directives, such as text substitution macros and simulation time scaling<br />\n
          — The programming language interface (PLI) binding mechanism<br />\n
          — The formal syntax and semantics of the Verilog procedural interface (VPI)<br />\n
          — Informative usage examples<br />\n
          — Informative delay model for SDF<br />\n
          — The VPI header file<br />\n
          The purpose of the original document, IEEE Std 1364-2001, was to provide an industry standard based on the Verilog Hardware Description Language. The reason for the document's revision is to incorporate corrections that have been identified by the working group since 1364-1995 and 1364-2001 were published by the IEEE.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Verilog Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1616454000 {#7292
      date: 2021-03-23 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1144360800 {#7318
      date: 2006-04-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 590
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
]
Attributes 
[]
Component 
App\Twig\Components\ProductMostRecent {#107062
  +product: App\Entity\Product\Product {#7310
    #id: 10103
    #code: "IEEE00003641"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751038817 {#7274
      date: 2025-06-27 17:40:17.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#7322
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 35421
        #name: "IEEE 1364:2005"
        #slug: "ieee-1364-2005-ieee00003641-241755"
        #description: """
          Revision Standard - Superseded.<br />\n
          The Verilog hardware description language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementers of tools supporting the language and advanced users of the language.<br />\n
          (Supersedes IEEE Std 1364-2001. Superseded by IEEE Std 1800-2009).<br />\n
          \t\t\t\t<br />\n
          Verilog is a hardware description language (HDL) that was standardized as IEEE Std 1364™-1995 and first revised as IEEE Std 1364-2001. This revision corrects and clarifies features ambiguously described in the 1995 and 2001 editions. It also resolves incompatibilities and inconsistencies of IEEE 1364-2001 with IEEE Std 1800™-2005.<br />\n
          The intent of this standard is to serve as a complete specification of the Verilog HDL. This standard contains the following:<br />\n
          — The formal syntax and semantics of all Verilog HDL constructs<br />\n
          — The formal syntax and semantics of standard delay format (SDF) constructs<br />\n
          — Simulation system tasks and functions, such as text output display commands<br />\n
          — Compiler directives, such as text substitution macros and simulation time scaling<br />\n
          — The programming language interface (PLI) binding mechanism<br />\n
          — The formal syntax and semantics of the Verilog procedural interface (VPI)<br />\n
          — Informative usage examples<br />\n
          — Informative delay model for SDF<br />\n
          — The VPI header file<br />\n
          The purpose of the original document, IEEE Std 1364-2001, was to provide an industry standard based on the Verilog Hardware Description Language. The reason for the document's revision is to incorporate corrections that have been identified by the working group since 1364-1995 and 1364-2001 were published by the IEEE.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for Verilog Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1616454000 {#7292
      date: 2021-03-23 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1144360800 {#7318
      date: 2006-04-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 590
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +label: "Historical"
  +icon: "historical"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductState App\Twig\Components\ProductState 298.0 MiB 0.15 ms
Input props 
[
  "product" => App\Entity\Product\Product {#106942
    #id: 9318
    #code: "IEEE00002052"
    #attributes: Doctrine\ORM\PersistentCollection {#106958 …}
    #variants: Doctrine\ORM\PersistentCollection {#106960 …}
    #options: Doctrine\ORM\PersistentCollection {#106964 …}
    #associations: Doctrine\ORM\PersistentCollection {#106962 …}
    #createdAt: DateTime @1751038164 {#106933
      date: 2025-06-27 17:29:24.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969444 {#106931
      date: 2025-07-31 15:44:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106948 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#107129
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106942}
        #id: 32281
        #name: "IEEE 1364:2001"
        #slug: "ieee-1364-2001-ieee00002052-240970"
        #description: """
          Revision Standard - Superseded.<br />\n
          Supersedes 1364-1995. The Verilog(R) Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable,it supports the development,verification, synthesis,and testing of hardware designs; the communication of hardware design data; and the maintenance,modification,and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.<br />\n
          \t\t\t\t<br />\n
          Verilog is a Hardware Description Language which was standardized as IEEE 1364-1995. It is currently used by integrated circuit designers to specify their designs at the switch, gate and RTL levels. The proposed project will revise Verilog 1364 to include new constructs which improve the utility of the language both at the detailed physical level and at high levels of abstraction to meet industry needs for improved design technology.<br />\n
          To provide an industry standard based on the Verilog Hardware Description Language.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Verilog Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106950 …}
    #channels: Doctrine\ORM\PersistentCollection {#106956 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106952 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106954 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106941 …}
    -apiLastModifiedAt: DateTime @1743289200 {#106934
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#106927
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1001628000 {#106924
      date: 2001-09-28 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 792
    -documents: Doctrine\ORM\PersistentCollection {#106944 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106946 …}
  }
  "showFullLabel" => "true"
]
Attributes 
[
  "showFullLabel" => "true"
]
Component 
App\Twig\Components\ProductState {#107144
  +product: App\Entity\Product\Product {#106942
    #id: 9318
    #code: "IEEE00002052"
    #attributes: Doctrine\ORM\PersistentCollection {#106958 …}
    #variants: Doctrine\ORM\PersistentCollection {#106960 …}
    #options: Doctrine\ORM\PersistentCollection {#106964 …}
    #associations: Doctrine\ORM\PersistentCollection {#106962 …}
    #createdAt: DateTime @1751038164 {#106933
      date: 2025-06-27 17:29:24.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969444 {#106931
      date: 2025-07-31 15:44:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106948 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#107129
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106942}
        #id: 32281
        #name: "IEEE 1364:2001"
        #slug: "ieee-1364-2001-ieee00002052-240970"
        #description: """
          Revision Standard - Superseded.<br />\n
          Supersedes 1364-1995. The Verilog(R) Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable,it supports the development,verification, synthesis,and testing of hardware designs; the communication of hardware design data; and the maintenance,modification,and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.<br />\n
          \t\t\t\t<br />\n
          Verilog is a Hardware Description Language which was standardized as IEEE 1364-1995. It is currently used by integrated circuit designers to specify their designs at the switch, gate and RTL levels. The proposed project will revise Verilog 1364 to include new constructs which improve the utility of the language both at the detailed physical level and at high levels of abstraction to meet industry needs for improved design technology.<br />\n
          To provide an industry standard based on the Verilog Hardware Description Language.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Verilog Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106950 …}
    #channels: Doctrine\ORM\PersistentCollection {#106956 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106952 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106954 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106941 …}
    -apiLastModifiedAt: DateTime @1743289200 {#106934
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#106927
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1001628000 {#106924
      date: 2001-09-28 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 792
    -documents: Doctrine\ORM\PersistentCollection {#106944 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106946 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductMostRecent App\Twig\Components\ProductMostRecent 298.0 MiB 0.60 ms
Input props 
[
  "product" => App\Entity\Product\Product {#106942
    #id: 9318
    #code: "IEEE00002052"
    #attributes: Doctrine\ORM\PersistentCollection {#106958 …}
    #variants: Doctrine\ORM\PersistentCollection {#106960 …}
    #options: Doctrine\ORM\PersistentCollection {#106964 …}
    #associations: Doctrine\ORM\PersistentCollection {#106962 …}
    #createdAt: DateTime @1751038164 {#106933
      date: 2025-06-27 17:29:24.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969444 {#106931
      date: 2025-07-31 15:44:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106948 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#107129
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106942}
        #id: 32281
        #name: "IEEE 1364:2001"
        #slug: "ieee-1364-2001-ieee00002052-240970"
        #description: """
          Revision Standard - Superseded.<br />\n
          Supersedes 1364-1995. The Verilog(R) Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable,it supports the development,verification, synthesis,and testing of hardware designs; the communication of hardware design data; and the maintenance,modification,and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.<br />\n
          \t\t\t\t<br />\n
          Verilog is a Hardware Description Language which was standardized as IEEE 1364-1995. It is currently used by integrated circuit designers to specify their designs at the switch, gate and RTL levels. The proposed project will revise Verilog 1364 to include new constructs which improve the utility of the language both at the detailed physical level and at high levels of abstraction to meet industry needs for improved design technology.<br />\n
          To provide an industry standard based on the Verilog Hardware Description Language.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Verilog Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106950 …}
    #channels: Doctrine\ORM\PersistentCollection {#106956 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106952 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106954 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106941 …}
    -apiLastModifiedAt: DateTime @1743289200 {#106934
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#106927
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1001628000 {#106924
      date: 2001-09-28 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 792
    -documents: Doctrine\ORM\PersistentCollection {#106944 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106946 …}
  }
]
Attributes 
[]
Component 
App\Twig\Components\ProductMostRecent {#107196
  +product: App\Entity\Product\Product {#106942
    #id: 9318
    #code: "IEEE00002052"
    #attributes: Doctrine\ORM\PersistentCollection {#106958 …}
    #variants: Doctrine\ORM\PersistentCollection {#106960 …}
    #options: Doctrine\ORM\PersistentCollection {#106964 …}
    #associations: Doctrine\ORM\PersistentCollection {#106962 …}
    #createdAt: DateTime @1751038164 {#106933
      date: 2025-06-27 17:29:24.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1753969444 {#106931
      date: 2025-07-31 15:44:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106948 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#107129
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106942}
        #id: 32281
        #name: "IEEE 1364:2001"
        #slug: "ieee-1364-2001-ieee00002052-240970"
        #description: """
          Revision Standard - Superseded.<br />\n
          Supersedes 1364-1995. The Verilog(R) Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable,it supports the development,verification, synthesis,and testing of hardware designs; the communication of hardware design data; and the maintenance,modification,and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.<br />\n
          \t\t\t\t<br />\n
          Verilog is a Hardware Description Language which was standardized as IEEE 1364-1995. It is currently used by integrated circuit designers to specify their designs at the switch, gate and RTL levels. The proposed project will revise Verilog 1364 to include new constructs which improve the utility of the language both at the detailed physical level and at high levels of abstraction to meet industry needs for improved design technology.<br />\n
          To provide an industry standard based on the Verilog Hardware Description Language.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Verilog Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106950 …}
    #channels: Doctrine\ORM\PersistentCollection {#106956 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106952 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106954 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106941 …}
    -apiLastModifiedAt: DateTime @1743289200 {#106934
      date: 2025-03-30 00:00:00.0 Europe/Paris (+01:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#106927
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1001628000 {#106924
      date: 2001-09-28 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 792
    -documents: Doctrine\ORM\PersistentCollection {#106944 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106946 …}
  }
  +label: "Historical"
  +icon: "historical"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductState App\Twig\Components\ProductState 298.0 MiB 0.15 ms
Input props 
[
  "product" => App\Entity\Product\Product {#106971
    #id: 9317
    #code: "IEEE00002051"
    #attributes: Doctrine\ORM\PersistentCollection {#106988 …}
    #variants: Doctrine\ORM\PersistentCollection {#106990 …}
    #options: Doctrine\ORM\PersistentCollection {#106994 …}
    #associations: Doctrine\ORM\PersistentCollection {#106992 …}
    #createdAt: DateTime @1751038164 {#106966
      date: 2025-06-27 17:29:24.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#106967
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106978 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#107262
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106971}
        #id: 32277
        #name: "IEEE 1364:1995"
        #slug: "ieee-1364-1995-ieee00002051-240969"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          The Verilog Hardware Description Language (HDL) is defined. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.<br />\n
          \t\t\t\t<br />\n
          The intent of this standard is to serve as a complete specification of the Verilog Hardware Description Language (HDL). This document contains:<br />\n
          -- The formal syntax and semantics of all Verilog HDL construct; s<br />\n
          -- Simulation system tasks and functions, such as text output display commands;<br />\n
          -- Compiler directives, such as text substitution macros and simulation time scaling;<br />\n
          -- The Programming Language Interface (PLI) binding mechanism;<br />\n
          -- The formal syntax and semantics of access routines, task/function routines, and Verilog procedural interface routines;<br />\n
          -- Informative usage examples;<br />\n
          -- Listings of header Þles for PLI
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Hardware Description Language Based on the Verilog(R) Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106980 …}
    #channels: Doctrine\ORM\PersistentCollection {#106986 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106982 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106984 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106972 …}
    -apiLastModifiedAt: DateTime @1754517600 {#106968
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#106969
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @845244000 {#106970
      date: 1996-10-14 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 688
    -documents: Doctrine\ORM\PersistentCollection {#106974 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106976 …}
  }
  "showFullLabel" => "true"
]
Attributes 
[
  "showFullLabel" => "true"
]
Component 
App\Twig\Components\ProductState {#107277
  +product: App\Entity\Product\Product {#106971
    #id: 9317
    #code: "IEEE00002051"
    #attributes: Doctrine\ORM\PersistentCollection {#106988 …}
    #variants: Doctrine\ORM\PersistentCollection {#106990 …}
    #options: Doctrine\ORM\PersistentCollection {#106994 …}
    #associations: Doctrine\ORM\PersistentCollection {#106992 …}
    #createdAt: DateTime @1751038164 {#106966
      date: 2025-06-27 17:29:24.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#106967
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106978 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#107262
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106971}
        #id: 32277
        #name: "IEEE 1364:1995"
        #slug: "ieee-1364-1995-ieee00002051-240969"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          The Verilog Hardware Description Language (HDL) is defined. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.<br />\n
          \t\t\t\t<br />\n
          The intent of this standard is to serve as a complete specification of the Verilog Hardware Description Language (HDL). This document contains:<br />\n
          -- The formal syntax and semantics of all Verilog HDL construct; s<br />\n
          -- Simulation system tasks and functions, such as text output display commands;<br />\n
          -- Compiler directives, such as text substitution macros and simulation time scaling;<br />\n
          -- The Programming Language Interface (PLI) binding mechanism;<br />\n
          -- The formal syntax and semantics of access routines, task/function routines, and Verilog procedural interface routines;<br />\n
          -- Informative usage examples;<br />\n
          -- Listings of header Þles for PLI
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Hardware Description Language Based on the Verilog(R) Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106980 …}
    #channels: Doctrine\ORM\PersistentCollection {#106986 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106982 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106984 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106972 …}
    -apiLastModifiedAt: DateTime @1754517600 {#106968
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#106969
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @845244000 {#106970
      date: 1996-10-14 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 688
    -documents: Doctrine\ORM\PersistentCollection {#106974 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106976 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}
ProductMostRecent App\Twig\Components\ProductMostRecent 298.0 MiB 0.58 ms
Input props 
[
  "product" => App\Entity\Product\Product {#106971
    #id: 9317
    #code: "IEEE00002051"
    #attributes: Doctrine\ORM\PersistentCollection {#106988 …}
    #variants: Doctrine\ORM\PersistentCollection {#106990 …}
    #options: Doctrine\ORM\PersistentCollection {#106994 …}
    #associations: Doctrine\ORM\PersistentCollection {#106992 …}
    #createdAt: DateTime @1751038164 {#106966
      date: 2025-06-27 17:29:24.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#106967
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106978 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#107262
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106971}
        #id: 32277
        #name: "IEEE 1364:1995"
        #slug: "ieee-1364-1995-ieee00002051-240969"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          The Verilog Hardware Description Language (HDL) is defined. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.<br />\n
          \t\t\t\t<br />\n
          The intent of this standard is to serve as a complete specification of the Verilog Hardware Description Language (HDL). This document contains:<br />\n
          -- The formal syntax and semantics of all Verilog HDL construct; s<br />\n
          -- Simulation system tasks and functions, such as text output display commands;<br />\n
          -- Compiler directives, such as text substitution macros and simulation time scaling;<br />\n
          -- The Programming Language Interface (PLI) binding mechanism;<br />\n
          -- The formal syntax and semantics of access routines, task/function routines, and Verilog procedural interface routines;<br />\n
          -- Informative usage examples;<br />\n
          -- Listings of header Þles for PLI
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Hardware Description Language Based on the Verilog(R) Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106980 …}
    #channels: Doctrine\ORM\PersistentCollection {#106986 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106982 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106984 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106972 …}
    -apiLastModifiedAt: DateTime @1754517600 {#106968
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#106969
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @845244000 {#106970
      date: 1996-10-14 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 688
    -documents: Doctrine\ORM\PersistentCollection {#106974 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106976 …}
  }
]
Attributes 
[]
Component 
App\Twig\Components\ProductMostRecent {#107329
  +product: App\Entity\Product\Product {#106971
    #id: 9317
    #code: "IEEE00002051"
    #attributes: Doctrine\ORM\PersistentCollection {#106988 …}
    #variants: Doctrine\ORM\PersistentCollection {#106990 …}
    #options: Doctrine\ORM\PersistentCollection {#106994 …}
    #associations: Doctrine\ORM\PersistentCollection {#106992 …}
    #createdAt: DateTime @1751038164 {#106966
      date: 2025-06-27 17:29:24.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#106967
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106978 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#107262
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106971}
        #id: 32277
        #name: "IEEE 1364:1995"
        #slug: "ieee-1364-1995-ieee00002051-240969"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          The Verilog Hardware Description Language (HDL) is defined. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.<br />\n
          \t\t\t\t<br />\n
          The intent of this standard is to serve as a complete specification of the Verilog Hardware Description Language (HDL). This document contains:<br />\n
          -- The formal syntax and semantics of all Verilog HDL construct; s<br />\n
          -- Simulation system tasks and functions, such as text output display commands;<br />\n
          -- Compiler directives, such as text substitution macros and simulation time scaling;<br />\n
          -- The Programming Language Interface (PLI) binding mechanism;<br />\n
          -- The formal syntax and semantics of access routines, task/function routines, and Verilog procedural interface routines;<br />\n
          -- Informative usage examples;<br />\n
          -- Listings of header Þles for PLI
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard Hardware Description Language Based on the Verilog(R) Hardware Description Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106980 …}
    #channels: Doctrine\ORM\PersistentCollection {#106986 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106982 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106984 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106972 …}
    -apiLastModifiedAt: DateTime @1754517600 {#106968
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#106969
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @845244000 {#106970
      date: 1996-10-14 00:00:00.0 Europe/Paris (+02:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1364"
    -bookCollection: ""
    -pageCount: 688
    -documents: Doctrine\ORM\PersistentCollection {#106974 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106976 …}
  }
  +label: "Historical"
  +icon: "historical"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}