Components

4 Twig Components
8 Render Count
17 ms Render Time
128.0 MiB Memory Usage

Components

Name Metadata Render Count Render Time
ProductState
"App\Twig\Components\ProductState"
components/ProductState.html.twig
3 2.72ms
ProductMostRecent
"App\Twig\Components\ProductMostRecent"
components/ProductMostRecent.html.twig
3 2.95ms
ProductType
"App\Twig\Components\ProductType"
components/ProductType.html.twig
1 0.65ms
ProductCard
"App\Twig\Components\ProductCard"
components/ProductCard.html.twig
1 11.64ms

Render calls

ProductState App\Twig\Components\ProductState 108.0 MiB 2.21 ms
Input props
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          IThe VITAL (VHDL Initiative Towards ASIC Libraries) ASIC Modeling Specification is defined in this standard. This modeling specification defines a methodology which promotes the development of highly accurate, efficient simulation models for ASIC (Application-Specific Integrated Circuit) components in VHDL.<br />\n
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Attributes
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Component
App\Twig\Components\ProductState {#92909
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    #enabled: true
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ProductType App\Twig\Components\ProductType 108.0 MiB 0.65 ms
Input props
[
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    #attributes: Doctrine\ORM\PersistentCollection {#7608 …}
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    #options: Doctrine\ORM\PersistentCollection {#7823 …}
    #associations: Doctrine\ORM\PersistentCollection {#7807 …}
    #createdAt: DateTime @1751038822 {#7303
      date: 2025-06-27 17:40:22.0 Europe/Paris (+02:00)
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    #updatedAt: DateTime @1754608190 {#7340
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    #enabled: true
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          IThe VITAL (VHDL Initiative Towards ASIC Libraries) ASIC Modeling Specification is defined in this standard. This modeling specification defines a methodology which promotes the development of highly accurate, efficient simulation models for ASIC (Application-Specific Integrated Circuit) components in VHDL.<br />\n
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Attributes
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Component
App\Twig\Components\ProductType {#93080
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    #createdAt: DateTime @1751038822 {#7303
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          IThe VITAL (VHDL Initiative Towards ASIC Libraries) ASIC Modeling Specification is defined in this standard. This modeling specification defines a methodology which promotes the development of highly accurate, efficient simulation models for ASIC (Application-Specific Integrated Circuit) components in VHDL.<br />\n
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}
ProductMostRecent App\Twig\Components\ProductMostRecent 108.0 MiB 1.17 ms
Input props
[
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Attributes
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Component
App\Twig\Components\ProductMostRecent {#93155
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ProductState App\Twig\Components\ProductState 108.0 MiB 0.22 ms
Input props
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Component
App\Twig\Components\ProductState {#100095
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