Symfony Profiler

[
  "product" => App\Entity\Product\Product {#7310
    #id: 11861
    #code: "IEEE00006700"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751040040 {#7274
      date: 2025-06-27 18:00:40.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754608621 {#7322
      date: 2025-08-08 01:17:01.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 42453
        #name: "IEEE 1800:2017"
        #slug: "ieee-1800-2017-ieee00006700-243513"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800(TM) SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1709074800 {#7292
      date: 2024-02-28 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1519254000 {#7318
      date: 2018-02-22 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  "showFullLabel" => "true"
]

[
  "showFullLabel" => "true"
]

App\Twig\Components\ProductState {#92999
  +product: App\Entity\Product\Product {#7310
    #id: 11861
    #code: "IEEE00006700"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751040040 {#7274
      date: 2025-06-27 18:00:40.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754608621 {#7322
      date: 2025-08-08 01:17:01.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 42453
        #name: "IEEE 1800:2017"
        #slug: "ieee-1800-2017-ieee00006700-243513"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800(TM) SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1709074800 {#7292
      date: 2024-02-28 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1519254000 {#7318
      date: 2018-02-22 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

[
  "product" => App\Entity\Product\Product {#7310
    #id: 11861
    #code: "IEEE00006700"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751040040 {#7274
      date: 2025-06-27 18:00:40.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754608621 {#7322
      date: 2025-08-08 01:17:01.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 42453
        #name: "IEEE 1800:2017"
        #slug: "ieee-1800-2017-ieee00006700-243513"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800(TM) SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1709074800 {#7292
      date: 2024-02-28 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1519254000 {#7318
      date: 2018-02-22 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
]

App\Twig\Components\ProductType {#93177
  +product: App\Entity\Product\Product {#7310
    #id: 11861
    #code: "IEEE00006700"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751040040 {#7274
      date: 2025-06-27 18:00:40.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754608621 {#7322
      date: 2025-08-08 01:17:01.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 42453
        #name: "IEEE 1800:2017"
        #slug: "ieee-1800-2017-ieee00006700-243513"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800(TM) SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1709074800 {#7292
      date: 2024-02-28 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1519254000 {#7318
      date: 2018-02-22 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +label: "Standard"
  -typeAttributeCode: "type"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

[
  "product" => App\Entity\Product\Product {#7310
    #id: 11861
    #code: "IEEE00006700"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751040040 {#7274
      date: 2025-06-27 18:00:40.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754608621 {#7322
      date: 2025-08-08 01:17:01.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 42453
        #name: "IEEE 1800:2017"
        #slug: "ieee-1800-2017-ieee00006700-243513"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800(TM) SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1709074800 {#7292
      date: 2024-02-28 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1519254000 {#7318
      date: 2018-02-22 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
]

App\Twig\Components\ProductMostRecent {#93244
  +product: App\Entity\Product\Product {#7310
    #id: 11861
    #code: "IEEE00006700"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751040040 {#7274
      date: 2025-06-27 18:00:40.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754608621 {#7322
      date: 2025-08-08 01:17:01.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 42453
        #name: "IEEE 1800:2017"
        #slug: "ieee-1800-2017-ieee00006700-243513"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800(TM) SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1709074800 {#7292
      date: 2024-02-28 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1519254000 {#7318
      date: 2018-02-22 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +label: "Historical"
  +icon: "historical"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

[
  "product" => App\Entity\Product\Product {#100225
    #id: 10743
    #code: "IEEE00004934"
    #attributes: Doctrine\ORM\PersistentCollection {#100208 …}
    #variants: Doctrine\ORM\PersistentCollection {#100205 …}
    #options: Doctrine\ORM\PersistentCollection {#100201 …}
    #associations: Doctrine\ORM\PersistentCollection {#100203 …}
    #createdAt: DateTime @1751039255 {#100233
      date: 2025-06-27 17:47:35.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#100206
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#100219 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#100243
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#100225}
        #id: 37981
        #name: "IEEE 1800:2012"
        #slug: "ieee-1800-2012-ieee00004934-242395"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified<br />\n
          hardware design, specification, and verification language, is provided. This standard includes<br />\n
          support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level<br />\n
          abstraction levels, and for writing test benches using coverage, assertions, object-oriented<br />\n
          programming, and constrained random verification. The standard also provides application<br />\n
          programming interfaces (APIs) to foreign programming languages. (Thanks to our sponsor, the PDF of this standard is provided to the public no charge. Visit GETIEEE program located at https://ieeexplore.ieee.org/browse/standards/get-program/page for details.)<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800™<br />\n
          SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2009.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#100216 …}
    #channels: Doctrine\ORM\PersistentCollection {#100210 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#100214 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#100212 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#100226 …}
    -apiLastModifiedAt: DateTime @1754517600 {#100193
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#100232
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1361401200 {#100231
      date: 2013-02-21 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#100223 …}
    -favorites: Doctrine\ORM\PersistentCollection {#100221 …}
  }
  "showFullLabel" => "true"
]

[
  "showFullLabel" => "true"
]

App\Twig\Components\ProductState {#100279
  +product: App\Entity\Product\Product {#100225
    #id: 10743
    #code: "IEEE00004934"
    #attributes: Doctrine\ORM\PersistentCollection {#100208 …}
    #variants: Doctrine\ORM\PersistentCollection {#100205 …}
    #options: Doctrine\ORM\PersistentCollection {#100201 …}
    #associations: Doctrine\ORM\PersistentCollection {#100203 …}
    #createdAt: DateTime @1751039255 {#100233
      date: 2025-06-27 17:47:35.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#100206
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#100219 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#100243
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#100225}
        #id: 37981
        #name: "IEEE 1800:2012"
        #slug: "ieee-1800-2012-ieee00004934-242395"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified<br />\n
          hardware design, specification, and verification language, is provided. This standard includes<br />\n
          support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level<br />\n
          abstraction levels, and for writing test benches using coverage, assertions, object-oriented<br />\n
          programming, and constrained random verification. The standard also provides application<br />\n
          programming interfaces (APIs) to foreign programming languages. (Thanks to our sponsor, the PDF of this standard is provided to the public no charge. Visit GETIEEE program located at https://ieeexplore.ieee.org/browse/standards/get-program/page for details.)<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800™<br />\n
          SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2009.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#100216 …}
    #channels: Doctrine\ORM\PersistentCollection {#100210 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#100214 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#100212 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#100226 …}
    -apiLastModifiedAt: DateTime @1754517600 {#100193
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#100232
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1361401200 {#100231
      date: 2013-02-21 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#100223 …}
    -favorites: Doctrine\ORM\PersistentCollection {#100221 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

[
  "product" => App\Entity\Product\Product {#100225
    #id: 10743
    #code: "IEEE00004934"
    #attributes: Doctrine\ORM\PersistentCollection {#100208 …}
    #variants: Doctrine\ORM\PersistentCollection {#100205 …}
    #options: Doctrine\ORM\PersistentCollection {#100201 …}
    #associations: Doctrine\ORM\PersistentCollection {#100203 …}
    #createdAt: DateTime @1751039255 {#100233
      date: 2025-06-27 17:47:35.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#100206
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#100219 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#100243
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#100225}
        #id: 37981
        #name: "IEEE 1800:2012"
        #slug: "ieee-1800-2012-ieee00004934-242395"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified<br />\n
          hardware design, specification, and verification language, is provided. This standard includes<br />\n
          support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level<br />\n
          abstraction levels, and for writing test benches using coverage, assertions, object-oriented<br />\n
          programming, and constrained random verification. The standard also provides application<br />\n
          programming interfaces (APIs) to foreign programming languages. (Thanks to our sponsor, the PDF of this standard is provided to the public no charge. Visit GETIEEE program located at https://ieeexplore.ieee.org/browse/standards/get-program/page for details.)<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800™<br />\n
          SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2009.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#100216 …}
    #channels: Doctrine\ORM\PersistentCollection {#100210 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#100214 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#100212 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#100226 …}
    -apiLastModifiedAt: DateTime @1754517600 {#100193
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#100232
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1361401200 {#100231
      date: 2013-02-21 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#100223 …}
    -favorites: Doctrine\ORM\PersistentCollection {#100221 …}
  }
]

App\Twig\Components\ProductMostRecent {#100347
  +product: App\Entity\Product\Product {#100225
    #id: 10743
    #code: "IEEE00004934"
    #attributes: Doctrine\ORM\PersistentCollection {#100208 …}
    #variants: Doctrine\ORM\PersistentCollection {#100205 …}
    #options: Doctrine\ORM\PersistentCollection {#100201 …}
    #associations: Doctrine\ORM\PersistentCollection {#100203 …}
    #createdAt: DateTime @1751039255 {#100233
      date: 2025-06-27 17:47:35.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#100206
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#100219 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#100243
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#100225}
        #id: 37981
        #name: "IEEE 1800:2012"
        #slug: "ieee-1800-2012-ieee00004934-242395"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified<br />\n
          hardware design, specification, and verification language, is provided. This standard includes<br />\n
          support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level<br />\n
          abstraction levels, and for writing test benches using coverage, assertions, object-oriented<br />\n
          programming, and constrained random verification. The standard also provides application<br />\n
          programming interfaces (APIs) to foreign programming languages. (Thanks to our sponsor, the PDF of this standard is provided to the public no charge. Visit GETIEEE program located at https://ieeexplore.ieee.org/browse/standards/get-program/page for details.)<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800™<br />\n
          SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2009.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#100216 …}
    #channels: Doctrine\ORM\PersistentCollection {#100210 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#100214 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#100212 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#100226 …}
    -apiLastModifiedAt: DateTime @1754517600 {#100193
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#100232
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1361401200 {#100231
      date: 2013-02-21 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#100223 …}
    -favorites: Doctrine\ORM\PersistentCollection {#100221 …}
  }
  +label: "Historical"
  +icon: "historical"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

[
  "product" => App\Entity\Product\Product {#7310
    #id: 11861
    #code: "IEEE00006700"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751040040 {#7274
      date: 2025-06-27 18:00:40.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754608621 {#7322
      date: 2025-08-08 01:17:01.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 42453
        #name: "IEEE 1800:2017"
        #slug: "ieee-1800-2017-ieee00006700-243513"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800(TM) SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1709074800 {#7292
      date: 2024-02-28 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1519254000 {#7318
      date: 2018-02-22 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  "showFullLabel" => "true"
]

[
  "showFullLabel" => "true"
]

App\Twig\Components\ProductState {#106987
  +product: App\Entity\Product\Product {#7310
    #id: 11861
    #code: "IEEE00006700"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751040040 {#7274
      date: 2025-06-27 18:00:40.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754608621 {#7322
      date: 2025-08-08 01:17:01.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 42453
        #name: "IEEE 1800:2017"
        #slug: "ieee-1800-2017-ieee00006700-243513"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800(TM) SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1709074800 {#7292
      date: 2024-02-28 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1519254000 {#7318
      date: 2018-02-22 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

[
  "product" => App\Entity\Product\Product {#7310
    #id: 11861
    #code: "IEEE00006700"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751040040 {#7274
      date: 2025-06-27 18:00:40.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754608621 {#7322
      date: 2025-08-08 01:17:01.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 42453
        #name: "IEEE 1800:2017"
        #slug: "ieee-1800-2017-ieee00006700-243513"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800(TM) SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1709074800 {#7292
      date: 2024-02-28 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1519254000 {#7318
      date: 2018-02-22 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
]

App\Twig\Components\ProductMostRecent {#107029
  +product: App\Entity\Product\Product {#7310
    #id: 11861
    #code: "IEEE00006700"
    #attributes: Doctrine\ORM\PersistentCollection {#7700 …}
    #variants: Doctrine\ORM\PersistentCollection {#7743 …}
    #options: Doctrine\ORM\PersistentCollection {#7915 …}
    #associations: Doctrine\ORM\PersistentCollection {#7899 …}
    #createdAt: DateTime @1751040040 {#7274
      date: 2025-06-27 18:00:40.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754608621 {#7322
      date: 2025-08-08 01:17:01.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#7921 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#7920
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#7310}
        #id: 42453
        #name: "IEEE 1800:2017"
        #slug: "ieee-1800-2017-ieee00006700-243513"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800(TM) SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …}
    #channels: Doctrine\ORM\PersistentCollection {#7627 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#7612 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#7644 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …}
    -apiLastModifiedAt: DateTime @1754517600 {#7317
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1709074800 {#7292
      date: 2024-02-28 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1519254000 {#7318
      date: 2018-02-22 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#7464 …}
    -favorites: Doctrine\ORM\PersistentCollection {#7499 …}
  }
  +label: "Historical"
  +icon: "historical"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

[
  "product" => App\Entity\Product\Product {#100225
    #id: 10743
    #code: "IEEE00004934"
    #attributes: Doctrine\ORM\PersistentCollection {#100208 …}
    #variants: Doctrine\ORM\PersistentCollection {#100205 …}
    #options: Doctrine\ORM\PersistentCollection {#100201 …}
    #associations: Doctrine\ORM\PersistentCollection {#100203 …}
    #createdAt: DateTime @1751039255 {#100233
      date: 2025-06-27 17:47:35.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#100206
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#100219 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#100243
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#100225}
        #id: 37981
        #name: "IEEE 1800:2012"
        #slug: "ieee-1800-2012-ieee00004934-242395"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified<br />\n
          hardware design, specification, and verification language, is provided. This standard includes<br />\n
          support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level<br />\n
          abstraction levels, and for writing test benches using coverage, assertions, object-oriented<br />\n
          programming, and constrained random verification. The standard also provides application<br />\n
          programming interfaces (APIs) to foreign programming languages. (Thanks to our sponsor, the PDF of this standard is provided to the public no charge. Visit GETIEEE program located at https://ieeexplore.ieee.org/browse/standards/get-program/page for details.)<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800™<br />\n
          SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2009.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#100216 …}
    #channels: Doctrine\ORM\PersistentCollection {#100210 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#100214 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#100212 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#100226 …}
    -apiLastModifiedAt: DateTime @1754517600 {#100193
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#100232
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1361401200 {#100231
      date: 2013-02-21 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#100223 …}
    -favorites: Doctrine\ORM\PersistentCollection {#100221 …}
  }
  "showFullLabel" => "true"
]

[
  "showFullLabel" => "true"
]

App\Twig\Components\ProductState {#107094
  +product: App\Entity\Product\Product {#100225
    #id: 10743
    #code: "IEEE00004934"
    #attributes: Doctrine\ORM\PersistentCollection {#100208 …}
    #variants: Doctrine\ORM\PersistentCollection {#100205 …}
    #options: Doctrine\ORM\PersistentCollection {#100201 …}
    #associations: Doctrine\ORM\PersistentCollection {#100203 …}
    #createdAt: DateTime @1751039255 {#100233
      date: 2025-06-27 17:47:35.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#100206
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#100219 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#100243
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#100225}
        #id: 37981
        #name: "IEEE 1800:2012"
        #slug: "ieee-1800-2012-ieee00004934-242395"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified<br />\n
          hardware design, specification, and verification language, is provided. This standard includes<br />\n
          support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level<br />\n
          abstraction levels, and for writing test benches using coverage, assertions, object-oriented<br />\n
          programming, and constrained random verification. The standard also provides application<br />\n
          programming interfaces (APIs) to foreign programming languages. (Thanks to our sponsor, the PDF of this standard is provided to the public no charge. Visit GETIEEE program located at https://ieeexplore.ieee.org/browse/standards/get-program/page for details.)<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800™<br />\n
          SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2009.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#100216 …}
    #channels: Doctrine\ORM\PersistentCollection {#100210 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#100214 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#100212 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#100226 …}
    -apiLastModifiedAt: DateTime @1754517600 {#100193
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#100232
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1361401200 {#100231
      date: 2013-02-21 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#100223 …}
    -favorites: Doctrine\ORM\PersistentCollection {#100221 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

[
  "product" => App\Entity\Product\Product {#100225
    #id: 10743
    #code: "IEEE00004934"
    #attributes: Doctrine\ORM\PersistentCollection {#100208 …}
    #variants: Doctrine\ORM\PersistentCollection {#100205 …}
    #options: Doctrine\ORM\PersistentCollection {#100201 …}
    #associations: Doctrine\ORM\PersistentCollection {#100203 …}
    #createdAt: DateTime @1751039255 {#100233
      date: 2025-06-27 17:47:35.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#100206
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#100219 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#100243
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#100225}
        #id: 37981
        #name: "IEEE 1800:2012"
        #slug: "ieee-1800-2012-ieee00004934-242395"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified<br />\n
          hardware design, specification, and verification language, is provided. This standard includes<br />\n
          support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level<br />\n
          abstraction levels, and for writing test benches using coverage, assertions, object-oriented<br />\n
          programming, and constrained random verification. The standard also provides application<br />\n
          programming interfaces (APIs) to foreign programming languages. (Thanks to our sponsor, the PDF of this standard is provided to the public no charge. Visit GETIEEE program located at https://ieeexplore.ieee.org/browse/standards/get-program/page for details.)<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800™<br />\n
          SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2009.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#100216 …}
    #channels: Doctrine\ORM\PersistentCollection {#100210 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#100214 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#100212 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#100226 …}
    -apiLastModifiedAt: DateTime @1754517600 {#100193
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#100232
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1361401200 {#100231
      date: 2013-02-21 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#100223 …}
    -favorites: Doctrine\ORM\PersistentCollection {#100221 …}
  }
]

App\Twig\Components\ProductMostRecent {#107121
  +product: App\Entity\Product\Product {#100225
    #id: 10743
    #code: "IEEE00004934"
    #attributes: Doctrine\ORM\PersistentCollection {#100208 …}
    #variants: Doctrine\ORM\PersistentCollection {#100205 …}
    #options: Doctrine\ORM\PersistentCollection {#100201 …}
    #associations: Doctrine\ORM\PersistentCollection {#100203 …}
    #createdAt: DateTime @1751039255 {#100233
      date: 2025-06-27 17:47:35.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#100206
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#100219 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#100243
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#100225}
        #id: 37981
        #name: "IEEE 1800:2012"
        #slug: "ieee-1800-2012-ieee00004934-242395"
        #description: """
          Revision Standard - Superseded.<br />\n
          The definition of the language syntax and semantics for SystemVerilog, which is a unified<br />\n
          hardware design, specification, and verification language, is provided. This standard includes<br />\n
          support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level<br />\n
          abstraction levels, and for writing test benches using coverage, assertions, object-oriented<br />\n
          programming, and constrained random verification. The standard also provides application<br />\n
          programming interfaces (APIs) to foreign programming languages. (Thanks to our sponsor, the PDF of this standard is provided to the public no charge. Visit GETIEEE program located at https://ieeexplore.ieee.org/browse/standards/get-program/page for details.)<br />\n
          \t\t\t\t<br />\n
          This standard provides the definition of the language syntax and semantics for the IEEE 1800™<br />\n
          SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.<br />\n
          This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2009.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#100216 …}
    #channels: Doctrine\ORM\PersistentCollection {#100210 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#100214 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#100212 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#100226 …}
    -apiLastModifiedAt: DateTime @1754517600 {#100193
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#100232
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1361401200 {#100231
      date: 2013-02-21 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1315
    -documents: Doctrine\ORM\PersistentCollection {#100223 …}
    -favorites: Doctrine\ORM\PersistentCollection {#100221 …}
  }
  +label: "Historical"
  +icon: "historical"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

[
  "product" => App\Entity\Product\Product {#106909
    #id: 10248
    #code: "IEEE00003989"
    #attributes: Doctrine\ORM\PersistentCollection {#106925 …}
    #variants: Doctrine\ORM\PersistentCollection {#106927 …}
    #options: Doctrine\ORM\PersistentCollection {#106931 …}
    #associations: Doctrine\ORM\PersistentCollection {#106929 …}
    #createdAt: DateTime @1751038925 {#106901
      date: 2025-06-27 17:42:05.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#106898
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106915 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#107191
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106909}
        #id: 36001
        #name: "IEEE 1800:2009"
        #slug: "ieee-1800-2009-ieee00003989-241900"
        #description: """
          Revision Standard - Superseded.<br />\n
          This standard represents a merger of two previous standards: IEEE Std 1364(TM)-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document.<br />\n
          (IEEE Std1800-2009 was a revision of both IEEE Std1364-2005 and IEEE Std1800-2005.)<br />\n
          \t\t\t\t<br />\n
          This SystemVerilog standard (IEEE Std 1800) is a Unified Hardware Design, Specification, and Verification language. IEEE Std 1364TM-2005 Verilog is a design language. Both standards were approved by the IEEE-SASB in November 2005. This standard creates new revisions of the IEEE 1364 Verilog and IEEE 1800 SystemVerilog standards, which include errata fixes and resolutions, enhancements, enhanced assertion language, merger of Verilog Language Reference Manual (LRM) and SystemVerilog 1800 LRM into a single LRM, integration with Verilog-AMS, and ensures interoperability with other languages such as SystemC and VHDL.<br />\n
          The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a solid and well-defined IEEE Unified Hardware Design, Specification and Verification standard language, while resolving errata and developing enhancements to the current IEEE 1800 SystemVerilog standard. The language is designed to co-exist, be interoperable, possibly merge, and enhance those hardware description languages presently used by designers.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106917 …}
    #channels: Doctrine\ORM\PersistentCollection {#106923 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106919 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106921 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106908 …}
    -apiLastModifiedAt: DateTime @1754517600 {#106900
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1613602800 {#106902
      date: 2021-02-18 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1260486000 {#106903
      date: 2009-12-11 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1285
    -documents: Doctrine\ORM\PersistentCollection {#106911 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106913 …}
  }
  "showFullLabel" => "true"
]

[
  "showFullLabel" => "true"
]

App\Twig\Components\ProductState {#4613
  +product: App\Entity\Product\Product {#106909
    #id: 10248
    #code: "IEEE00003989"
    #attributes: Doctrine\ORM\PersistentCollection {#106925 …}
    #variants: Doctrine\ORM\PersistentCollection {#106927 …}
    #options: Doctrine\ORM\PersistentCollection {#106931 …}
    #associations: Doctrine\ORM\PersistentCollection {#106929 …}
    #createdAt: DateTime @1751038925 {#106901
      date: 2025-06-27 17:42:05.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#106898
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106915 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#107191
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106909}
        #id: 36001
        #name: "IEEE 1800:2009"
        #slug: "ieee-1800-2009-ieee00003989-241900"
        #description: """
          Revision Standard - Superseded.<br />\n
          This standard represents a merger of two previous standards: IEEE Std 1364(TM)-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document.<br />\n
          (IEEE Std1800-2009 was a revision of both IEEE Std1364-2005 and IEEE Std1800-2005.)<br />\n
          \t\t\t\t<br />\n
          This SystemVerilog standard (IEEE Std 1800) is a Unified Hardware Design, Specification, and Verification language. IEEE Std 1364TM-2005 Verilog is a design language. Both standards were approved by the IEEE-SASB in November 2005. This standard creates new revisions of the IEEE 1364 Verilog and IEEE 1800 SystemVerilog standards, which include errata fixes and resolutions, enhancements, enhanced assertion language, merger of Verilog Language Reference Manual (LRM) and SystemVerilog 1800 LRM into a single LRM, integration with Verilog-AMS, and ensures interoperability with other languages such as SystemC and VHDL.<br />\n
          The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a solid and well-defined IEEE Unified Hardware Design, Specification and Verification standard language, while resolving errata and developing enhancements to the current IEEE 1800 SystemVerilog standard. The language is designed to co-exist, be interoperable, possibly merge, and enhance those hardware description languages presently used by designers.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106917 …}
    #channels: Doctrine\ORM\PersistentCollection {#106923 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106919 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106921 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106908 …}
    -apiLastModifiedAt: DateTime @1754517600 {#106900
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1613602800 {#106902
      date: 2021-02-18 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1260486000 {#106903
      date: 2009-12-11 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1285
    -documents: Doctrine\ORM\PersistentCollection {#106911 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106913 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

[
  "product" => App\Entity\Product\Product {#106909
    #id: 10248
    #code: "IEEE00003989"
    #attributes: Doctrine\ORM\PersistentCollection {#106925 …}
    #variants: Doctrine\ORM\PersistentCollection {#106927 …}
    #options: Doctrine\ORM\PersistentCollection {#106931 …}
    #associations: Doctrine\ORM\PersistentCollection {#106929 …}
    #createdAt: DateTime @1751038925 {#106901
      date: 2025-06-27 17:42:05.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#106898
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106915 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#107191
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106909}
        #id: 36001
        #name: "IEEE 1800:2009"
        #slug: "ieee-1800-2009-ieee00003989-241900"
        #description: """
          Revision Standard - Superseded.<br />\n
          This standard represents a merger of two previous standards: IEEE Std 1364(TM)-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document.<br />\n
          (IEEE Std1800-2009 was a revision of both IEEE Std1364-2005 and IEEE Std1800-2005.)<br />\n
          \t\t\t\t<br />\n
          This SystemVerilog standard (IEEE Std 1800) is a Unified Hardware Design, Specification, and Verification language. IEEE Std 1364TM-2005 Verilog is a design language. Both standards were approved by the IEEE-SASB in November 2005. This standard creates new revisions of the IEEE 1364 Verilog and IEEE 1800 SystemVerilog standards, which include errata fixes and resolutions, enhancements, enhanced assertion language, merger of Verilog Language Reference Manual (LRM) and SystemVerilog 1800 LRM into a single LRM, integration with Verilog-AMS, and ensures interoperability with other languages such as SystemC and VHDL.<br />\n
          The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a solid and well-defined IEEE Unified Hardware Design, Specification and Verification standard language, while resolving errata and developing enhancements to the current IEEE 1800 SystemVerilog standard. The language is designed to co-exist, be interoperable, possibly merge, and enhance those hardware description languages presently used by designers.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106917 …}
    #channels: Doctrine\ORM\PersistentCollection {#106923 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106919 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106921 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106908 …}
    -apiLastModifiedAt: DateTime @1754517600 {#106900
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1613602800 {#106902
      date: 2021-02-18 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1260486000 {#106903
      date: 2009-12-11 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1285
    -documents: Doctrine\ORM\PersistentCollection {#106911 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106913 …}
  }
]

App\Twig\Components\ProductMostRecent {#4682
  +product: App\Entity\Product\Product {#106909
    #id: 10248
    #code: "IEEE00003989"
    #attributes: Doctrine\ORM\PersistentCollection {#106925 …}
    #variants: Doctrine\ORM\PersistentCollection {#106927 …}
    #options: Doctrine\ORM\PersistentCollection {#106931 …}
    #associations: Doctrine\ORM\PersistentCollection {#106929 …}
    #createdAt: DateTime @1751038925 {#106901
      date: 2025-06-27 17:42:05.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607611 {#106898
      date: 2025-08-08 01:00:11.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106915 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#107191
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106909}
        #id: 36001
        #name: "IEEE 1800:2009"
        #slug: "ieee-1800-2009-ieee00003989-241900"
        #description: """
          Revision Standard - Superseded.<br />\n
          This standard represents a merger of two previous standards: IEEE Std 1364(TM)-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document.<br />\n
          (IEEE Std1800-2009 was a revision of both IEEE Std1364-2005 and IEEE Std1800-2005.)<br />\n
          \t\t\t\t<br />\n
          This SystemVerilog standard (IEEE Std 1800) is a Unified Hardware Design, Specification, and Verification language. IEEE Std 1364TM-2005 Verilog is a design language. Both standards were approved by the IEEE-SASB in November 2005. This standard creates new revisions of the IEEE 1364 Verilog and IEEE 1800 SystemVerilog standards, which include errata fixes and resolutions, enhancements, enhanced assertion language, merger of Verilog Language Reference Manual (LRM) and SystemVerilog 1800 LRM into a single LRM, integration with Verilog-AMS, and ensures interoperability with other languages such as SystemC and VHDL.<br />\n
          The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a solid and well-defined IEEE Unified Hardware Design, Specification and Verification standard language, while resolving errata and developing enhancements to the current IEEE 1800 SystemVerilog standard. The language is designed to co-exist, be interoperable, possibly merge, and enhance those hardware description languages presently used by designers.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106917 …}
    #channels: Doctrine\ORM\PersistentCollection {#106923 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106919 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106921 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106908 …}
    -apiLastModifiedAt: DateTime @1754517600 {#106900
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1613602800 {#106902
      date: 2021-02-18 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1260486000 {#106903
      date: 2009-12-11 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 1285
    -documents: Doctrine\ORM\PersistentCollection {#106911 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106913 …}
  }
  +label: "Historical"
  +icon: "historical"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

[
  "product" => App\Entity\Product\Product {#106938
    #id: 10090
    #code: "IEEE00003617"
    #attributes: Doctrine\ORM\PersistentCollection {#106955 …}
    #variants: Doctrine\ORM\PersistentCollection {#106957 …}
    #options: Doctrine\ORM\PersistentCollection {#106961 …}
    #associations: Doctrine\ORM\PersistentCollection {#106959 …}
    #createdAt: DateTime @1751038807 {#106933
      date: 2025-06-27 17:40:07.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#106934
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106945 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#93406
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106938}
        #id: 35369
        #name: "IEEE 1800:2005"
        #slug: "ieee-1800-2005-ieee00003617-241742"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          This standard represents a merger of two previous standards: IEEE 1364-2005 Verilog hardware description language (HDL) and IEEE 1800-2005 SystemVerilog unified hardware design, specification and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard enables users to have all information regarding syntax and semantics in a single document.<br />\n
          \t\t\t\t<br />\n
          SystemVerilog is a Unified Hardware Design, Specification and Verification language that is based on the work done by Accellera, a consortium of Electronic Design Automation (EDA), semiconductor, and system companies. The proposed project will create an IEEE standard that is leveraged from Accellera SystemVerilog 3.1a. The new standard will include design specification methods, embedded assertions language, test bench language including coverage and assertions API, and a direct programming interface. The proposed SystemVerilog standard enables a productivity boost in design and validation, and covers design, simulation, validation, and formal assertion based verification flows.<br />\n
          The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a well-defined and official IEEE Unified Hardware Design, Specification and Verification standard language. The language is designed to co-exist and enhance those hardware description languages presently used by designers while providing the capabilities lacking in those languages.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog: Unified Hardware Design, Specification and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106947 …}
    #channels: Doctrine\ORM\PersistentCollection {#106953 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106949 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106951 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106939 …}
    -apiLastModifiedAt: DateTime @1754517600 {#106935
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#106936
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1132614000 {#106937
      date: 2005-11-22 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 648
    -documents: Doctrine\ORM\PersistentCollection {#106941 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106943 …}
  }
  "showFullLabel" => "true"
]

[
  "showFullLabel" => "true"
]

App\Twig\Components\ProductState {#107194
  +product: App\Entity\Product\Product {#106938
    #id: 10090
    #code: "IEEE00003617"
    #attributes: Doctrine\ORM\PersistentCollection {#106955 …}
    #variants: Doctrine\ORM\PersistentCollection {#106957 …}
    #options: Doctrine\ORM\PersistentCollection {#106961 …}
    #associations: Doctrine\ORM\PersistentCollection {#106959 …}
    #createdAt: DateTime @1751038807 {#106933
      date: 2025-06-27 17:40:07.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#106934
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106945 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#93406
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106938}
        #id: 35369
        #name: "IEEE 1800:2005"
        #slug: "ieee-1800-2005-ieee00003617-241742"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          This standard represents a merger of two previous standards: IEEE 1364-2005 Verilog hardware description language (HDL) and IEEE 1800-2005 SystemVerilog unified hardware design, specification and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard enables users to have all information regarding syntax and semantics in a single document.<br />\n
          \t\t\t\t<br />\n
          SystemVerilog is a Unified Hardware Design, Specification and Verification language that is based on the work done by Accellera, a consortium of Electronic Design Automation (EDA), semiconductor, and system companies. The proposed project will create an IEEE standard that is leveraged from Accellera SystemVerilog 3.1a. The new standard will include design specification methods, embedded assertions language, test bench language including coverage and assertions API, and a direct programming interface. The proposed SystemVerilog standard enables a productivity boost in design and validation, and covers design, simulation, validation, and formal assertion based verification flows.<br />\n
          The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a well-defined and official IEEE Unified Hardware Design, Specification and Verification standard language. The language is designed to co-exist and enhance those hardware description languages presently used by designers while providing the capabilities lacking in those languages.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog: Unified Hardware Design, Specification and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106947 …}
    #channels: Doctrine\ORM\PersistentCollection {#106953 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106949 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106951 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106939 …}
    -apiLastModifiedAt: DateTime @1754517600 {#106935
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#106936
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1132614000 {#106937
      date: 2005-11-22 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 648
    -documents: Doctrine\ORM\PersistentCollection {#106941 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106943 …}
  }
  +appearance: "state-suspended"
  +labels: [
    "Superseded"
  ]
  -stateAttributeCode: "state"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}

[
  "product" => App\Entity\Product\Product {#106938
    #id: 10090
    #code: "IEEE00003617"
    #attributes: Doctrine\ORM\PersistentCollection {#106955 …}
    #variants: Doctrine\ORM\PersistentCollection {#106957 …}
    #options: Doctrine\ORM\PersistentCollection {#106961 …}
    #associations: Doctrine\ORM\PersistentCollection {#106959 …}
    #createdAt: DateTime @1751038807 {#106933
      date: 2025-06-27 17:40:07.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#106934
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106945 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#93406
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106938}
        #id: 35369
        #name: "IEEE 1800:2005"
        #slug: "ieee-1800-2005-ieee00003617-241742"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          This standard represents a merger of two previous standards: IEEE 1364-2005 Verilog hardware description language (HDL) and IEEE 1800-2005 SystemVerilog unified hardware design, specification and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard enables users to have all information regarding syntax and semantics in a single document.<br />\n
          \t\t\t\t<br />\n
          SystemVerilog is a Unified Hardware Design, Specification and Verification language that is based on the work done by Accellera, a consortium of Electronic Design Automation (EDA), semiconductor, and system companies. The proposed project will create an IEEE standard that is leveraged from Accellera SystemVerilog 3.1a. The new standard will include design specification methods, embedded assertions language, test bench language including coverage and assertions API, and a direct programming interface. The proposed SystemVerilog standard enables a productivity boost in design and validation, and covers design, simulation, validation, and formal assertion based verification flows.<br />\n
          The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a well-defined and official IEEE Unified Hardware Design, Specification and Verification standard language. The language is designed to co-exist and enhance those hardware description languages presently used by designers while providing the capabilities lacking in those languages.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog: Unified Hardware Design, Specification and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106947 …}
    #channels: Doctrine\ORM\PersistentCollection {#106953 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106949 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106951 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106939 …}
    -apiLastModifiedAt: DateTime @1754517600 {#106935
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#106936
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1132614000 {#106937
      date: 2005-11-22 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 648
    -documents: Doctrine\ORM\PersistentCollection {#106941 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106943 …}
  }
]

App\Twig\Components\ProductMostRecent {#107245
  +product: App\Entity\Product\Product {#106938
    #id: 10090
    #code: "IEEE00003617"
    #attributes: Doctrine\ORM\PersistentCollection {#106955 …}
    #variants: Doctrine\ORM\PersistentCollection {#106957 …}
    #options: Doctrine\ORM\PersistentCollection {#106961 …}
    #associations: Doctrine\ORM\PersistentCollection {#106959 …}
    #createdAt: DateTime @1751038807 {#106933
      date: 2025-06-27 17:40:07.0 Europe/Paris (+02:00)
    }
    #updatedAt: DateTime @1754607004 {#106934
      date: 2025-08-08 00:50:04.0 Europe/Paris (+02:00)
    }
    #enabled: true
    #translations: Doctrine\ORM\PersistentCollection {#106945 …}
    #translationsCache: [
      "en_US" => App\Entity\Product\ProductTranslation {#93406
        #locale: "en_US"
        #translatable: App\Entity\Product\Product {#106938}
        #id: 35369
        #name: "IEEE 1800:2005"
        #slug: "ieee-1800-2005-ieee00003617-241742"
        #description: """
          New IEEE Standard - Superseded.<br />\n
          This standard represents a merger of two previous standards: IEEE 1364-2005 Verilog hardware description language (HDL) and IEEE 1800-2005 SystemVerilog unified hardware design, specification and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard enables users to have all information regarding syntax and semantics in a single document.<br />\n
          \t\t\t\t<br />\n
          SystemVerilog is a Unified Hardware Design, Specification and Verification language that is based on the work done by Accellera, a consortium of Electronic Design Automation (EDA), semiconductor, and system companies. The proposed project will create an IEEE standard that is leveraged from Accellera SystemVerilog 3.1a. The new standard will include design specification methods, embedded assertions language, test bench language including coverage and assertions API, and a direct programming interface. The proposed SystemVerilog standard enables a productivity boost in design and validation, and covers design, simulation, validation, and formal assertion based verification flows.<br />\n
          The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a well-defined and official IEEE Unified Hardware Design, Specification and Verification standard language. The language is designed to co-exist and enhance those hardware description languages presently used by designers while providing the capabilities lacking in those languages.
          """
        #metaKeywords: null
        #metaDescription: null
        #shortDescription: "IEEE Standard for SystemVerilog: Unified Hardware Design, Specification and Verification Language"
        -notes: "Superseded"
      }
    ]
    #currentLocale: "en_US"
    #currentTranslation: null
    #fallbackLocale: "en_US"
    #variantSelectionMethod: "match"
    #productTaxons: Doctrine\ORM\PersistentCollection {#106947 …}
    #channels: Doctrine\ORM\PersistentCollection {#106953 …}
    #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …}
    #reviews: Doctrine\ORM\PersistentCollection {#106949 …}
    #averageRating: 0.0
    #images: Doctrine\ORM\PersistentCollection {#106951 …}
    -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …}
    -subscriptionCollections: Doctrine\ORM\PersistentCollection {#106939 …}
    -apiLastModifiedAt: DateTime @1754517600 {#106935
      date: 2025-08-07 00:00:00.0 Europe/Paris (+02:00)
    }
    -lastUpdatedAt: DateTime @1578006000 {#106936
      date: 2020-01-03 00:00:00.0 Europe/Paris (+01:00)
    }
    -author: ""
    -publishedAt: DateTime @1132614000 {#106937
      date: 2005-11-22 00:00:00.0 Europe/Paris (+01:00)
    }
    -releasedAt: null
    -confirmedAt: null
    -canceledAt: null
    -edition: null
    -coreDocument: "1800"
    -bookCollection: ""
    -pageCount: 648
    -documents: Doctrine\ORM\PersistentCollection {#106941 …}
    -favorites: Doctrine\ORM\PersistentCollection {#106943 …}
  }
  +label: "Historical"
  +icon: "historical"
  -mostRecentAttributeCode: "most_recent"
  -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …}
}