Components
4
Twig Components
8
Render Count
13
ms
Render Time
96.0
MiB
Memory Usage
Components
| Name | Metadata | Render Count | Render Time |
|---|---|---|---|
| ProductState |
"App\Twig\Components\ProductState"components/ProductState.html.twig |
3 | 0.92ms |
| ProductMostRecent |
"App\Twig\Components\ProductMostRecent"components/ProductMostRecent.html.twig |
3 | 2.79ms |
| ProductType |
"App\Twig\Components\ProductType"components/ProductType.html.twig |
1 | 0.32ms |
| ProductCard |
"App\Twig\Components\ProductCard"components/ProductCard.html.twig |
1 | 9.69ms |
Render calls
| ProductState | App\Twig\Components\ProductState | 76.0 MiB | 0.46 ms | |
|---|---|---|---|---|
| Input props | [ "product" => App\Entity\Product\Product {#7310 #id: 9097 #code: "IEEE00001615" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 …} #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751037968 {#7274 : 2025-06-27 17:26:08.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607004 {#7322 : 2025-08-08 00:50:04.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 31397 #name: "IEEE 1076.3:1997" #slug: "ieee-1076-3-1997-ieee00001615-240749" #description: """ New IEEE Standard - Superseded.<br />\n The current interpretation of common logic values and the association of numeric values to specific VHDL array types is described. This standard provides semantic for the VHDL synthesis domain, and enables formal verification and simulation acceleration in the VHDL based design. The standard interpretations are provided for values of standard logic types defined by IEEE Std 1164-1993, and of the BIT and BOOLEAN types defined in IEEE Std 1076-1993. The numeric types SIGNED and UNSIGNED and their associated operators define integer and natural number arithmetic for arrays of common logic values. Twos complement and binary encoding techniques are used. The numeric semantic is conveyed by two VHDL packages. This standard also contains any allowable modifications.<br />\n \t\t\t\t<br />\n This standard defines standard practices for synthesizing binary digital electronic circuits from VHDL source code. It includes the following:<br />\n a) The hardware interpretation of values belonging to the BIT and BOOLEAN types deÞned by IEEE<br />\n Std 1076-1993 and to the STD_ULOGIC type defined by IEEE Std 1164-1993.<br />\n b) A function (STD_MATCH) that provides "don't care" or "wild card" testing of values based on the<br />\n STD_ULOGIC type.<br />\n c) Standard functions for representing sensitivity to the edge of a signal.<br />\n d) Two packages that deÞne vector types for representing signed and unsigned arithmetic values, and<br />\n that define arithmetic, shift, and type conversion operations on those types.<br />\n This standard is designed for use with IEEE Std 1076-1993. Modifications that may be made to the packages for use with the previous edition, IEEE Std 1076-1987, are described in 7.2.<br />\n Only some parts of the VHSIC Hardware Description Language (VHDL) are able to be synthesized currently. There are also no current standards describing how to create these needed portable descriptions in VHDL that can be synthesized. This standard will define a set of packages to allow this portability of synthesizable descriptions. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard VHDL Synthesis Packages" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @865461600 {#7318 : 1997-06-05 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1076.3" -bookCollection: "" -pageCount: 52 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } "showFullLabel" => "true" ] |
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| Attributes | [ "showFullLabel" => "true" ] |
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| Component | App\Twig\Components\ProductState {#92999 +product: App\Entity\Product\Product {#7310 #id: 9097 #code: "IEEE00001615" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 …} #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751037968 {#7274 : 2025-06-27 17:26:08.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607004 {#7322 : 2025-08-08 00:50:04.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 31397 #name: "IEEE 1076.3:1997" #slug: "ieee-1076-3-1997-ieee00001615-240749" #description: """ New IEEE Standard - Superseded.<br />\n The current interpretation of common logic values and the association of numeric values to specific VHDL array types is described. This standard provides semantic for the VHDL synthesis domain, and enables formal verification and simulation acceleration in the VHDL based design. The standard interpretations are provided for values of standard logic types defined by IEEE Std 1164-1993, and of the BIT and BOOLEAN types defined in IEEE Std 1076-1993. The numeric types SIGNED and UNSIGNED and their associated operators define integer and natural number arithmetic for arrays of common logic values. Twos complement and binary encoding techniques are used. The numeric semantic is conveyed by two VHDL packages. This standard also contains any allowable modifications.<br />\n \t\t\t\t<br />\n This standard defines standard practices for synthesizing binary digital electronic circuits from VHDL source code. It includes the following:<br />\n a) The hardware interpretation of values belonging to the BIT and BOOLEAN types deÞned by IEEE<br />\n Std 1076-1993 and to the STD_ULOGIC type defined by IEEE Std 1164-1993.<br />\n b) A function (STD_MATCH) that provides "don't care" or "wild card" testing of values based on the<br />\n STD_ULOGIC type.<br />\n c) Standard functions for representing sensitivity to the edge of a signal.<br />\n d) Two packages that deÞne vector types for representing signed and unsigned arithmetic values, and<br />\n that define arithmetic, shift, and type conversion operations on those types.<br />\n This standard is designed for use with IEEE Std 1076-1993. Modifications that may be made to the packages for use with the previous edition, IEEE Std 1076-1987, are described in 7.2.<br />\n Only some parts of the VHSIC Hardware Description Language (VHDL) are able to be synthesized currently. There are also no current standards describing how to create these needed portable descriptions in VHDL that can be synthesized. This standard will define a set of packages to allow this portability of synthesizable descriptions. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard VHDL Synthesis Packages" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @865461600 {#7318 : 1997-06-05 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1076.3" -bookCollection: "" -pageCount: 52 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } +appearance: "state-suspended" +labels: [ "Superseded" ] -stateAttributeCode: "state" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …} } |
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| ProductType | App\Twig\Components\ProductType | 76.0 MiB | 0.32 ms | |
|---|---|---|---|---|
| Input props | [ "product" => App\Entity\Product\Product {#7310 #id: 9097 #code: "IEEE00001615" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 …} #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751037968 {#7274 : 2025-06-27 17:26:08.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607004 {#7322 : 2025-08-08 00:50:04.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 31397 #name: "IEEE 1076.3:1997" #slug: "ieee-1076-3-1997-ieee00001615-240749" #description: """ New IEEE Standard - Superseded.<br />\n The current interpretation of common logic values and the association of numeric values to specific VHDL array types is described. This standard provides semantic for the VHDL synthesis domain, and enables formal verification and simulation acceleration in the VHDL based design. The standard interpretations are provided for values of standard logic types defined by IEEE Std 1164-1993, and of the BIT and BOOLEAN types defined in IEEE Std 1076-1993. The numeric types SIGNED and UNSIGNED and their associated operators define integer and natural number arithmetic for arrays of common logic values. Twos complement and binary encoding techniques are used. The numeric semantic is conveyed by two VHDL packages. This standard also contains any allowable modifications.<br />\n \t\t\t\t<br />\n This standard defines standard practices for synthesizing binary digital electronic circuits from VHDL source code. It includes the following:<br />\n a) The hardware interpretation of values belonging to the BIT and BOOLEAN types deÞned by IEEE<br />\n Std 1076-1993 and to the STD_ULOGIC type defined by IEEE Std 1164-1993.<br />\n b) A function (STD_MATCH) that provides "don't care" or "wild card" testing of values based on the<br />\n STD_ULOGIC type.<br />\n c) Standard functions for representing sensitivity to the edge of a signal.<br />\n d) Two packages that deÞne vector types for representing signed and unsigned arithmetic values, and<br />\n that define arithmetic, shift, and type conversion operations on those types.<br />\n This standard is designed for use with IEEE Std 1076-1993. Modifications that may be made to the packages for use with the previous edition, IEEE Std 1076-1987, are described in 7.2.<br />\n Only some parts of the VHSIC Hardware Description Language (VHDL) are able to be synthesized currently. There are also no current standards describing how to create these needed portable descriptions in VHDL that can be synthesized. This standard will define a set of packages to allow this portability of synthesizable descriptions. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard VHDL Synthesis Packages" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @865461600 {#7318 : 1997-06-05 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1076.3" -bookCollection: "" -pageCount: 52 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } ] |
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| Attributes | [] |
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| Component | App\Twig\Components\ProductType {#93179 +product: App\Entity\Product\Product {#7310 #id: 9097 #code: "IEEE00001615" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 …} #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751037968 {#7274 : 2025-06-27 17:26:08.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607004 {#7322 : 2025-08-08 00:50:04.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 31397 #name: "IEEE 1076.3:1997" #slug: "ieee-1076-3-1997-ieee00001615-240749" #description: """ New IEEE Standard - Superseded.<br />\n The current interpretation of common logic values and the association of numeric values to specific VHDL array types is described. This standard provides semantic for the VHDL synthesis domain, and enables formal verification and simulation acceleration in the VHDL based design. The standard interpretations are provided for values of standard logic types defined by IEEE Std 1164-1993, and of the BIT and BOOLEAN types defined in IEEE Std 1076-1993. The numeric types SIGNED and UNSIGNED and their associated operators define integer and natural number arithmetic for arrays of common logic values. Twos complement and binary encoding techniques are used. The numeric semantic is conveyed by two VHDL packages. This standard also contains any allowable modifications.<br />\n \t\t\t\t<br />\n This standard defines standard practices for synthesizing binary digital electronic circuits from VHDL source code. It includes the following:<br />\n a) The hardware interpretation of values belonging to the BIT and BOOLEAN types deÞned by IEEE<br />\n Std 1076-1993 and to the STD_ULOGIC type defined by IEEE Std 1164-1993.<br />\n b) A function (STD_MATCH) that provides "don't care" or "wild card" testing of values based on the<br />\n STD_ULOGIC type.<br />\n c) Standard functions for representing sensitivity to the edge of a signal.<br />\n d) Two packages that deÞne vector types for representing signed and unsigned arithmetic values, and<br />\n that define arithmetic, shift, and type conversion operations on those types.<br />\n This standard is designed for use with IEEE Std 1076-1993. Modifications that may be made to the packages for use with the previous edition, IEEE Std 1076-1987, are described in 7.2.<br />\n Only some parts of the VHSIC Hardware Description Language (VHDL) are able to be synthesized currently. There are also no current standards describing how to create these needed portable descriptions in VHDL that can be synthesized. This standard will define a set of packages to allow this portability of synthesizable descriptions. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard VHDL Synthesis Packages" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @865461600 {#7318 : 1997-06-05 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1076.3" -bookCollection: "" -pageCount: 52 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } +label: "Standard" -typeAttributeCode: "type" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …} } |
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| ProductMostRecent | App\Twig\Components\ProductMostRecent | 76.0 MiB | 1.05 ms | |
|---|---|---|---|---|
| Input props | [ "product" => App\Entity\Product\Product {#7310 #id: 9097 #code: "IEEE00001615" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 …} #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751037968 {#7274 : 2025-06-27 17:26:08.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607004 {#7322 : 2025-08-08 00:50:04.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 31397 #name: "IEEE 1076.3:1997" #slug: "ieee-1076-3-1997-ieee00001615-240749" #description: """ New IEEE Standard - Superseded.<br />\n The current interpretation of common logic values and the association of numeric values to specific VHDL array types is described. This standard provides semantic for the VHDL synthesis domain, and enables formal verification and simulation acceleration in the VHDL based design. The standard interpretations are provided for values of standard logic types defined by IEEE Std 1164-1993, and of the BIT and BOOLEAN types defined in IEEE Std 1076-1993. The numeric types SIGNED and UNSIGNED and their associated operators define integer and natural number arithmetic for arrays of common logic values. Twos complement and binary encoding techniques are used. The numeric semantic is conveyed by two VHDL packages. This standard also contains any allowable modifications.<br />\n \t\t\t\t<br />\n This standard defines standard practices for synthesizing binary digital electronic circuits from VHDL source code. It includes the following:<br />\n a) The hardware interpretation of values belonging to the BIT and BOOLEAN types deÞned by IEEE<br />\n Std 1076-1993 and to the STD_ULOGIC type defined by IEEE Std 1164-1993.<br />\n b) A function (STD_MATCH) that provides "don't care" or "wild card" testing of values based on the<br />\n STD_ULOGIC type.<br />\n c) Standard functions for representing sensitivity to the edge of a signal.<br />\n d) Two packages that deÞne vector types for representing signed and unsigned arithmetic values, and<br />\n that define arithmetic, shift, and type conversion operations on those types.<br />\n This standard is designed for use with IEEE Std 1076-1993. Modifications that may be made to the packages for use with the previous edition, IEEE Std 1076-1987, are described in 7.2.<br />\n Only some parts of the VHSIC Hardware Description Language (VHDL) are able to be synthesized currently. There are also no current standards describing how to create these needed portable descriptions in VHDL that can be synthesized. This standard will define a set of packages to allow this portability of synthesizable descriptions. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard VHDL Synthesis Packages" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @865461600 {#7318 : 1997-06-05 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1076.3" -bookCollection: "" -pageCount: 52 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } ] |
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| Attributes | [] |
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| Component | App\Twig\Components\ProductMostRecent {#93254 +product: App\Entity\Product\Product {#7310 #id: 9097 #code: "IEEE00001615" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 …} #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751037968 {#7274 : 2025-06-27 17:26:08.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607004 {#7322 : 2025-08-08 00:50:04.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 31397 #name: "IEEE 1076.3:1997" #slug: "ieee-1076-3-1997-ieee00001615-240749" #description: """ New IEEE Standard - Superseded.<br />\n The current interpretation of common logic values and the association of numeric values to specific VHDL array types is described. This standard provides semantic for the VHDL synthesis domain, and enables formal verification and simulation acceleration in the VHDL based design. The standard interpretations are provided for values of standard logic types defined by IEEE Std 1164-1993, and of the BIT and BOOLEAN types defined in IEEE Std 1076-1993. The numeric types SIGNED and UNSIGNED and their associated operators define integer and natural number arithmetic for arrays of common logic values. Twos complement and binary encoding techniques are used. The numeric semantic is conveyed by two VHDL packages. This standard also contains any allowable modifications.<br />\n \t\t\t\t<br />\n This standard defines standard practices for synthesizing binary digital electronic circuits from VHDL source code. It includes the following:<br />\n a) The hardware interpretation of values belonging to the BIT and BOOLEAN types deÞned by IEEE<br />\n Std 1076-1993 and to the STD_ULOGIC type defined by IEEE Std 1164-1993.<br />\n b) A function (STD_MATCH) that provides "don't care" or "wild card" testing of values based on the<br />\n STD_ULOGIC type.<br />\n c) Standard functions for representing sensitivity to the edge of a signal.<br />\n d) Two packages that deÞne vector types for representing signed and unsigned arithmetic values, and<br />\n that define arithmetic, shift, and type conversion operations on those types.<br />\n This standard is designed for use with IEEE Std 1076-1993. Modifications that may be made to the packages for use with the previous edition, IEEE Std 1076-1987, are described in 7.2.<br />\n Only some parts of the VHSIC Hardware Description Language (VHDL) are able to be synthesized currently. There are also no current standards describing how to create these needed portable descriptions in VHDL that can be synthesized. This standard will define a set of packages to allow this portability of synthesizable descriptions. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard VHDL Synthesis Packages" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @865461600 {#7318 : 1997-06-05 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1076.3" -bookCollection: "" -pageCount: 52 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } +label: "Historical" +icon: "historical" -mostRecentAttributeCode: "most_recent" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …} } |
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| ProductState | App\Twig\Components\ProductState | 76.0 MiB | 0.26 ms | |
|---|---|---|---|---|
| Input props | [ "product" => App\Entity\Product\Product {#7310 #id: 9097 #code: "IEEE00001615" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 …} #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751037968 {#7274 : 2025-06-27 17:26:08.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607004 {#7322 : 2025-08-08 00:50:04.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 31397 #name: "IEEE 1076.3:1997" #slug: "ieee-1076-3-1997-ieee00001615-240749" #description: """ New IEEE Standard - Superseded.<br />\n The current interpretation of common logic values and the association of numeric values to specific VHDL array types is described. This standard provides semantic for the VHDL synthesis domain, and enables formal verification and simulation acceleration in the VHDL based design. The standard interpretations are provided for values of standard logic types defined by IEEE Std 1164-1993, and of the BIT and BOOLEAN types defined in IEEE Std 1076-1993. The numeric types SIGNED and UNSIGNED and their associated operators define integer and natural number arithmetic for arrays of common logic values. Twos complement and binary encoding techniques are used. The numeric semantic is conveyed by two VHDL packages. This standard also contains any allowable modifications.<br />\n \t\t\t\t<br />\n This standard defines standard practices for synthesizing binary digital electronic circuits from VHDL source code. It includes the following:<br />\n a) The hardware interpretation of values belonging to the BIT and BOOLEAN types deÞned by IEEE<br />\n Std 1076-1993 and to the STD_ULOGIC type defined by IEEE Std 1164-1993.<br />\n b) A function (STD_MATCH) that provides "don't care" or "wild card" testing of values based on the<br />\n STD_ULOGIC type.<br />\n c) Standard functions for representing sensitivity to the edge of a signal.<br />\n d) Two packages that deÞne vector types for representing signed and unsigned arithmetic values, and<br />\n that define arithmetic, shift, and type conversion operations on those types.<br />\n This standard is designed for use with IEEE Std 1076-1993. Modifications that may be made to the packages for use with the previous edition, IEEE Std 1076-1987, are described in 7.2.<br />\n Only some parts of the VHSIC Hardware Description Language (VHDL) are able to be synthesized currently. There are also no current standards describing how to create these needed portable descriptions in VHDL that can be synthesized. This standard will define a set of packages to allow this portability of synthesizable descriptions. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard VHDL Synthesis Packages" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @865461600 {#7318 : 1997-06-05 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1076.3" -bookCollection: "" -pageCount: 52 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } "showFullLabel" => "true" ] |
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| Attributes | [ "showFullLabel" => "true" ] |
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| Component | App\Twig\Components\ProductState {#100209 +product: App\Entity\Product\Product {#7310 #id: 9097 #code: "IEEE00001615" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 …} #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751037968 {#7274 : 2025-06-27 17:26:08.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607004 {#7322 : 2025-08-08 00:50:04.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 31397 #name: "IEEE 1076.3:1997" #slug: "ieee-1076-3-1997-ieee00001615-240749" #description: """ New IEEE Standard - Superseded.<br />\n The current interpretation of common logic values and the association of numeric values to specific VHDL array types is described. This standard provides semantic for the VHDL synthesis domain, and enables formal verification and simulation acceleration in the VHDL based design. The standard interpretations are provided for values of standard logic types defined by IEEE Std 1164-1993, and of the BIT and BOOLEAN types defined in IEEE Std 1076-1993. The numeric types SIGNED and UNSIGNED and their associated operators define integer and natural number arithmetic for arrays of common logic values. Twos complement and binary encoding techniques are used. The numeric semantic is conveyed by two VHDL packages. This standard also contains any allowable modifications.<br />\n \t\t\t\t<br />\n This standard defines standard practices for synthesizing binary digital electronic circuits from VHDL source code. It includes the following:<br />\n a) The hardware interpretation of values belonging to the BIT and BOOLEAN types deÞned by IEEE<br />\n Std 1076-1993 and to the STD_ULOGIC type defined by IEEE Std 1164-1993.<br />\n b) A function (STD_MATCH) that provides "don't care" or "wild card" testing of values based on the<br />\n STD_ULOGIC type.<br />\n c) Standard functions for representing sensitivity to the edge of a signal.<br />\n d) Two packages that deÞne vector types for representing signed and unsigned arithmetic values, and<br />\n that define arithmetic, shift, and type conversion operations on those types.<br />\n This standard is designed for use with IEEE Std 1076-1993. Modifications that may be made to the packages for use with the previous edition, IEEE Std 1076-1987, are described in 7.2.<br />\n Only some parts of the VHSIC Hardware Description Language (VHDL) are able to be synthesized currently. There are also no current standards describing how to create these needed portable descriptions in VHDL that can be synthesized. This standard will define a set of packages to allow this portability of synthesizable descriptions. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard VHDL Synthesis Packages" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @865461600 {#7318 : 1997-06-05 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1076.3" -bookCollection: "" -pageCount: 52 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } +appearance: "state-suspended" +labels: [ "Superseded" ] -stateAttributeCode: "state" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …} } |
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| ProductMostRecent | App\Twig\Components\ProductMostRecent | 76.0 MiB | 1.06 ms | |
|---|---|---|---|---|
| Input props | [ "product" => App\Entity\Product\Product {#7310 #id: 9097 #code: "IEEE00001615" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 …} #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751037968 {#7274 : 2025-06-27 17:26:08.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607004 {#7322 : 2025-08-08 00:50:04.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 31397 #name: "IEEE 1076.3:1997" #slug: "ieee-1076-3-1997-ieee00001615-240749" #description: """ New IEEE Standard - Superseded.<br />\n The current interpretation of common logic values and the association of numeric values to specific VHDL array types is described. This standard provides semantic for the VHDL synthesis domain, and enables formal verification and simulation acceleration in the VHDL based design. The standard interpretations are provided for values of standard logic types defined by IEEE Std 1164-1993, and of the BIT and BOOLEAN types defined in IEEE Std 1076-1993. The numeric types SIGNED and UNSIGNED and their associated operators define integer and natural number arithmetic for arrays of common logic values. Twos complement and binary encoding techniques are used. The numeric semantic is conveyed by two VHDL packages. This standard also contains any allowable modifications.<br />\n \t\t\t\t<br />\n This standard defines standard practices for synthesizing binary digital electronic circuits from VHDL source code. It includes the following:<br />\n a) The hardware interpretation of values belonging to the BIT and BOOLEAN types deÞned by IEEE<br />\n Std 1076-1993 and to the STD_ULOGIC type defined by IEEE Std 1164-1993.<br />\n b) A function (STD_MATCH) that provides "don't care" or "wild card" testing of values based on the<br />\n STD_ULOGIC type.<br />\n c) Standard functions for representing sensitivity to the edge of a signal.<br />\n d) Two packages that deÞne vector types for representing signed and unsigned arithmetic values, and<br />\n that define arithmetic, shift, and type conversion operations on those types.<br />\n This standard is designed for use with IEEE Std 1076-1993. Modifications that may be made to the packages for use with the previous edition, IEEE Std 1076-1987, are described in 7.2.<br />\n Only some parts of the VHSIC Hardware Description Language (VHDL) are able to be synthesized currently. There are also no current standards describing how to create these needed portable descriptions in VHDL that can be synthesized. This standard will define a set of packages to allow this portability of synthesizable descriptions. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard VHDL Synthesis Packages" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @865461600 {#7318 : 1997-06-05 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1076.3" -bookCollection: "" -pageCount: 52 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } ] |
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| Attributes | [] |
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| Component | App\Twig\Components\ProductMostRecent {#100293 +product: App\Entity\Product\Product {#7310 #id: 9097 #code: "IEEE00001615" #attributes: Doctrine\ORM\PersistentCollection {#7700 …} #variants: Doctrine\ORM\PersistentCollection {#7743 …} #options: Doctrine\ORM\PersistentCollection {#7915 …} #associations: Doctrine\ORM\PersistentCollection {#7899 …} #createdAt: DateTime @1751037968 {#7274 : 2025-06-27 17:26:08.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607004 {#7322 : 2025-08-08 00:50:04.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#7921 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#7920 #locale: "en_US" #translatable: App\Entity\Product\Product {#7310} #id: 31397 #name: "IEEE 1076.3:1997" #slug: "ieee-1076-3-1997-ieee00001615-240749" #description: """ New IEEE Standard - Superseded.<br />\n The current interpretation of common logic values and the association of numeric values to specific VHDL array types is described. This standard provides semantic for the VHDL synthesis domain, and enables formal verification and simulation acceleration in the VHDL based design. The standard interpretations are provided for values of standard logic types defined by IEEE Std 1164-1993, and of the BIT and BOOLEAN types defined in IEEE Std 1076-1993. The numeric types SIGNED and UNSIGNED and their associated operators define integer and natural number arithmetic for arrays of common logic values. Twos complement and binary encoding techniques are used. The numeric semantic is conveyed by two VHDL packages. This standard also contains any allowable modifications.<br />\n \t\t\t\t<br />\n This standard defines standard practices for synthesizing binary digital electronic circuits from VHDL source code. It includes the following:<br />\n a) The hardware interpretation of values belonging to the BIT and BOOLEAN types deÞned by IEEE<br />\n Std 1076-1993 and to the STD_ULOGIC type defined by IEEE Std 1164-1993.<br />\n b) A function (STD_MATCH) that provides "don't care" or "wild card" testing of values based on the<br />\n STD_ULOGIC type.<br />\n c) Standard functions for representing sensitivity to the edge of a signal.<br />\n d) Two packages that deÞne vector types for representing signed and unsigned arithmetic values, and<br />\n that define arithmetic, shift, and type conversion operations on those types.<br />\n This standard is designed for use with IEEE Std 1076-1993. Modifications that may be made to the packages for use with the previous edition, IEEE Std 1076-1987, are described in 7.2.<br />\n Only some parts of the VHSIC Hardware Description Language (VHDL) are able to be synthesized currently. There are also no current standards describing how to create these needed portable descriptions in VHDL that can be synthesized. This standard will define a set of packages to allow this portability of synthesizable descriptions. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard VHDL Synthesis Packages" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#7533 …} #channels: Doctrine\ORM\PersistentCollection {#7627 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#7612 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#7644 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#7389 …} -apiLastModifiedAt: DateTime @1754517600 {#7317 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#7292 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @865461600 {#7318 : 1997-06-05 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1076.3" -bookCollection: "" -pageCount: 52 -documents: Doctrine\ORM\PersistentCollection {#7464 …} -favorites: Doctrine\ORM\PersistentCollection {#7499 …} } +label: "Historical" +icon: "historical" -mostRecentAttributeCode: "most_recent" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …} } |
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| ProductCard | App\Twig\Components\ProductCard | 96.0 MiB | 9.69 ms | |
|---|---|---|---|---|
| Input props | [ "product" => App\Entity\Product\Product {#121515 #id: 9093 #code: "IEEE00001611" #attributes: Doctrine\ORM\PersistentCollection {#121539 …} #variants: Doctrine\ORM\PersistentCollection {#121537 …} #options: Doctrine\ORM\PersistentCollection {#121532 …} #associations: Doctrine\ORM\PersistentCollection {#121535 …} #createdAt: DateTime @1751037965 {#121528 : 2025-06-27 17:26:05.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#121521 : 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#121550 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#121648 #locale: "en_US" #translatable: App\Entity\Product\Product {#121515} #id: 31381 #name: "IEEE 1076:1993" #slug: "ieee-1076-1993-ieee00001611-240745" #description: """ Revision Standard - Superseded.<br />\n Aiding in the comprehension and use of IEEE VHDL, this unique product offers a comprehensive & reliable tutorial on VHDL - not available anywhere else. An enhancement to IEEE Std 1076-1993, the interactive tutorial is organized into four modules designed to incrementally add to the user's understanding of VHDL and it's applications. This hands-on tutorial shows clear links between the many levels and layers of VHDL and provides actual examples of VHDL implementation, making it an indispensible tool for VHDL product development and users.<br />\n \t\t\t\t<br />\n The intent of this standard is to define VHDL accurately. Its primary audiences are the implementor of tools 5 supporting the language and the advanced user of the language. Other users are encouraged to use commercially available books, tutorials, and classes to learn the language in some detail prior to reading this manual. These resources generally focus on how to use the language, rather than how a VHDL-compliant tool is required to behave.<br />\n At the time of its publication, this document was the authoritative definition of VHDL. From time to time, it may become necessary to correct and/or clarify portions of this standard. Such corrections and clarifications may be published in separate documents. Such documents modify this standard at the time of their publication and remain in effect until superseded by subsequent documents or until the standard is officially revised. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard VHDL Language Reference Manual" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#121548 …} #channels: Doctrine\ORM\PersistentCollection {#121541 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#121545 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#121543 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#121555 …} -apiLastModifiedAt: DateTime @1754517600 {#121514 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#121563 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @770853600 {#121534 : 1994-06-06 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1076" -bookCollection: "" -pageCount: 288 -documents: Doctrine\ORM\PersistentCollection {#121554 …} -favorites: Doctrine\ORM\PersistentCollection {#121552 …} } "layout" => "vertical" "showPrice" => true "showStatusBadges" => true "additionalClasses" => "product__teaser--with-grey-border" "hasStretchedLink" => true "hoverType" => "shadow" "linkLabel" => "See more" ] |
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| Attributes | [] |
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| Component | App\Twig\Components\ProductCard {#121607 +product: App\Entity\Product\Product {#121515 #id: 9093 #code: "IEEE00001611" #attributes: Doctrine\ORM\PersistentCollection {#121539 …} #variants: Doctrine\ORM\PersistentCollection {#121537 …} #options: Doctrine\ORM\PersistentCollection {#121532 …} #associations: Doctrine\ORM\PersistentCollection {#121535 …} #createdAt: DateTime @1751037965 {#121528 : 2025-06-27 17:26:05.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#121521 : 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#121550 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#121648 #locale: "en_US" #translatable: App\Entity\Product\Product {#121515} #id: 31381 #name: "IEEE 1076:1993" #slug: "ieee-1076-1993-ieee00001611-240745" #description: """ Revision Standard - Superseded.<br />\n Aiding in the comprehension and use of IEEE VHDL, this unique product offers a comprehensive & reliable tutorial on VHDL - not available anywhere else. An enhancement to IEEE Std 1076-1993, the interactive tutorial is organized into four modules designed to incrementally add to the user's understanding of VHDL and it's applications. This hands-on tutorial shows clear links between the many levels and layers of VHDL and provides actual examples of VHDL implementation, making it an indispensible tool for VHDL product development and users.<br />\n \t\t\t\t<br />\n The intent of this standard is to define VHDL accurately. Its primary audiences are the implementor of tools 5 supporting the language and the advanced user of the language. Other users are encouraged to use commercially available books, tutorials, and classes to learn the language in some detail prior to reading this manual. These resources generally focus on how to use the language, rather than how a VHDL-compliant tool is required to behave.<br />\n At the time of its publication, this document was the authoritative definition of VHDL. From time to time, it may become necessary to correct and/or clarify portions of this standard. Such corrections and clarifications may be published in separate documents. Such documents modify this standard at the time of their publication and remain in effect until superseded by subsequent documents or until the standard is officially revised. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard VHDL Language Reference Manual" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#121548 …} #channels: Doctrine\ORM\PersistentCollection {#121541 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#121545 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#121543 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#121555 …} -apiLastModifiedAt: DateTime @1754517600 {#121514 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#121563 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @770853600 {#121534 : 1994-06-06 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1076" -bookCollection: "" -pageCount: 288 -documents: Doctrine\ORM\PersistentCollection {#121554 …} -favorites: Doctrine\ORM\PersistentCollection {#121552 …} } +layout: "vertical" +showPrice: true +showStatusBadges: true +additionalClasses: "product__teaser--with-grey-border" +linkLabel: "See more" +imageFilter: "product_thumbnail_teaser" +hasStretchedLink: true +backgroundColor: "white" +hoverType: "shadow" } |
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| ProductState | App\Twig\Components\ProductState | 96.0 MiB | 0.19 ms | |
|---|---|---|---|---|
| Input props | [ "product" => App\Entity\Product\Product {#121515 #id: 9093 #code: "IEEE00001611" #attributes: Doctrine\ORM\PersistentCollection {#121539 …} #variants: Doctrine\ORM\PersistentCollection {#121537 …} #options: Doctrine\ORM\PersistentCollection {#121532 …} #associations: Doctrine\ORM\PersistentCollection {#121535 …} #createdAt: DateTime @1751037965 {#121528 : 2025-06-27 17:26:05.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#121521 : 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#121550 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#121648 #locale: "en_US" #translatable: App\Entity\Product\Product {#121515} #id: 31381 #name: "IEEE 1076:1993" #slug: "ieee-1076-1993-ieee00001611-240745" #description: """ Revision Standard - Superseded.<br />\n Aiding in the comprehension and use of IEEE VHDL, this unique product offers a comprehensive & reliable tutorial on VHDL - not available anywhere else. An enhancement to IEEE Std 1076-1993, the interactive tutorial is organized into four modules designed to incrementally add to the user's understanding of VHDL and it's applications. This hands-on tutorial shows clear links between the many levels and layers of VHDL and provides actual examples of VHDL implementation, making it an indispensible tool for VHDL product development and users.<br />\n \t\t\t\t<br />\n The intent of this standard is to define VHDL accurately. Its primary audiences are the implementor of tools 5 supporting the language and the advanced user of the language. Other users are encouraged to use commercially available books, tutorials, and classes to learn the language in some detail prior to reading this manual. These resources generally focus on how to use the language, rather than how a VHDL-compliant tool is required to behave.<br />\n At the time of its publication, this document was the authoritative definition of VHDL. From time to time, it may become necessary to correct and/or clarify portions of this standard. Such corrections and clarifications may be published in separate documents. Such documents modify this standard at the time of their publication and remain in effect until superseded by subsequent documents or until the standard is officially revised. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard VHDL Language Reference Manual" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#121548 …} #channels: Doctrine\ORM\PersistentCollection {#121541 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#121545 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#121543 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#121555 …} -apiLastModifiedAt: DateTime @1754517600 {#121514 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#121563 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @770853600 {#121534 : 1994-06-06 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1076" -bookCollection: "" -pageCount: 288 -documents: Doctrine\ORM\PersistentCollection {#121554 …} -favorites: Doctrine\ORM\PersistentCollection {#121552 …} } ] |
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| Attributes | [ "showFullLabel" => false ] |
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| Component | App\Twig\Components\ProductState {#121650 +product: App\Entity\Product\Product {#121515 #id: 9093 #code: "IEEE00001611" #attributes: Doctrine\ORM\PersistentCollection {#121539 …} #variants: Doctrine\ORM\PersistentCollection {#121537 …} #options: Doctrine\ORM\PersistentCollection {#121532 …} #associations: Doctrine\ORM\PersistentCollection {#121535 …} #createdAt: DateTime @1751037965 {#121528 : 2025-06-27 17:26:05.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#121521 : 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#121550 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#121648 #locale: "en_US" #translatable: App\Entity\Product\Product {#121515} #id: 31381 #name: "IEEE 1076:1993" #slug: "ieee-1076-1993-ieee00001611-240745" #description: """ Revision Standard - Superseded.<br />\n Aiding in the comprehension and use of IEEE VHDL, this unique product offers a comprehensive & reliable tutorial on VHDL - not available anywhere else. An enhancement to IEEE Std 1076-1993, the interactive tutorial is organized into four modules designed to incrementally add to the user's understanding of VHDL and it's applications. This hands-on tutorial shows clear links between the many levels and layers of VHDL and provides actual examples of VHDL implementation, making it an indispensible tool for VHDL product development and users.<br />\n \t\t\t\t<br />\n The intent of this standard is to define VHDL accurately. Its primary audiences are the implementor of tools 5 supporting the language and the advanced user of the language. Other users are encouraged to use commercially available books, tutorials, and classes to learn the language in some detail prior to reading this manual. These resources generally focus on how to use the language, rather than how a VHDL-compliant tool is required to behave.<br />\n At the time of its publication, this document was the authoritative definition of VHDL. From time to time, it may become necessary to correct and/or clarify portions of this standard. Such corrections and clarifications may be published in separate documents. Such documents modify this standard at the time of their publication and remain in effect until superseded by subsequent documents or until the standard is officially revised. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard VHDL Language Reference Manual" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#121548 …} #channels: Doctrine\ORM\PersistentCollection {#121541 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#121545 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#121543 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#121555 …} -apiLastModifiedAt: DateTime @1754517600 {#121514 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#121563 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @770853600 {#121534 : 1994-06-06 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1076" -bookCollection: "" -pageCount: 288 -documents: Doctrine\ORM\PersistentCollection {#121554 …} -favorites: Doctrine\ORM\PersistentCollection {#121552 …} } +appearance: "state-suspended" +labels: [ "Superseded" ] -stateAttributeCode: "state" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …} } |
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| ProductMostRecent | App\Twig\Components\ProductMostRecent | 96.0 MiB | 0.69 ms | |
|---|---|---|---|---|
| Input props | [ "product" => App\Entity\Product\Product {#121515 #id: 9093 #code: "IEEE00001611" #attributes: Doctrine\ORM\PersistentCollection {#121539 …} #variants: Doctrine\ORM\PersistentCollection {#121537 …} #options: Doctrine\ORM\PersistentCollection {#121532 …} #associations: Doctrine\ORM\PersistentCollection {#121535 …} #createdAt: DateTime @1751037965 {#121528 : 2025-06-27 17:26:05.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#121521 : 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#121550 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#121648 #locale: "en_US" #translatable: App\Entity\Product\Product {#121515} #id: 31381 #name: "IEEE 1076:1993" #slug: "ieee-1076-1993-ieee00001611-240745" #description: """ Revision Standard - Superseded.<br />\n Aiding in the comprehension and use of IEEE VHDL, this unique product offers a comprehensive & reliable tutorial on VHDL - not available anywhere else. An enhancement to IEEE Std 1076-1993, the interactive tutorial is organized into four modules designed to incrementally add to the user's understanding of VHDL and it's applications. This hands-on tutorial shows clear links between the many levels and layers of VHDL and provides actual examples of VHDL implementation, making it an indispensible tool for VHDL product development and users.<br />\n \t\t\t\t<br />\n The intent of this standard is to define VHDL accurately. Its primary audiences are the implementor of tools 5 supporting the language and the advanced user of the language. Other users are encouraged to use commercially available books, tutorials, and classes to learn the language in some detail prior to reading this manual. These resources generally focus on how to use the language, rather than how a VHDL-compliant tool is required to behave.<br />\n At the time of its publication, this document was the authoritative definition of VHDL. From time to time, it may become necessary to correct and/or clarify portions of this standard. Such corrections and clarifications may be published in separate documents. Such documents modify this standard at the time of their publication and remain in effect until superseded by subsequent documents or until the standard is officially revised. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard VHDL Language Reference Manual" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#121548 …} #channels: Doctrine\ORM\PersistentCollection {#121541 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#121545 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#121543 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#121555 …} -apiLastModifiedAt: DateTime @1754517600 {#121514 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#121563 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @770853600 {#121534 : 1994-06-06 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1076" -bookCollection: "" -pageCount: 288 -documents: Doctrine\ORM\PersistentCollection {#121554 …} -favorites: Doctrine\ORM\PersistentCollection {#121552 …} } ] |
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| Attributes | [] |
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| Component | App\Twig\Components\ProductMostRecent {#121727 +product: App\Entity\Product\Product {#121515 #id: 9093 #code: "IEEE00001611" #attributes: Doctrine\ORM\PersistentCollection {#121539 …} #variants: Doctrine\ORM\PersistentCollection {#121537 …} #options: Doctrine\ORM\PersistentCollection {#121532 …} #associations: Doctrine\ORM\PersistentCollection {#121535 …} #createdAt: DateTime @1751037965 {#121528 : 2025-06-27 17:26:05.0 Europe/Paris (+02:00) } #updatedAt: DateTime @1754607611 {#121521 : 2025-08-08 01:00:11.0 Europe/Paris (+02:00) } #enabled: true #translations: Doctrine\ORM\PersistentCollection {#121550 …} #translationsCache: [ "en_US" => App\Entity\Product\ProductTranslation {#121648 #locale: "en_US" #translatable: App\Entity\Product\Product {#121515} #id: 31381 #name: "IEEE 1076:1993" #slug: "ieee-1076-1993-ieee00001611-240745" #description: """ Revision Standard - Superseded.<br />\n Aiding in the comprehension and use of IEEE VHDL, this unique product offers a comprehensive & reliable tutorial on VHDL - not available anywhere else. An enhancement to IEEE Std 1076-1993, the interactive tutorial is organized into four modules designed to incrementally add to the user's understanding of VHDL and it's applications. This hands-on tutorial shows clear links between the many levels and layers of VHDL and provides actual examples of VHDL implementation, making it an indispensible tool for VHDL product development and users.<br />\n \t\t\t\t<br />\n The intent of this standard is to define VHDL accurately. Its primary audiences are the implementor of tools 5 supporting the language and the advanced user of the language. Other users are encouraged to use commercially available books, tutorials, and classes to learn the language in some detail prior to reading this manual. These resources generally focus on how to use the language, rather than how a VHDL-compliant tool is required to behave.<br />\n At the time of its publication, this document was the authoritative definition of VHDL. From time to time, it may become necessary to correct and/or clarify portions of this standard. Such corrections and clarifications may be published in separate documents. Such documents modify this standard at the time of their publication and remain in effect until superseded by subsequent documents or until the standard is officially revised. """ #metaKeywords: null #metaDescription: null #shortDescription: "IEEE Standard VHDL Language Reference Manual" -notes: "Superseded" } ] #currentLocale: "en_US" #currentTranslation: null #fallbackLocale: "en_US" #variantSelectionMethod: "match" #productTaxons: Doctrine\ORM\PersistentCollection {#121548 …} #channels: Doctrine\ORM\PersistentCollection {#121541 …} #mainTaxon: Proxies\__CG__\App\Entity\Taxonomy\Taxon {#7311 …} #reviews: Doctrine\ORM\PersistentCollection {#121545 …} #averageRating: 0.0 #images: Doctrine\ORM\PersistentCollection {#121543 …} -supplier: Proxies\__CG__\App\Entity\Supplier\Supplier {#7325 …} -subscriptionCollections: Doctrine\ORM\PersistentCollection {#121555 …} -apiLastModifiedAt: DateTime @1754517600 {#121514 : 2025-08-07 00:00:00.0 Europe/Paris (+02:00) } -lastUpdatedAt: DateTime @1578006000 {#121563 : 2020-01-03 00:00:00.0 Europe/Paris (+01:00) } -author: "" -publishedAt: DateTime @770853600 {#121534 : 1994-06-06 00:00:00.0 Europe/Paris (+02:00) } -releasedAt: null -confirmedAt: null -canceledAt: null -edition: null -coreDocument: "1076" -bookCollection: "" -pageCount: 288 -documents: Doctrine\ORM\PersistentCollection {#121554 …} -favorites: Doctrine\ORM\PersistentCollection {#121552 …} } +label: "Historical" +icon: "historical" -mostRecentAttributeCode: "most_recent" -localeContext: Sylius\Component\Locale\Context\CompositeLocaleContext {#1833 …} } |
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